CN102468178B - Method for manufacturing transistor - Google Patents
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- CN102468178B CN102468178B CN201010551481.7A CN201010551481A CN102468178B CN 102468178 B CN102468178 B CN 102468178B CN 201010551481 A CN201010551481 A CN 201010551481A CN 102468178 B CN102468178 B CN 102468178B
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Abstract
The invention provides a method for manufacturing a transistor. The method comprises the following steps of: providing a semiconductor substrate, wherein a doping trap is formed inside the semiconductor substrate; sequentially forming a dielectric layer and a polysilicon layer on the semiconductor substrate; performing at least one ion implantation on the polysilicon layer, wherein during the at least one ion implantation, the conductive type of the doped ions in one ion implantation is consistent with the type of the transistor; etching the polysilicon layer to form a grid; etching the dielectric layer to form a grid dielectric layer; forming side walls on two sides of the grid; and forming a source region and a drain region inside the semiconductor substrate on the two sides of the grid by taking the grid and the side walls as masks. By the method, the grid resistance of the transistor is reduced, the RC time constant of the transistor is reduced, the speed of the transistor is improved, and the power consumption of the transistor is reduced.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly transistorized manufacture method.
Background technology
Metal-oxide-semicondutor (MOS) transistor is the most basic device during semiconductor is manufactured, and it is widely used in various integrated circuits, and the doping type difference during according to main charge carrier and manufacture, is divided into NMOS and PMOS transistor.
Prior art provides a kind of manufacture method of MOS transistor.Please refer to the manufacture method cross-sectional view of the MOS transistor of the prior art shown in Fig. 1 to Fig. 3.
Please refer to Fig. 1, Semiconductor substrate 100 is provided, at the interior formation isolation structure 101 of described Semiconductor substrate 100, the Semiconductor substrate 100 between described isolation structure 101 is active area, forms dopant well (not shown) in described active area.
Then, form successively gate dielectric layer 102 and grid 103 in the Semiconductor substrate 100 between described isolation structure 101, described gate dielectric layer 102 and grid 103 form grid structure.
Continue with reference to figure 1, carry out oxidation technology, form the oxide layer 104 that covers described grid structure.
With reference to figure 2, in the Semiconductor substrate of grid structure both sides, form successively source/drain extension region 105, described source/drain extension region 105 forms by light dope Implantation.
With reference to figure 3, in the Semiconductor substrate of grid structure both sides, form the side wall 111 of grid structure.Taking described grid structure as mask, carry out source/drain ion and inject (S/D implant), in the interior formation of Semiconductor substrate 100 source region 112 and the drain region 113 of grid structure both sides.
In the Chinese patent application that is CN101789447A at publication number, can find more information about prior art.
Find in practice, the response device speed of the MOS transistor that existing method is made is slower, and the power consumption of device is bigger than normal.
Summary of the invention
The problem that the present invention solves has been to provide a kind of transistor and preparation method thereof, has improved the response speed of device, has reduced the power consumption of device.
For addressing the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, is formed with dopant well;
In described Semiconductor substrate, form successively dielectric layer and polysilicon layer;
Described polysilicon layer is carried out at least primary ions and inject, in described Implantation at least one times, once the conduction type of the doping ion of Implantation is consistent with transistorized type;
Polysilicon layer described in etching, forms grid;
Dielectric layer described in etching, forms gate dielectric layer;
Form side wall in described grid both sides;
Taking described grid and side wall as mask, in the Semiconductor substrate of described grid both sides, form source region and drain region.
Alternatively, described Implantation is at least one times that primary ions is injected, twice Implantation or three secondary ions inject, described primary ions is injected to the first Implantation, described twice Implantation is that the first Implantation and the second Implantation or described twice Implantation are the first Implantation and the 3rd Implantation, described three secondary ions are injected to the first Implantation, the second Implantation and the 3rd Implantation, the conduction type of the doping ion of described the first Implantation is consistent with transistorized type, the atomic weight of the doping ion of described the second Implantation is greater than the atomic weight of silicon, the defect that the doping ion of described the 3rd Implantation produces in described polysilicon layer for adsorbing described the first Implantation and the second Implantation.
Alternatively, if described transistor is nmos pass transistor, the doping ion of described the first Implantation is phosphonium ion or arsenic ion;
If described transistor is PMOS transistor, described the first Implantation doping ion be boron ion or boron fluoride ion.
Alternatively, if the doping ion of described the first Implantation is phosphonium ion, its energy range is 3～10KeV, and dosage range is 1E15～5E15/cm
2;
If the doping ion of described the first Implantation is arsenic ion, its energy range is 5～15KeV, and dosage range is 9E14～6E15/cm
2;
If the doping ion of described the first Implantation is boron ion, its energy range is 1～10KeV, and dosage range is 1E15～5E15/cm
2;
If the doping ion of described the first Implantation is boron fluoride, its energy range is 3～18KeV, and dosage range is 1E15～5E15/cm
2.
Alternatively, described the second Implantation carries out prior to described the first Implantation.
Alternatively, the degree of depth of described the second Implantation is more than or equal to the degree of depth of the first Implantation.
Alternatively, the doping ion of described the second Implantation is germanium ion, antimony ion or bismuth ion.
Alternatively, if the doping ion of described the second Implantation is antimony ion, its energy range is 20～100KeV, and dosage range is 5E14～2E15/cm
2;
If the doping ion of described the second Implantation is germanium ion, its energy range is 10～80KeV, and dosage range is 6E14～7E15/cm
2;
If the doping ion of described the second Implantation is bismuth ion, its energy range is 50～130KeV, and dosage range is 1E14～5E15/cm
2.
Alternatively, the degree of depth of described the 3rd Implantation is greater than the degree of depth of described the second Implantation, and the degree of depth of described the second Implantation is greater than the degree of depth of described the first Implantation.
Alternatively, the doping ion of described the 3rd Implantation is carbon ion, nitrogen ion or fluorine ion.
Alternatively, if the doping ion of described the 3rd Implantation is carbon ion, its energy range is 3～12KeV, and dosage range is 1E14～1E15/cm
2;
If the doping ion of described the 3rd Implantation is nitrogen ion, its energy range is 5～20KeV, and dosage range is 2E14～3E15/cm
2;
If the doping ion of described the 3rd Implantation is fluorine ion, its energy range is 1～5KeV, and dosage range is 5E13～3E14/cm
2.
Alternatively, the thickness range of described polysilicon layer is 500～5000 dusts.
Compared with prior art, the present invention has the following advantages:
The polysilicon layer of the present invention in Semiconductor substrate carries out at least primary ions and injects, in described Implantation at least one times, once the conduction type of the doping ion of Implantation is consistent with transistorized type, then, polysilicon layer described in etching, form grid, then,, taking grid and side wall as mask, in the Semiconductor substrate of grid structure both sides, form source region and drain region.In forming source region and drain region, polysilicon gate being carried out to Implantation with prior art compares, the present invention has strengthened the dosage of the doping ion in grid, thereby reduce transistorized resistance, thereby reduce the RC time constant of device, improve the response speed of device, also reduced the power consumption of device;
Further optimally, described Implantation is at least one times that primary ions is injected, twice Implantation or three secondary ions inject, described primary ions is injected to the first Implantation, described twice Implantation is that the first Implantation and the second Implantation or described twice Implantation are the first Implantation and the 3rd Implantation, described three secondary ions are injected to the first Implantation, the second Implantation and the 3rd Implantation, the conduction type of the doping ion of described the first Implantation is consistent with transistorized type, the atomic weight of the doping ion of described the second Implantation is greater than the atomic weight of silicon, the defect that the doping ion of described the 3rd Implantation produces in described polysilicon layer for adsorbing described the first Implantation and the second Implantation.The atomic weight of the doping ion of described the second Implantation is greater than the atomic weight of silicon, thereby at the doping ion of described the second Implantation by the lattice disturbance of polysilicon layer, make described polysilicon layer arrange and become amorphous grillages cloth from neat lattice, increase the resistance that the doping ion of the first Implantation is subject in described polysilicon layer, in described polysilicon layer, there is channeling effect (channel effect) in the doping ion that prevents described the first Implantation, the degree of depth of the doping ion of avoiding described the first Implantation in described polysilicon layer is uncontrolled, thereby prevent the doping doping ion penetration polysilicon layer of described the first Implantation, spread to Semiconductor substrate, and the doping ion damaged of described the second Implantation the lattice structure of described polysilicon layer, thereby in described polysilicon layer, produce downward pressure, be conducive to improve the migration rate of transistorized charge carrier, the doping Implantation of described the 3rd Implantation can be eliminated the defect forming in polysilicon layer, thereby prevent that the doping ion of described the first Implantation in described polysilicon layer and/or the second doping ion injecting from moving along with the movement of described defect, reduces transistorized oxidation-enhanced diffusion effect.
Brief description of the drawings
Fig. 1～Fig. 3 is the preparation method of transistor cross-sectional view of prior art;
Fig. 4 is the preparation method of transistor schematic flow sheet of the embodiment of the present invention;
Fig. 5～Fig. 9 is the preparation method of transistor cross-sectional view of one embodiment of the invention.
Embodiment
The transistorized response speed that existing method is made is slower, and the power consumption of device is larger.Study discovery through inventor, because the transistorized resistance that prior art is made is bigger than normal, caused transistorized response speed slower, the power consumption of device is less.
Particularly, with reference to figure 3, prior art is carrying out Implantation while forming described source region 112 and drain region 113, also described grid 103 has been carried out to Implantation to reduce the resistance of described grid 103, but the underdosage of described Implantation, to reduce the resistance of described grid, need to be adjusted the parameter of the doping Implantation in grid 103.
Inventor also finds, along with reducing of transistor size, the super shallow junction technology of employing in described source region 112 and drain region 113 is made and (is adopted low energy ion to inject and form described source region 112 and drain region 113, the energy that described low energy ion injects is lower, the degree of depth of the doping ion forming is more shallow), therefore, the degree of depth of the doping ion in described grid 103 also shoals, this has strengthened the activation difficulty of the doping ion in described grid 103, thereby can make the doping ion in grid 103 be difficult to effective activation, cause the resistance of grid 103 bigger than normal.
Inventor considers, strengthen the energy of the Implantation of described grid 103, thereby increase the degree of depth of the doping ion of described grid 103, can improve the ratio of the activation of the doping ion in described grid 103, reduce the resistance of described grid 103, but strengthen the energy of the Implantation of described grid 103, easily cause the doping ion in grid 103 to spread to Semiconductor substrate 100 through the gate dielectric layer 102 of below, cause leakage current, and strengthen the degree of depth of the Implantation of described grid 103, need to adopt special Implantation step, in order to avoid described special Implantation step affects the degree of depth in source region 112 and drain region 113.This can need special mask plate, and this mask plate protects described source region 112 and drain region 113, only exposes described grid 103, and this can increase process costs.
Inventor considers, increases the dosage of the Implantation step of grid 103, also can reduce the resistance of described grid 103, but due to the special mask plate of needs, thereby also increase process costs.
Based on above-mentioned situation, inventor considers to carry out Implantation at the polysilicon layer without etch step,, after described polysilicon layer deposition, it is carried out to Implantation; Then described polysilicon layer is carried out to etching, form grid, thereby without special mask plate, and with existing transistor fabrication process compatible.
Particularly, transistorized manufacture method provided by the invention please refer to Fig. 4, and described method comprises:
Step S1, provides Semiconductor substrate;
Step S2 forms successively dielectric layer and polysilicon layer in described Semiconductor substrate;
Step S3, carries out at least primary ions to described polysilicon layer and injects, and in described Implantation at least one times, once the conduction type of the doping ion of Implantation is consistent with transistorized type;
Step S4, polysilicon layer described in etching, forms grid;
Step S5, dielectric layer described in etching, forms gate dielectric layer;
Step S6, forms side wall in described grid both sides;
Step S7 taking described grid and side wall as mask, forms source region and drain region in the Semiconductor substrate of described grid both sides.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.
For technical scheme of the present invention is described better, incorporated by reference to the transistorized manufacture method cross-sectional view of the one embodiment of the invention shown in Fig. 5～Fig. 9.
First, please refer to Fig. 5, Semiconductor substrate 200 is provided, in described Semiconductor substrate 200, be formed with isolation structure 201, is dopant well (not shown) between adjacent isolation structure 201.
The material of described Semiconductor substrate 200 can be silicon, germanium silicon or other semiconductor material.In the present embodiment, the material of described Semiconductor substrate 200 is silicon.
Described isolation structure 201 is for isolating between device, and described isolation structure 201 can be fleet plough groove isolation structure or an oxidation isolation structure.
Described dopant well forms by Implantation.The Implantation that forms described dopant well is identical with existing technique, as those skilled in the art's known technology, does not explain at this.
Then,, please continue to refer to Fig. 5, in described Semiconductor substrate 200, form dielectric layer 202.Described dielectric layer 202 will form transistorized gate dielectric layer by etch step follow-up.The material of described dielectric layer 202 can be silica, silicon nitride, silicon oxynitride, carborundum etc., is preferably silica.
Then, continue with reference to figure 5, on described dielectric layer 202, form polysilicon layer 203.Described polysilicon layer 203 can utilize chemical vapor deposition method to make, and also can utilize epitaxial deposition process to make.Described polysilicon layer 203 will form transistorized grid by etching technics in subsequent step.
As an embodiment, the thickness range of described polysilicon layer 203 is 500～5000 dusts, is preferably 800～4000 dusts, for example 1000 dusts, 2000 dusts, 3000 dusts or 4000 dusts.
Continue with reference to figure 5, described polysilicon layer 203 is carried out to the first Implantation, the doping ion of described the first Implantation is the first doping ion, and described the first doping conduction type of ion and the type of transistorized conducting channel are consistent.Particularly, if described transistor is nmos pass transistor, the type of its conducting channel is N-type, and described the first doping ion is N-type doping ion; If described transistor is PMOS transistor, the type of its conducting channel is P type, and described the first doping ion is P type doping ion.
N-type doping ion of the present invention can be phosphonium ion, arsenic ion, and described P type doping ion can be boron ion, indium ion or boron fluoride ion.
Inventor's discovery, the technological parameter of described the first Implantation has impact to improving resistance, and no matter energy or the dosage of doping ion are excessive or too small, all can have impact to transistorized parameter.For example, if dosage or the energy of described the first Implantation are excessive, easily cause channeling effect, the degree of depth of described doping ion in described polysilicon layer 203 is uncontrolled, thereby may cause that doping ion arrives Semiconductor substrate 200 through described dielectric layer 202, causes leakage current; Dosage or the energy of described the first Implantation are too small, can make the doping ion in described polysilicon layer 203 be difficult to activate, thereby cannot play the effect that reduces the final resistance forming.
As preferred embodiment, the parameter of described the first Implantation is set to:
If described doping ion is phosphonium ion, the energy range of its Implantation is 3～10KeV, for example, be 3KeV, 5KeV or 10KeV, and the dosage range of its Implantation is 1E15～5E15/cm
2;
If described doping ion is arsenic ion, the energy range of its Implantation is 5～15KeV, for example, be 5KeV, 10KeV or 15KeV, and the dosage range of its Implantation is 9E14～6E15/cm
2;
If described doping ion is boron ion, the energy range of its Implantation for being 1～10KeV, for example, is 1KeV, 5KeV or 10KeV, and the dosage range of its Implantation is 1E15～5E15/cm
2;
If described doping ion is boron difluoride ion, the energy range of its Implantation for being 3～18KeV, for example, is 3KeV, 9KeV or 18KeV, and the dosage range of its Implantation is 1E15～5E15/cm
2.
While carrying out due to described the first Implantation, the lattice structure of described polysilicon layer 203 is the lattice structure that rule is arranged, described the first doping ion may be in the interior generation channeling effect of described polysilicon layer 203, thereby makes the degree of depth of described the first doping ion uncontrollable.In order to reduce channeling effect, as the preferred embodiments of the present invention, carrying out before the first Implantation, described polysilicon layer 203 is carried out to the second Implantation, the doping ion of described the second Implantation is the second doping ion, the atomic weight of described the second doping ion is greater than the atomic weight of described silicon, to destroy the lattice structure of described polysilicon layer 203, make in the time carrying out the first Implantation, the resistance that described the first doping ion is subject in described polysilicon layer 203 strengthens, thereby avoids the appearance of channeling effect.Because the atomic weight of described the second doping ion is greater than the atomic weight of silicon, described the second doping ion is in by the lattice disturbance of described polysilicon layer 203, can also produce the pressure towards Semiconductor substrate 200 from described polysilicon layer 203, described pressure is conducive to improve the migration rate of transistorized charge carrier, improves transistorized performance.
As preferred embodiment, the degree of depth of described the second Implantation is more than or equal to the degree of depth of the first Implantation, thereby described the second Implantation, by the lattice disturbance of the polysilicon layer of adequate thickness 203, can effectively be avoided the appearance of channeling effect.
As an embodiment, described the second doping ion is antimony, and the energy range of described the second Implantation is 20～100KeV, and dosage range is 5E14～2E15/cm
2;
As another embodiment, described the second doping ion is germanium ion, and the energy range of described the second Implantation is 10～80KeV, and dosage range is 6E14～7E15/cm
2;
As an embodiment again, described the second ion doping ion is bismuth ion, and the energy range of described the second Implantation is 50～130KeV, and dosage range is 1E14～5E15/cm
2.
Due to described the first Implantation, the second implantation membership causes lattice damage and defect in described polysilicon layer 203, described defect may move in subsequent anneal step, and drive the first doping ion and second doping ionic transfer, thereby cause oxidation-enhanced diffusion effect, cause leakage current, make the reliability decrease of grid, therefore, as preferred embodiment, also need described polysilicon layer 203 to carry out the 3rd Implantation, the doping ion of described the 3rd Implantation is the 3rd doping ion, described the 3rd doping ion is for adsorbing the defect in polysilicon layer 203, defect in described polysilicon layer 203 is pricked surely, prevent the appearance of oxidation-enhanced diffusion effect.
As the preferred embodiments of the present invention, the degree of depth of described the 3rd Implantation is greater than the degree of depth of described the second Implantation, the degree of depth of described the second Implantation is greater than the degree of depth of described the first Implantation, thereby can effectively described the first Implantation and the second Implantation be pricked surely in the defect of described polysilicon layer 203 interior generations, prevent that described defect from moving to dielectric layer 202.
As an embodiment, described the 3rd doping ion is carbon ion, nitrogen ion or fluorine ion.
In order to obtain the effect of the defect in the described polysilicon layer 203 of better absorption, inventor is optimized setting to the parameter of the 3rd Implantation, and design parameter is as follows:
In the time that described the 3rd doping ion is carbon ion, the energy range of described the 3rd Implantation is 3～12KeV, and dosage range is 1E14～1E15/cm
2;
In the time that described the 3rd doping ion is nitrogen ion, the energy range of described the 3rd Implantation is 5～20KeV, and dosage range is 2E14～3E15/cm
2;
In the time that described the 3rd ion doping ion is fluorine ion, the energy range of described the 3rd Implantation is 1～5KeV, and dosage range is 5E13～3E14/cm
2.
It should be noted that, above-mentioned the first doping ion, the second doping ion, the 3rd doping ion can utilize special annealing steps to activate, but may increase the heat budget of Semiconductor substrate 200, as preferred embodiment, described the first doping ion, the second doping ion, the 3rd doping ion activate in the annealing steps in follow-up formation light doping section or source region, drain region, to save processing step, reduce the heat budget that Semiconductor substrate 200 is caused.
In other embodiments of the invention, can also only carry out described the first Implantation to described polysilicon layer 203, can reduce like this resistance of described polysilicon layer 203; Or described polysilicon layer 203 is carried out to described the first Implantation and the 3rd Implantation, like this in reducing the resistance of described polysilicon layer 203, can also adsorb the defect in polysilicon layer 203, prevent that the doping ion in described polysilicon layer 203 from spreading along with the diffusion of described defect, reduces oxidation-enhanced diffusion effect; Or described polysilicon layer 203 is carried out to the first Implantation and the second Implantation, can prevent that like this doping ion of the first Implantation is in the interior channeling effect that occurs of described polysilicon layer 203, and reduce the resistance of described polysilicon layer 203.
Then, please refer to Fig. 6, polysilicon layer 203 described in etching, forms grid 220.Described grid 220 is in Semiconductor substrate 200 between described isolation structure 201.
The lithographic method of described polysilicon layer 203 is identical with existing technique, as those skilled in the art's known technology, is not described in detail at this.
Then, please refer to Fig. 7, dielectric layer 202 described in etching, forms gate dielectric layer 221.Described gate dielectric layer 221 and grid 220 form grid structure.
The lithographic method of described gate dielectric layer 221 is same as the prior art, as those skilled in the art's known technology, is not described in detail at this.
Then, please refer to Fig. 8, as an embodiment, in the Semiconductor substrate of described grid 220 both sides, form light doping section 213.Described light doping section 213 forms by light dope Implantation (Light dopeddrain, LDD), and the parameter of described light dope Implantation arranges same as the prior art, does not repeat at this.
After light dope Implantation, carry out annealing steps, to activate the doping ion of described light doping section 213, activate the doping ion in described grid 220 simultaneously.The described rapid thermal annealing that is annealed into.In the present embodiment, the parameter of described rapid thermal annealing is: 900～1030 degrees Celsius of temperature, 1～30 second time.
Then, please refer to Fig. 9, described grid 220 is carried out to oxidation technology, in the outside oxide layer 204 that forms of described grid 220, to protect described grid 220.
Then, form side wall 211 in described grid 220 both sides.As an embodiment, the material of described side wall 211 is insulation material, for example, be the sandwich construction of silicon oxide layer, silicon nitride layer or silica-silicon-nitride and silicon oxide composition.
Then,, still with reference to figure 9, taking described grid 220 and side wall 211 as mask, carry out Implantation, in the interior formation of Semiconductor substrate 200 source region 212 and the drain region 213 of described grid 220 both sides.The parameter of described Implantation arranges same as the prior art, as those skilled in the art's known technology, is not described in detail at this.
To sum up, transistor provided by the invention and preparation method thereof, carries out the first Implantation to polysilicon layer, reduce the resistance of polysilicon layer, thereby reduce the resistance of the grid of final formation, reduced transistorized RC time constant, reduced transistorized power consumption; The present invention is also by carrying out the second Implantation to polysilicon layer, in polysilicon layer, there is channeling effect in the doping ion that prevents the first Implantation, prevent transistorized leakage current, the present invention has also eliminated in polysilicon layer by the 3rd Implantation the defect causing due to the first Implantation and the second Implantation, prevent the appearance of oxidation-enhanced diffusion effect, improved transistorized performance.
Although the present invention discloses as above with preferred embodiment, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (10)
1. a transistorized manufacture method, is characterized in that, comprising:
Semiconductor substrate is provided;
In described Semiconductor substrate, form successively dielectric layer and polysilicon layer;
Described polysilicon layer is carried out at least twice Implantation, described at least twice Implantation is that twice Implantation or three secondary ions inject, described twice Implantation is the first Implantation and the second Implantation, described three secondary ions are injected to the first Implantation, the second Implantation and the 3rd Implantation, the conduction type of the doping ion of described the first Implantation is consistent with transistorized type, the atomic weight of the doping ion of described the second Implantation is greater than the atomic weight of silicon and produces from described polysilicon layer the pressure towards Semiconductor substrate, the defect that the doping ion of described the 3rd Implantation produces in described polysilicon layer for adsorbing described the first Implantation and the second Implantation, described the second Implantation carries out prior to described the first Implantation,
Polysilicon layer described in etching, forms grid;
Dielectric layer described in etching, forms gate dielectric layer;
Form side wall in described grid both sides;
Taking described grid and side wall as mask, in the Semiconductor substrate of described grid both sides, form source region and drain region.
2. transistorized manufacture method as claimed in claim 1, is characterized in that, if described transistor is nmos pass transistor, the doping ion of described the first Implantation is phosphonium ion or arsenic ion;
If described transistor is PMOS transistor, described the first Implantation doping ion be boron ion or boron fluoride ion.
3. transistorized manufacture method as claimed in claim 2, is characterized in that, if the doping ion of described the first Implantation is phosphonium ion, its energy range is 3～10KeV, and dosage range is 1E15～5E15/cm
2;
If the doping ion arsenic ion of described the first Implantation, its energy range is 5～15KeV, and dosage range is 9E14～6E15/cm
2;
If the doping ion of described the first Implantation is boron ion, its energy range is 1～10KeV, and dosage range is 1E15～5E15/cm
2;
If the doping ion of described the first Implantation is boron fluoride ion, its energy range is 3～18KeV, and dosage range is 1E15～5E15/cm
2.
4. transistorized manufacture method as claimed in claim 1, is characterized in that, the degree of depth of described the second Implantation is more than or equal to the degree of depth of the first Implantation.
5. transistorized manufacture method as claimed in claim 1, is characterized in that, the doping ion of described the second Implantation is germanium ion, antimony ion or bismuth ion.
6. transistorized manufacture method as claimed in claim 1, is characterized in that, if the doping ion of described the second Implantation is antimony ion, its energy range is 20～100KeV, and dosage range is 5E14～2E15/cm
2;
If the doping ion of described the second Implantation is germanium ion, its energy range is 10～80KeV, and dosage range is 6E14～7E15/cm
2;
If the doping ion of described the second Implantation is bismuth ion, its energy range is 50～130KeV, and dosage range is 1E14～5E15/cm
2.
7. transistorized manufacture method as claimed in claim 1, is characterized in that, the degree of depth of described the 3rd Implantation is greater than the degree of depth of described the second Implantation, and the degree of depth of described the second Implantation is greater than the degree of depth of described the first Implantation.
8. transistorized manufacture method as claimed in claim 1, is characterized in that, the doping ion of described the 3rd Implantation is carbon ion, nitrogen ion or fluorine ion.
9. transistorized manufacture method as claimed in claim 8, is characterized in that, if the doping ion of described the 3rd Implantation is carbon ion, its energy range is 3～12KeV, and dosage range is 1E14～1E15/cm
2; If the doping ion of described the 3rd Implantation is nitrogen ion, its energy range is 5～20KeV, and dosage range is 2E14～3E15/cm
2; If the doping ion of described the 3rd Implantation is fluorine ion, its energy range is 1～5KeV, and dosage range is 5E13～3E14/cm
2.
10. transistorized manufacture method as claimed in claim 1, is characterized in that, the thickness range of described polysilicon layer is 500～5000 dusts.
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| CN105161405A (en) * | 2015-07-30 | 2015-12-16 | 上海华力微电子有限公司 | Method for improving electrical properties of device |
| CN110112070B (en) * | 2019-04-28 | 2022-05-10 | 上海华虹宏力半导体制造有限公司 | MOS transistor and forming method thereof |
| CN113517184A (en) * | 2020-04-10 | 2021-10-19 | 中芯北方集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| CN114496760B (en) * | 2022-04-01 | 2022-07-01 | 晶芯成(北京)科技有限公司 | Forming method of MOS transistor |
| CN116419562B (en) * | 2023-06-09 | 2023-09-08 | 合肥晶合集成电路股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN116435260A (en) * | 2023-06-12 | 2023-07-14 | 合肥晶合集成电路股份有限公司 | Method for manufacturing semiconductor device |
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