CN102044438B - MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof - Google Patents
MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof Download PDFInfo
- Publication number
- CN102044438B CN102044438B CN200910197613A CN200910197613A CN102044438B CN 102044438 B CN102044438 B CN 102044438B CN 200910197613 A CN200910197613 A CN 200910197613A CN 200910197613 A CN200910197613 A CN 200910197613A CN 102044438 B CN102044438 B CN 102044438B
- Authority
- CN
- China
- Prior art keywords
- drain
- semiconductor substrate
- electrode
- gate electrode
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000002347 injection Methods 0.000 claims abstract description 28
- 239000007924 injection Substances 0.000 claims abstract description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 40
- 238000005468 ion implantation Methods 0.000 claims description 5
- 238000000034 method Methods 0.000 abstract description 33
- 230000000694 effects Effects 0.000 abstract description 19
- 230000008569 process Effects 0.000 abstract description 18
- 230000036632 reaction speed Effects 0.000 abstract description 5
- 229940090044 injection Drugs 0.000 description 19
- 238000005516 engineering process Methods 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910052787 antimony Inorganic materials 0.000 description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 239000002784 hot electron Substances 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000428 dust Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 230000035755 proliferation Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000001947 vapour-phase growth Methods 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention relates to an MOS (Metal Oxide Semiconductor) transistor and a manufacturing method thereof. The manufacturing method comprises the following steps of: providing a semiconductor substrate, wherein a gate dielectric layer and a gate electrode are sequentially formed on the semiconductor substrate, the gate electrode is provided with a first side and a second side, the semiconductor substrate at the first side of the gate electrode is a source region, and the semiconductor substrate at the second side of the gate electrode is a drain region; carrying out light doped injection on the drain region, and carrying out source electrode injection on the source region to respectively form a light doped drain electrode and a source electrode; forming side walls at two sides of the gate electrode on the gate electrode dielectric layer; and carrying out drain electrode injection on the drain region to form a drain electrode. In the invention, an LDD (Light Doped Drain) structure is formed only on the drain electrode through the local adjustment of a standard MOS transistor standard process, thereby the resistance of a conducting channel is reduced, the length of the conducting channel is lengthened, the short channel effect is lightened, and the reaction speed and the overall electrical property of the device are improved.
Description
Technical field
The present invention relates to semiconductor fabrication process, particularly a kind of MOS transistor and manufacturing approach thereof.
Background technology
With the raising of integrated circuit integrated level, device size is progressively scaled, and characteristic size has reached the 32nm magnitude at present.Metal oxide semiconductor field effect tube (MOS) is modal semiconductor device, is the elementary cell that constitutes various complicated circuits.MOS transistor basic structure comprises three main region: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode according to the type of device difference, can be divided into n type doping (NMOS) and p type doping (PMOS) through highly doped formation.
In the scaled process of device; Drain voltage does not reduce thereupon; This just causes the increase of the channel region electric field between source/drain electrode, and under the highfield effect, electronics can accelerate to the speed than much higher times of heat movement speed between twice collision; Owing to kinetic energy is called as hot electron very greatly, thereby cause thermoelectronic effect (hot electron effect).This effect belongs to the small-size effect of device, can cause that hot electron injects to gate dielectric layer, forms gate electrode electric current and substrate current, influences the reliability of device and circuit.
In order to overcome thermoelectronic effect, have multiplely to the improving one's methods of mos transistor structure, for example two injecting structure, buried channel structure, discrete grid structures, bury drain structure etc.; Wherein study morely and practical value is bigger a kind of be lightly doped drain (1ightly doped drain:LDD) structure.The effect of lightly doped drain structure is to reduce electric field, can significantly improve thermoelectronic effect.
Although the LDD structure has significant effect to reducing thermoelectronic effect, also there are some shortcomings.Such as causing the resistance between source/drain electrode to increase, saturation current is reduced, and then cause that the device reaction speed descends.In addition, the LDD structure also makes the MOS transistor manufacturing process more complicated.
In the existing integrated technique, like Fig. 1～shown in Figure 4, the manufacturing of MOS transistor mainly comprises following flow process: with reference to figure 1, at first on Semiconductor substrate 100, form gate electrode dielectric layer 110 and gate electrode 120; With reference to figure 2, then the LDD ion is carried out in source region 130 and drain region 140 and inject, and the injection ion is spread in substrate through annealing process; With reference to figure 3, form side wall 150 afterwards, carry out source/drain electrode again and inject, form device architecture as shown in Figure 4 at last.In above technology, the LDD structure is formed at source region and drain region respectively, and because the annealing effect makes the physical width of length of effective channel much smaller than gate electrode, causes short-channel effect easily.
Publication number is that 20040150014 U.S. Patent application has been cancelled the LDD structure avoiding its each item side effect in mos transistor structure, but need do bigger adjustment to technical process and parameter, cause certain difficulty to actual production.
For improving the performance of MOS transistor, need a kind of new manufacturing process of exploitation, under the situation that does not improve process complexity, alleviate or eliminate each item side effect that the LDD structure causes.
Summary of the invention
The problem that the present invention solves provides a kind of MOS transistor and manufacturing approach thereof, reduces the harmful effect that the LDD structure is brought, and improves the electric property of MOS transistor.
For addressing the above problem, the invention provides a kind of manufacturing approach of MOS transistor, comprise the following step:
Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the said Semiconductor substrate successively, said gate electrode has first side and second side, and the Semiconductor substrate of said gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region;
Light dope is carried out in said drain region inject, the source electrode injection is carried out in said source region, form lightly doped drain and source electrode respectively;
The both sides of gate electrode form side wall on said gate dielectric layer;
To the injection that drains of said drain region, form drain electrode.
Optional, saidly light dope is carried out in the drain region inject and comprise: on said Semiconductor substrate, form first photoresist layer; Graphical said first photoresist layer defines the drain region shape; With said first photoresist layer is that mask carries out the light dope injection, removes said first photoresist layer afterwards.
Optional, the source electrode injection is carried out in said source region comprised: on said Semiconductor substrate, form second photoresist layer; Graphical said second photoresist layer defines the source region shape; With said second photoresist layer is that mask carries out the source electrode injection, removes said second photoresist layer afterwards.
Optional, said drain region drained to inject to be comprised: on said Semiconductor substrate, form the 3rd photoresist layer; Graphical said the 3rd photoresist layer defines the drain region shape; With said the 3rd photoresist layer is the mask injection that drains, and removes said the 3rd photoresist layer afterwards.
Optional, said light dope ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude.
Optional, the dosage that said source electrode injects is 10
14～10
15/ cm
2The order of magnitude.
Optional, the dosage that said drain electrode is injected is 10
14～10
15/ cm
2The order of magnitude.
Optional, the ionic type that said light dope injects, source electrode injects, drain electrode is injected is arsenic or antimony.
Optional, the ionic type that said light dope injects, source electrode injects, drain electrode is injected is a boron.
Optional, the material of said gate dielectric layer is a silicon dioxide.
For addressing the above problem, the present invention also provides a kind of MOS transistor, comprising:
Semiconductor substrate;
Gate dielectric layer and gate electrode are formed on the said Semiconductor substrate successively;
Side wall is formed at the both sides of said gate electrode;
Source electrode is formed in the Semiconductor substrate of said gate electrode one side;
Drain electrode is formed in the Semiconductor substrate of said gate electrode opposite side;
The lightly doped drain structure, said lightly doped drain structure only is formed in the said drain electrode.
Optional, said light dope ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude.
Optional, the dosage that said source electrode injects is 10
14～10
15/ cm
2The order of magnitude.
Optional, the dosage that said drain electrode is injected is 10
14～10
15/ cm
2The order of magnitude.
Compared with prior art; Technique scheme has the following advantages: through the adjustment of the part on MOS transistor standard technology basis, only form the LDD structure in drain electrode, do not form the LDD structure at source electrode; Reduced the resistance of conducting channel thus; The conducting channel length that extended has alleviated short-channel effect, has improved device reaction speed and whole electrical property.
In addition, technique scheme is only done local adjustment to technological process, and production capacity and cost are not had considerable influence.
Description of drawings
Fig. 1 to Fig. 4 is the cross-sectional view of existing technology MOS transistor manufacturing approach;
Fig. 5 is the schematic flow sheet of the MOS transistor manufacturing approach of embodiment of the present invention;
Fig. 6 to Figure 11 is the cross-sectional view of the nmos pass transistor manufacturing approach of the embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed practical implementation.
Method provided by the invention is not only applicable to the manufacturing of MOS transistor, is applicable to integrated MOS transistor circuit, the particularly characteristic size MOS transistor circuit below 130nm yet.Said MOS transistor can be PMOS transistor or the nmos pass transistor among the CMOS.
Existing MOS transistor manufacturing process all forms the LDD structure in source electrode and drain electrode, because the doping content of LDD structure is low, resistance is higher relatively; Therefore the resistance of conducting channel is higher; Cause RC to postpone to increase, reduced the reaction speed of MOS transistor, influenced device performance.In addition, because all there is the LDD structure in source/drain electrode, its horizontal proliferation meeting causes the shortening of length of effective channel, causes short-channel effect, causes bad results such as puncture voltage reduction, channel leakage increase.
The inventor finds that source electrode institute making alive is all not too high generally speaking, is generally ground connection, and therefore the electric field strength of one side is limited in the source region, there is no need to form the LDD structure.As only form the LDD structure in drain electrode, can reduce channel resistance to a certain extent, and increase channel length.
Because in the present integrated technique, the process that forms the LDD structure is ion to be carried out in source/drain electrode simultaneously inject, so the LDD structure all exists at source-drain electrode.For this reason,, it is done local adjustment, only form the LDD structure,, improve the device performance of formed MOS transistor so that under the not obvious situation that influences process complexity in drain electrode based on existing MOS transistor technological process.
About the technological process adjustment to the MOS standard technology, Fig. 5 has indicated the schematic flow sheet of an embodiment of the present invention.As shown in Figure 5, execution in step S510 provides Semiconductor substrate; Be formed with gate dielectric layer and gate electrode on the said Semiconductor substrate successively; Said gate electrode has first side and second side, and the Semiconductor substrate of said gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region; Execution in step S520 carries out light dope to said drain region and injects, and source electrode is carried out in said source region inject, and forms lightly doped drain and source electrode respectively; Execution in step S530, the both sides of gate electrode form side wall on said gate dielectric layer; Execution in step S540 to the injection that drains of said drain region, forms drain electrode.
Method provided by the invention is applicable to the manufacturing of MOS single tube device in the integrated circuit; But should method of the present invention be limited in the manufacturing process of MOS single tube device; Form the MOS transistor integrated device perhaps in the situation of one-sided formation LDD structure if in other technologies, relate to, method of the present invention also can well be suitable for.
Fig. 6 to Figure 11 is the cross-sectional view of the nmos pass transistor manufacturing approach of first embodiment of the invention, is elaborated below in conjunction with Fig. 5.
With reference to Fig. 5 and Fig. 6, execution in step S510 provides Semiconductor substrate; Be formed with gate dielectric layer and gate electrode on the said Semiconductor substrate successively; Said gate electrode has first side and second side, and the Semiconductor substrate of said gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region.Specifically comprise: P type semiconductor substrate 600 is provided, certain isolation structure (not shown) is arranged on the said Semiconductor substrate 600, like silica etc.Silicon or SiGe that said Semiconductor substrate 600 can be monocrystalline, polycrystalline or non crystalline structure also can be silicon-on-insulators (SOI).The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.
Form gate dielectric layer 610 on said Semiconductor substrate 600 surfaces; Its material is a silica; Thickness is tens of to the hundreds of dust, and its deposition process can be conventional vacuum coating technology, for example boiler tube thermal oxidation; Ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, present embodiment adopts the boiler tube thermal oxidation technology.
On gate dielectric layer 610, form the gate electrode layer (not shown) then; Said gate electrode layer can be polysilicon or metal; Select n type DOPOS doped polycrystalline silicon in the present embodiment for use, its formation method is low-pressure chemical vapor phase deposition (LPCVD), and dopant ion is a phosphorus; This method is a knowledge known in those skilled in the art, and the thickness of said gate electrode layer is between hundreds of extremely several thousand dusts.Then said gate electrode layer is carried out graphically, form the gate electrode 620 of nmos pass transistor.So far, the device architecture of formation is as shown in Figure 6.Above technological process is all consistent with existing MOS transistor technological process.
After said gate electrode 620 formed, said Semiconductor substrate 600 was divided into three parts, and wherein first is positioned at the part of gate electrode below 620; Channel region for MOS transistor; Second and third part for being positioned at the part of said gate electrode 620 both sides, is respectively source region and drain region shown in I district among Fig. 6 and II district; See that from structure source region and drain region are equivalent, can distinguish source region and drain region but in physical circuit, vary in size according to applied voltage polarity.The I district is the source region in the present embodiment, and the II district is the drain region.
Like Fig. 5 and Fig. 7, shown in 8, execution in step S520 carries out light dope to said drain region and injects, and source electrode is carried out in said source region inject, and forms lightly doped drain and source electrode respectively.The light dope that at first carries out the drain region in the present embodiment injects, and is as shown in Figure 7, specifically comprises: on said Semiconductor substrate 600, form first photoresist layer, then said first photoresist layer is carried out graphically, one side forms photoresist figure 630 in the source region.Be mask with said photoresist figure 630 then, light dope carried out in the drain region inject.For the NMOS of present embodiment, injection be n type ion, for example phosphorus (P), arsenic (As).Ion implantation dosage is 10
12～10
13/ cm
2The order of magnitude injects ion energy and is 10 to 100keV, and it injects degree of depth is tens of to the hundreds of dust.After said light dope injects and accomplishes; Remove said photoresist figure 630, said Semiconductor substrate 600 is heat-treated, the injection ion in the drain region is taken place vertically and horizontal diffusion; Its part is diffused in the Semiconductor substrate 600 of gate electrode 620 belows, form lightly doped drain 640.This step is that with the difference of existing MOS technology the light dope injection only is directed against the drain region and carries out, and the source region is not related to.
After forming lightly doped drain 640, source electrode is carried out in said source region inject, with reference to Fig. 8, form second photoresist layer on said Semiconductor substrate 600 surfaces, and patterned, one side forms photoresist figure 650 in the drain region.Subsequently, be that mask carries out the ion injection to the source region with said photoresist figure 650, promptly source electrode injects.To nmos device, injecting ionic type is the n type, and like arsenic (As), antimony (Sb), it is 10 that said source electrode injects ion dose
14～10
15/ cm
2The order of magnitude injects ion energy and is 10 to 100keV, and it injects ion dose and injects high two one magnitude than said light dope.Source electrode is removed said photoresist figure 650 after injecting, and one side forms the source electrode 660 of higher-doped concentration in the source region.This moment, device architecture was as shown in Figure 8, and compared with prior art, the source electrode of present technique scheme only injects through source electrode and forms, and the light dope injection process does not relate to the source region, and the inventor is through discovering, the ion dose that source electrode is injected is chosen to be 10
14～10
15/ cm
2The order of magnitude injects ion energy and is chosen to be 10 to 100keV, and the MOS electric properties of devices is not produced obvious influence.
Need to prove that the light dope that present embodiment carries out the drain region earlier injects, in other embodiments, the source electrode that also can carry out the source region earlier injects.
With reference to Fig. 5 and Fig. 9, execution in step S530, the both sides of gate electrode form side wall on said gate dielectric layer.Specifically comprise: on the gate dielectric layer of said Semiconductor substrate 600, form the dielectric layer (not shown); Present embodiment is a silica material; Generation type can be low-pressure chemical vapor phase deposition (LPCVD); Thickness is higher than the height of said gate electrode 620, and said dielectric layer also can be selected oxide layer-silicon nitride-oxide layer (ONO) structure for use.Said dielectric layer is returned (etch back) technology at quarter, form side wall (spacer) 670 in said gate electrode 620 both sides, re-use wet etching afterwards and remove the gate dielectric layer 610 beyond the said side wall 670.As shown in Figure 9.It act as grill-protected electrode 620.
With reference to figure 5 and Figure 10, execution in step S540 to the injection that drains of said drain region, forms drain electrode.Specifically comprise: on said Semiconductor substrate 600, form the 3rd photoresist layer; And patterned, one side forms photoresist figure 680 in the source region, is that mask carries out the ion injection to the drain region with said photoresist layer 680; I.e. drain electrode is injected, and forms drain electrode 640b.The ionic type that said drain electrode is injected is identical with the source electrode injection, and the type of MOS transistor is NMOS in the present embodiment, and injecting ionic type at this is the n type, and like arsenic (As), antimony (Sb), it is 10 that ion dose is injected in said drain electrode
14～10
15/ cm
2The order of magnitude injects ion energy and is 10 to 100keV.Because the existence of side wall 670, make in the Semiconductor substrate 600 of side wall 670 belows and do not inject ion, the low concentration doping ion that forms when therefore below the said side wall 670 in drain region, only having light dope to inject, this zone is the LDD structure 640a of drain electrode 640b.The difference of above correlation step and existing technological process is: existing technology is carried out ion simultaneously to source/drain electrode and is injected; Source/drain electrode all contains the LDD structure; The Twi-lithography technology of then utilizing present embodiment realizes the selectivity of source/drain region is injected, and only in drain electrode, forms the LDD structure.
After completion is injected in said drain electrode, said photoresist figure 680 is removed, just form the nmos device of gained, its structure is shown in figure 11, comprises Semiconductor substrate 600; Gate dielectric layer 610 and gate electrode 620, said gate dielectric layer 610 forms successively with gate electrode 620 and said Semiconductor substrate 600 on; Source electrode 660 is formed in the Semiconductor substrate 600 of said gate electrode 620 1 sides; Side wall 670 is formed at the both sides of said gate electrode 620; Drain electrode 640b is formed in the Semiconductor substrate 600 of gate electrode 620 1 sides relative with said source electrode 660; LDD structure 640a, said LDD structure 640a only is formed in the said drain electrode 640a.Should scheme to know with the comparison of prior art gained nmos pass transistor; Ion concentration when the ion implantation concentration in the present embodiment below source region side wall 670 is the source electrode injection; Do not form the LDD structure; Its implantation dosage injects high two one magnitude than light dope, can significantly reduce the resistance of conducting channel.In addition; The source electrode 660 of below, present embodiment source region injects not horizontal proliferation to gate electrode 620 belows of ion; And in the prior art because there is the LDD structure in source electrode, and annealed technology diffuses to gate electrode below, its length of effective channel is less than the physical width of gate electrode; The length of effective channel of the MOS transistor that present embodiment forms is relatively large, more is prone to avoid short-channel effect.
More than first embodiment be the manufacturing process of nmos pass transistor, the transistorized manufacturing approach of brief description PMOS is as the second embodiment of the present invention.The transistorized manufacturing approach of PMOS and first embodiment are similar, only inject ionic type and source electrode, drain electrode in Semiconductor substrate type, light dope and inject aspect the ionic type difference to some extent.For the PMOS transistor, select the N type semiconductor substrate for use; Light dope is carried out when injecting in the drain region, injection be p type ion, for example boron; Source electrode injects, drain electrode is injected the ionic type of selecting for use and is p type, for example boron.
According to the design rule of integrated circuit, the size of device each item structure can be scaled.Main purpose of the present invention is the MOS transistor device that provides the integrated method of a kind of technology to have one-sided LDD structure with formation, therefore the concrete process of device is not too much related to.
The above is two specific embodiments of the present invention, forms nmos pass transistor and PMOS transistor respectively.The present invention only forms the LDD structure in drain electrode through the adjustment of the part on MOS standard technology basis, does not form the LDD structure at source electrode; Reduced the resistance of conducting channel thus; The conducting channel length that extended has alleviated short-channel effect, has improved device reaction speed and whole electrical property.
The present technique scheme is only done local adjustment to technological process, and production capacity and cost are not had considerable influence.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (4)
1. the manufacturing approach of a MOS transistor is characterized in that, comprising:
Semiconductor substrate is provided, is formed with gate dielectric layer and gate electrode on the said Semiconductor substrate successively, said gate electrode has first side and second side, and the Semiconductor substrate of said gate electrode first side is the source region, and the Semiconductor substrate of second side is the drain region;
After said source region forms the photoresist figure, light dope is carried out in said drain region and inject, after said drain region forms the photoresist figure, the source electrode injection carried out in said source region, form lightly doped drain and source electrode respectively;
The both sides of gate electrode form side wall on said gate dielectric layer;
After said source region forms the photoresist figure,, form and drain injections that drain of said drain region;
Wherein, said light dope ion implantation dosage is 10
12~ 10
13/ cm
2The order of magnitude, the dosage that said source electrode injects is 10
14~ 10
15/ cm
2The order of magnitude, the dosage that said drain electrode is injected is 10
14~ 10
15/ cm
2The order of magnitude.
2. the manufacturing approach of MOS transistor according to claim 1 is characterized in that, saidly light dope is carried out in the drain region injects and to comprise: on said Semiconductor substrate, form first photoresist layer; Graphical said first photoresist layer defines the drain region shape; With said first photoresist layer is that mask carries out the light dope injection, removes said first photoresist layer afterwards.
3. the manufacturing approach of MOS transistor according to claim 1 is characterized in that, the source electrode injection is carried out in said source region comprised: on said Semiconductor substrate, form second photoresist layer; Graphical said second photoresist layer defines the source region shape; With said second photoresist layer is that mask carries out the source electrode injection, removes said second photoresist layer afterwards.
4. the manufacturing approach of MOS transistor according to claim 1 is characterized in that, said drain region is drained to inject to be comprised: on said Semiconductor substrate, form the 3rd photoresist layer; Graphical said the 3rd photoresist layer defines the drain region shape; With said the 3rd photoresist layer is the mask injection that drains, and removes said the 3rd photoresist layer afterwards.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197613A CN102044438B (en) | 2009-10-23 | 2009-10-23 | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197613A CN102044438B (en) | 2009-10-23 | 2009-10-23 | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102044438A CN102044438A (en) | 2011-05-04 |
| CN102044438B true CN102044438B (en) | 2012-10-03 |
Family
ID=43910459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910197613A Expired - Fee Related CN102044438B (en) | 2009-10-23 | 2009-10-23 | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102044438B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105206216A (en) * | 2015-10-23 | 2015-12-30 | 武汉华星光电技术有限公司 | Display device and display device shift register circuit applied to gate drive circuit |
| CN110943129A (en) * | 2018-09-25 | 2020-03-31 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN113299554A (en) * | 2020-02-24 | 2021-08-24 | 微龛(广州)半导体有限公司 | Asymmetric MOSFET (Metal-oxide-semiconductor field Effect transistor), manufacturing method thereof and semiconductor device |
| CN111446298B (en) * | 2020-04-10 | 2023-10-20 | 上海华虹宏力半导体制造有限公司 | Medium-high voltage CMOS device and manufacturing method thereof |
| CN111785774B (en) * | 2020-06-15 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | CMOS device in BCD process and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483157B1 (en) * | 1997-06-20 | 2002-11-19 | Advanced Micro Devices, Inc. | Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area |
| CN100369266C (en) * | 2003-09-29 | 2008-02-13 | 友达光电股份有限公司 | Controlled film transistor, its preparation method and electroluminescent display apparatus containing same |
| CN101345257A (en) * | 2007-07-10 | 2009-01-14 | 联华电子股份有限公司 | Asymmetric metal-oxide-semiconductor transistor and production method and element using the same |
-
2009
- 2009-10-23 CN CN200910197613A patent/CN102044438B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6483157B1 (en) * | 1997-06-20 | 2002-11-19 | Advanced Micro Devices, Inc. | Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area |
| CN100369266C (en) * | 2003-09-29 | 2008-02-13 | 友达光电股份有限公司 | Controlled film transistor, its preparation method and electroluminescent display apparatus containing same |
| CN101345257A (en) * | 2007-07-10 | 2009-01-14 | 联华电子股份有限公司 | Asymmetric metal-oxide-semiconductor transistor and production method and element using the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102044438A (en) | 2011-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102044438B (en) | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof | |
| CN101599459B (en) | Fabricating method of semiconductor device | |
| CN102468178B (en) | Method for manufacturing transistor | |
| CN101281870A (en) | Method for manufacturing semiconductor device | |
| CN102938375A (en) | Field effect transistor and forming method thereof | |
| CN100590817C (en) | PMOS transistor and fabrication method thereof | |
| CN102737995B (en) | The manufacture method of semiconductor device | |
| CN102569077B (en) | Method for manufacturing source/drain region of semiconductor device | |
| CN101740389A (en) | MOS (Metal Oxide Semiconductor) transistor and forming method thereof | |
| CN101150071A (en) | Method of manufacturing semiconductor device | |
| CN102487007A (en) | Method for forming semiconductor device | |
| CN1905212B (en) | Transistor and method for forming the same | |
| CN102087981A (en) | Manufacture method for MOS (metal oxide semiconductor) transistor | |
| CN102479709B (en) | Transistor and manufacturing method for same | |
| CN105470134A (en) | Semiconductor device and manufacturing method thereof and electronic device | |
| CN102044435B (en) | MOS (Metal Oxide Semiconductor) transistor with common source structure and manufacturing method thereof | |
| CN102468162B (en) | Production method for n-channel metal oxide semiconductor (NMOS) field effect transistor | |
| CN101989550B (en) | Method for manufacturing n-metal-oxide-semiconductor (NMOS) transistor | |
| CN101789447A (en) | Metal oxide semiconductor (MOS) transistor and formation method thereof | |
| CN105336611A (en) | Manufacturing method of Fin FET device | |
| CN104425271A (en) | Mos transistor and forming method thereof | |
| CN102097307B (en) | Method for forming offset side wall and MOS transistor | |
| CN102082085A (en) | Forming method of ultra shallow junction structure and forming method of PMOS (P-Channel Metal Oxide Semiconductor) transistor | |
| CN101459081A (en) | MOS transistor forming method | |
| CN102569084B (en) | P-type high-concentration doped silicon and technology for preparing P-channel MOS (Metal Oxide Semiconductor) pipe of BCD products |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA Effective date: 20121101 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20121101 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121003 Termination date: 20191023 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |