CN102044435B - MOS (Metal Oxide Semiconductor) transistor with common source structure and manufacturing method thereof - Google Patents
MOS (Metal Oxide Semiconductor) transistor with common source structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102044435B CN102044435B CN200910197457A CN200910197457A CN102044435B CN 102044435 B CN102044435 B CN 102044435B CN 200910197457 A CN200910197457 A CN 200910197457A CN 200910197457 A CN200910197457 A CN 200910197457A CN 102044435 B CN102044435 B CN 102044435B
- Authority
- CN
- China
- Prior art keywords
- common source
- mos transistor
- source configuration
- drain electrode
- gate electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to an MOS (Metal Oxide Semiconductor) transistor with a common source structure and a manufacturing method thereof. The manufacturing method comprises the following steps of: sequentially forming a grid electrode medium layer and a grid electrode adjacent to the MOS transistor on a semiconductor substrate; carrying out LDD (Laser Detector Diode) injection to form a lightly doped drain electrode adjacent to the MOS transistor; forming a side wall at one side of the grid electrode near the lightly doped drain electrode; carrying out source/drain electrode injection to from the drain electrode adjacent to the MOS transistor and the common source structure. In the invention, because an LDD structure is only formed at one side of the drain electrode but is not formed in a common source region through the partial adjustment based on the MOS standard process, the resistance of a conducting channel is reduced, the conducting channel is lengthened, the short channel effect is reduced, and the reaction speed of a device and the overall electric performance are improved. In the invention, the standard process flow is only partially adjusted and is simple, thereby not exerting greater influence on the capacity and the cost.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of MOS transistor and manufacturing approach thereof with common source configuration.
Background technology
Along with improving constantly of integrated circuit integrated level, device size is progressively scaled, and characteristic size has reached the 32nm magnitude at present.Metal oxide semiconductor field effect tube (MOS transistor) is modal semiconductor device, is the elementary cell that constitutes various circuit.MOS transistor basic structure comprises three main region: source electrode (source), drain electrode (drain) and gate electrode (gate).Wherein source electrode and drain electrode are to be made up of highly doped zone, and be different according to type of device, can be divided into n type doping (NMOS) and p type doping (PMOS).
In the scaled process of device; Drain voltage does not reduce thereupon; This just causes the increase of the channel region electric field between source-drain electrode, and under the highfield effect, electronics can accelerate to the speed than much higher times of heat movement speed between twice collision; Owing to kinetic energy is called as hot electron very greatly, thereby cause thermoelectronic effect (hot electron effect).This effect belongs to the small-size effect of device, can cause that hot electron injects to gate dielectric layer, forms gate electrode electric current and substrate current, influences the reliability of device and circuit.
In order to overcome thermoelectronic effect, have multiplely to the improving one's methods of mos transistor structure, for example two injecting structure, buried channel structure, discrete grid structures, bury drain structure etc.; Wherein study morely and practical value is bigger a kind of be lightly doped drain (lightly doped drain:LDD) structure.The effect of lightly doped drain is to reduce electric field, can significantly improve thermoelectronic effect.
Although the LDD structure has significant improvement effect to thermoelectronic effect, also there are some shortcomings.Doping content such as the LDD structure is lower, causes the resistance between source/drain electrode to increase, and saturation current is reduced, and then cause the decline of device reaction speed.In addition, the LDD structure also makes the manufacturing process of MOS transistor more complicated.
In integrated circuit, the MOS transistor of two common sources is a kind of comparatively common device architectures, and generally, the LDD structure all exists in source/drain electrode.In the prior art, the manufacturing with MOS transistor of common source configuration mainly comprises following flow process (like Fig. 1～shown in Figure 5): with reference to Fig. 1, at first on Semiconductor substrate 100, form gate dielectric layer 110 and gate electrode 120 successively; With reference to Fig. 2, carry out the LDD ion and inject, form common source district 130 and drain region 140a, 140b, and the injection ion is spread in said Semiconductor substrate 100 through annealing process; With reference to Fig. 3, form side wall 150 in said gate electrode 120 both sides; With reference to Fig. 4, carry out source/drain electrode and inject, form device architecture as shown in Figure 5.In above technology; The LDD structure is formed at common source district 130 and drain region 140a, 140b simultaneously, and because the annealing effect, the ion in the LDD structure can spread; Make effective channel length much smaller than the physical width of gate electrode 120, cause short-channel effect easily.
Publication number is that 20080132014 U.S. Patent application has proposed a kind of method that reduces common source district resistance, and the doping through the zones of different variable concentrations realizes.This need increase multiple tracks photoetching and injection process, will do bigger adjustment to technical process and parameter, and the actual production meeting is caused certain influence.
For raising has the performance of the MOS transistor of common source configuration, need a kind of new manufacturing approach of exploitation, under the situation that does not increase process complexity, alleviate or eliminate the harmful effect that the LDD structure causes.
Summary of the invention
The problem that the present invention solved provides a kind of MOS transistor and manufacturing approach thereof with common source configuration, reduces the harmful effect that the LDD structure is brought, and improves the electric property of MOS transistor.
For addressing the above problem, the invention provides a kind of manufacturing approach with MOS transistor of common source configuration, comprising:
On Semiconductor substrate, form the gate electrode of gate dielectric layer and adjacent mos transistors successively;
Carry out LDD and inject, form the lightly doped drain of adjacent mos transistors;
At the side formation side wall of said gate electrode near lightly doped drain;
Carry out source/drain electrode and inject, form the drain electrode and the common source configuration of adjacent mos transistors.
Optional, said gate electrode at formation gate dielectric layer and adjacent mos transistors on the Semiconductor substrate comprises: on Semiconductor substrate, form gate dielectric layer and the pseudo-gate electrode that covers the common source district; Comprise at the side formation side wall of said gate electrode near lightly doped drain: the both sides at said pseudo-gate electrode form side wall.
Optional, said manufacturing approach with MOS transistor of common source configuration also comprises: after forming side wall, before carrying out source/drain electrode and injecting, remove the part in said pseudo-gate electrode and gate dielectric layer covering common source district.
Optional, said gate electrode at formation gate dielectric layer and adjacent mos transistors on the Semiconductor substrate comprises: on Semiconductor substrate, form and expose the gate dielectric layer in common source district and the gate electrode of adjacent mos transistors.
Optional, said manufacturing approach with MOS transistor of common source configuration also comprises: before carrying out the LDD injection, on said gate electrode, form photoresist layer and patterning, the photoresist layer of said patterning covers said common source district; After forming side wall, carry out source/drain electrode injection before, remove said photoresist layer.
Optional, the material of said gate dielectric layer is a silicon dioxide.
Optional, said LDD ion implantation dosage is 10
12～10
13/ cm
2
Optional, said source/drain ion implantation dosage is 10
14～10
15/ cm
2
Optional, said type with MOS transistor of common source configuration is a nmos pass transistor.
Optional, the type of said Semiconductor substrate is the P type.
Optional, it is arsenic or antimony that said LDD injects ionic type.
Optional, it is arsenic or antimony that ionic type is injected in said source/drain electrode.
Optional, said type with MOS transistor of common source configuration is the PMOS transistor.
Optional, the type of said Semiconductor substrate is the N type.
Optional, it is boron that said LDD injects ionic type.
Optional, it is boron that ionic type is injected in said source/drain electrode.
The present invention also provides a kind of MOS transistor with common source configuration, comprising:
Semiconductor substrate;
The gate electrode of gate dielectric layer and adjacent mos transistors is formed on the said Semiconductor substrate successively;
The drain electrode of adjacent mos transistors and common source configuration are formed at respectively in the Semiconductor substrate of said gate electrode both sides, and wherein, said common source configuration is formed in the Semiconductor substrate between the gate electrode of said adjacent mos transistors;
Lightly doped drain and side wall, said lightly doped drain are formed in the Semiconductor substrate of said drain electrode one side, and said side wall is formed at the side of said gate electrode near drain electrode.
Optional, said type with MOS transistor of common source configuration is a nmos pass transistor.
Optional, the dopant ion type of said drain electrode and common source configuration is arsenic or antimony.
Optional, said type with MOS transistor of common source configuration is the PMOS transistor.
Optional, the dopant ion type of said drain electrode and common source configuration is a boron.
Compared with prior art; Such scheme has the following advantages: through the adjustment of the part on MOS standard technology basis, only form the LDD structure in drain electrode one side, do not form the LDD structure in the common source district; Reduced the resistance of conducting channel thus; The conducting channel length that extended has alleviated short-channel effect, and then has improved device reaction speed and whole electrical property.
In addition, technique scheme is only done local adjustment to technological process, and its flow process is simple, can not produce considerable influence to production capacity and cost.
Description of drawings
Fig. 1 to Fig. 5 is the cross-sectional view of the manufacturing approach of the MOS transistor of existing technology with common source configuration;
Fig. 6 is the schematic flow sheet of manufacturing approach of the MOS transistor with common source configuration of embodiment of the present invention;
Fig. 7 to Figure 12 is the cross-sectional view of manufacturing approach of the MOS transistor with common source configuration of first embodiment of the invention;
Figure 13 is the cross-sectional view of manufacturing approach of the MOS transistor with common source configuration of second embodiment of the invention;
Figure 14 to Figure 17 is the cross-sectional view of manufacturing approach of the MOS transistor with common source configuration of third embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed specific embodiment.
Method provided by the invention is not only applicable to make the common source configuration of two MOS transistors, is applicable to the common source configuration of a plurality of MOS transistors, the particularly characteristic size MOS transistor circuit below 130nm yet.Said MOS transistor can be PMOS transistor or the nmos pass transistor in the CMOS technology.
Of preamble; Existing manufacturing approach with MOS transistor of common source configuration all forms the LDD structure in common source district and two drain regions, because LDD structure doping content is low, resistance is higher relatively; Make that conducting channel resistance is higher; Cause RC to postpone to increase, reduced the reaction speed of MOS transistor, influenced device performance.Because all there are the LDD structure in common source district and drain region, its horizontal proliferation causes length of effective channel to shorten, and causes short-channel effect easily in addition, causes problems such as puncture voltage reduces, the increase of channel leakage stream.
The inventor finds, because common source institute making alive is not too high generally speaking, ground connection under the situation is therefore limited in the electric field strength in common source district mostly, there is no need to form the LDD structure in this zone.Only form the LDD structure, can reduce channel resistance to a certain extent, and can increase channel length, avoid short-channel effect in the drain region.Because in the present manufacturing approach, the LDD ion in source/drain region injects and carries out simultaneously,,, need do certain adjustment to technological process for fear of form the LDD structure in the common source district so the LDD structure all exists in common source district and drain region.
For this reason, the present invention is based on existing MOS transistor technological process, and it is done local adjustment, only form the LDD structure, make under the not obvious situation that influences process complexity, improve the device performance of formed MOS transistor in the drain region.
About the flow process adjustment to the MOS transistor standard technology, Fig. 6 has indicated the schematic flow sheet of an embodiment.As shown in Figure 6, execution in step S610 forms the gate electrode of gate dielectric layer and adjacent mos transistors successively on Semiconductor substrate; Execution in step S620 carries out LDD and injects, and forms the lightly doped drain of adjacent mos transistors; Execution in step S630 is at the side formation side wall of said gate electrode near lightly doped drain; Execution in step S640 carries out source/drain electrode and injects, and forms the drain electrode and the common source configuration of adjacent mos transistors.
Method provided by the invention is applicable to the manufacturing of the MOS transistor that has common source configuration in the integrated circuit; But should method of the present invention be limited to this; If in other technologies, relate to the situation that forms MOS transistor or only form the LDD structure in the drain region, method of the present invention also can well be suitable for.
Fig. 7 to Figure 12 is elaborated below in conjunction with Fig. 6 for the cross-sectional view of the manufacturing approach of the nmos pass transistor with common source configuration of first embodiment of the invention.
Like Fig. 6 and shown in Figure 7, execution in step S610 forms the gate electrode of gate dielectric layer and adjacent mos transistors successively on Semiconductor substrate.Specifically comprise: P type semiconductor substrate 700 at first is provided, certain isolation structure (not shown) is arranged on the said Semiconductor substrate 700, like silica etc.Said Semiconductor substrate can be the silicon or the SiGe of monocrystalline, polycrystalline or non crystalline structure, also can be silicon-on-insulator (SOI).The material that perhaps can also comprise other, for example III-V compounds of group such as GaAs.
Form gate dielectric layer 710 on said Semiconductor substrate 700 surfaces; Thickness tens of to the hundreds of dust; Its formation method can be conventional vacuum coating technology; For example boiler tube thermal oxidation, ald (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) technology, present embodiment adopts the boiler tube thermal oxidation technology.
On said gate dielectric layer 710, form the gate electrode layer (not shown) then; The material of said gate electrode layer can be polysilicon or metal; Select n type DOPOS doped polycrystalline silicon in the present embodiment for use; Its formation method is low-pressure chemical vapor phase deposition (LPCVD), and dopant ion is a phosphorus, and the thickness of said polysilicon is between hundreds of extremely several thousand dusts.Then said gate electrode layer is carried out graphically; And form the pseudo-gate electrode 720 of two adjacent common source nmos pass transistors through etching; Pseudo-gate electrode 720 is for merging gate electrode described in the present embodiment; Comprise the independent gate electrode (like area I among Fig. 7 and II) of two adjacent common source nmos pass transistors and cover two adjacent common source nmos pass transistors between the part (like area I II among Fig. 7) in common source district, the Semiconductor substrate of pseudo-gate electrode 720 both sides constitutes the drain region of two adjacent common source nmos pass transistors.So far, the device architecture of formation is as shown in Figure 7.
Next like Fig. 6 and shown in Figure 8, execution in step S620 carries out LDD and injects, and forms the lightly doped drain of adjacent mos transistors.Specifically comprise: at first on said pseudo-gate electrode 720, form mask (not indicating among the figure); Carry out LDD afterwards and inject, in the drain region of the both sides of said pseudo-gate electrode 720, form lightly doped drain 730a, 730b.For the NMOS of present embodiment, injection be n type ion, for example phosphorus (P) or arsenic (As).Ion implantation dosage is 10
12～10
13/ cm
2, its inject degree of depth tens of between the hundreds of dust and the prior art basically identical.After said LDD injects; Remove mask; Said Semiconductor substrate 700 is heat-treated, the injection ion among said lightly doped drain 730a, the 730b is taken place vertically and horizontal diffusion, its part is diffused in the Semiconductor substrate 700 of said pseudo-gate electrode 720 belows.This step is that with the difference of existing technology LDD injects the lightly doped drain that only is directed against two adjacent common source nmos pass transistors and carries out, and injects and carry out LDD for the source region of adjacent common source nmos pass transistor.
Like Fig. 6 and shown in Figure 9; Execution in step S630; At the side formation side wall of said gate electrode near lightly doped drain, be in the both sides of said pseudo-gate electrode 720 in the present embodiment, promptly one side forms side wall (spacer) in the drain region of two adjacent common source nmos pass transistors.At first on said Semiconductor substrate 700, form the dielectric layer (not shown), be generally oxide layer, generation type can be low-pressure chemical vapor phase deposition (LPCVD), and thickness is higher than gate height.Said dielectric layer also can be selected oxide layer-silicon nitride-oxide layer sandwich construction forms such as (ONO) for use.Afterwards said dielectric layer is returned (etch back) technology at quarter, form side wall 740 in the both sides of said pseudo-gate electrode 720.Said side wall 740 can play a protective role to said pseudo-gate electrode 720.After forming said side wall 740, will be positioned at lightly doped drain 730a, last gate dielectric layer 710 removals of 730b.Through this step, only on the drain region of two adjacent common source nmos pass transistors, form side wall, and prior art all can form side wall in the source region and the drain region of MOS transistor.
With reference to figure 6 and Figure 10,11, execution in step S640 carries out source/drain electrode and injects, and forms the drain electrode and the common source configuration of adjacent mos transistors.Concrete technology comprises: before carrying out source/drain electrode injection; Need earlier pseudo-gate electrode 720 and the part (being the area I II among Figure 10) that gate dielectric layer 710 covers the common source district to be removed; Expose the common source district; Be specially: at first on said Semiconductor substrate 700, apply photoresist (not shown) and graphical, carry out dry etching then, pseudo-gate electrode 720 etchings of the part that covers common source district 750 are removed it; Utilize wet etching that the gate dielectric layer 710 of 750 tops, common source district is removed again, expose common source district 750.Said dry etching generally adopts chlorine-containing gas, and wet etching adopts hydrofluoric acid.Remove residual photoresist then.So far, device architecture is shown in figure 10, and the independent gate electrode 720a of two adjacent common source nmos pass transistors, 720b form, is common source district 750 between them.Be not form side wall near common source district 750 1 sides with the existing structure difference at said independent gate electrode 720a, 720b.
With reference to Figure 11, carry out source/drain electrode and inject.To nmos device, injecting ionic type is the n type, and like arsenic (As) or antimony (Sb), the ion dose that source/drain electrode is injected is 10
14～10
15/ cm
2, inject high two one magnitude than said LDD, with the prior art basically identical.Because said lightly doped drain 730a, 730b have been formed with side wall 740; The Semiconductor substrate 700 that makes side wall 740 belows in the source/process that drain electrode is injected do not inject ion; The low concentration doping ion that forms when therefore below said side wall 740, only having LDD to inject; Inject through source/drain electrode, form LDD structure 760a, 760b.And for said common source district 750, owing to do not form side wall, in the source/the process intermediate ion injection zone of drain electrode injection limits on independent gate electrode 720a, 720b border.After said source/drain electrode is injected, form drain electrode 770a, 770b and the zone of the common source between independent gate electrode 720a and independent gate electrode 720b formation common source configuration 750a in the drain region of independent gate electrode 720a one side and the drain region of independent gate electrode 720b one side.The difference of above correlation step and existing technological process is: the scope that common source district ion injects is bigger than existing technology.
After completion is injected in source/drain electrode, through steps necessarys such as cleanings, form nmos device, structure is shown in figure 12, comprises Semiconductor substrate 700; Gate electrode 720a, the 720b of gate dielectric layer 710 and adjacent mos transistors are formed on the said Semiconductor substrate 700 successively; The drain electrode 770a of adjacent mos transistors, 770b and common source configuration 750a; Be formed at respectively in the Semiconductor substrate 700 of gate electrode 720a, 720b both sides of said adjacent mos transistors; Wherein, said common source configuration 750a is formed in the Semiconductor substrate 700 between said gate electrode 720a, the 720b; LDD structure 760a, 760b and side wall 740, said LDD structure 760a, 760b are formed at respectively in said drain electrode 770a, the 770b, and said side wall 740 is formed at said gate electrode 720a, the 720b side near drain electrode 770a, 770b respectively.
The nmos pass transistor comparison of Figure 12 and prior art formation can be known in common source configuration 750a, there is not low-doped LDD structure in the present embodiment, significantly reduced the resistance of conducting channel.In addition, horizontal proliferation is not to the Semiconductor substrate 700 of gate electrode 720a, 720b below for the injection ion of present embodiment common source configuration 750a below, and compared with prior art, length of effective channel is less relatively, avoids or weakened short-channel effect.
More than first embodiment be manufacturing process with nmos pass transistor of common source configuration, brief description has the transistorized related procedure of PMOS of common source configuration, as the second embodiment of the present invention.The said transistorized structure of PMOS with common source configuration is shown in figure 13, and its typical process flow is consistent with first embodiment, only injects aspect ionic type and the source/drain electrode injection ionic type difference to some extent at substrate type, LDD.For PMOS transistor, select N type semiconductor substrate 800 for use with common source configuration; Drain electrode 830a, 830b are carried out LDD when injecting, injection be p type ion, boron (B) for example; Source/drain electrode is injected the ionic type of selecting for use and also is p type, for example boron (B).Other parts comprise gate dielectric layer 810, gate electrode 820a, 820b, and side wall 840, LDD structure 860a, 860b, the formation method of common source configuration 850 is consistent with first embodiment.
Figure 14 to Figure 17 is elaborated below in conjunction with Fig. 6 for the cross-sectional view of the manufacturing approach of the MOS transistor with common source configuration of third embodiment of the invention.
Like Fig. 6 and shown in Figure 14, execution in step S610 forms the gate electrode of gate dielectric layer and adjacent mos transistors successively on Semiconductor substrate.Specifically comprise: Semiconductor substrate 900 at first is provided, certain isolation structure (not shown) is arranged on the said Semiconductor substrate 900, for example silica etc.The material of said Semiconductor substrate 900 is consistent with first or second embodiment.
Form gate dielectric layer 910 on said Semiconductor substrate 900 surfaces, to the hundreds of dust, its formation method is consistent with first embodiment tens of for thickness.Then, on said gate dielectric layer 910, forming the gate electrode of adjacent mos transistors, is independent gate electrode 920a, the 920b of adjacent mos transistors in the present embodiment, is the common source district between said independent gate electrode 920a, the 920b.The material of said independent gate electrode 920a, 920b is consistent with first embodiment with the formation method.Different with first embodiment is that gate dielectric layer that present embodiment forms on Semiconductor substrate and gate electrode expose the common source district.
Like Fig. 6 and shown in Figure 15, execution in step S620 carries out LDD and injects, and forms the lightly doped drain of adjacent mos transistors.Specifically comprise: at first at said independent gate electrode 920a, 920b last coating photoresist and graphical to it, form photoresist figure 950, said photoresist figure 950 covers independent gate electrode 920a, 920b and the common source district between them.Afterwards, utilize said photoresist figure 950 to be mask, to shown in Semiconductor substrate 900 carry out LDD and inject, form lightly doped drain 930a and 930b.For nmos device, injection be n type ion; For the PMOS device, injection be n type ion.Ion implantation dosage is 10
12～10
13/ cm
2, its inject degree of depth tens of between the hundreds of dust, with the prior art basically identical.Afterwards, said Semiconductor substrate 900 is heat-treated, the injection ion among lightly doped drain 930a and the 930b is taken place vertically and horizontal diffusion, its part is diffused in the substrate of said independent gate electrode 920a, 920b below.
Like Fig. 6 and shown in Figure 16, execution in step S630 is at the side formation side wall of said gate electrode near lightly doped drain.Specifically comprise: on said Semiconductor substrate 900, form the dielectric layer (not shown), be generally oxide layer, generation type can be low-pressure chemical vapor phase deposition (LPCVD), and thickness is higher than the height of independent gate electrode 920a, 920b.Said dielectric layer also can be selected oxide layer-silicon nitride-oxide layer sandwich construction forms such as (ONO) for use.Said dielectric layer is returned (etch back) technology at quarter; The side near lightly doped drain 930a, 930b at said independent gate electrode 920a, 920b forms side wall 940; Because the existence of said photoresist figure 950, said independent gate electrode 920a, 920b do not form side wall near a side in common source district.
Like Fig. 6 and shown in Figure 17, execution in step S640 carries out source/drain electrode and injects, and forms the drain electrode and the common source configuration of adjacent mos transistors.Specifically comprise: at first remove said photoresist figure 950, afterwards said Semiconductor substrate 900 is carried out source/drain electrode and inject, form drain electrode 980a, 980b and common source configuration 970.For nmos device, injecting ionic type is the n type; For the PMOS device, injecting ionic type is the p type, and it is 10 that source electrode injects ion dose
14～10
15/ cm
2, inject high two one magnitude than LDD, with the prior art basically identical.Owing to be formed with side wall 940 near lightly doped drain 930a, 930b one side; Make in the Semiconductor substrate 900 of side wall 940 belows and do not inject ion; The low concentration doping ion that forms when therefore below said side wall 940, only having LDD to inject; Form LDD structure 960a, the 960b of drain electrode one side, form common source configuration 970 between said independent gate electrode 920a, the 920b.
After completion was injected in source/drain electrode, through steps necessarys such as cleanings, completion had the transistorized manufacture process of PMOS of common source configuration.
According to the design rule of integrated circuit, the size of device each item structure can be scaled.Main purpose of the present invention is to provide the integrated method of a kind of technology to have the metal-oxide-semiconductor field effect transistor of common source with formation, so the concrete process of device is not too much related to.
The present invention is through the adjustment of the part on MOS standard technology basis; Only form the LDD structure in drain electrode one side; Do not form the LDD structure in the common source district, the conducting channel length that extended has thus reduced the resistance of conducting channel; Alleviate short-channel effect, improved device reaction speed and whole electrical property.
The present technique scheme is only done local adjustment to technological process, can not produce considerable influence to production capacity and cost.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (19)
1. the manufacturing approach with MOS transistor of common source configuration is characterized in that, comprising:
On Semiconductor substrate, form the gate electrode of gate dielectric layer and adjacent mos transistors successively;
Carry out LDD and inject, form the lightly doped drain of adjacent mos transistors, do not inject and carry out LDD in the common source zone of adjacent mos transistors;
At the side formation side wall of said gate electrode near lightly doped drain;
Carry out source/drain electrode and inject, form the drain electrode and the common source configuration of adjacent mos transistors, said LDD structure only is formed in the said drain electrode structure, and said source/drain electrode implantation dosage is than high two one magnitude of said LDD implantation dosage.
2. the manufacturing approach with MOS transistor of common source configuration according to claim 1; It is characterized in that said gate electrode at formation gate dielectric layer and adjacent mos transistors on the Semiconductor substrate comprises: on Semiconductor substrate, form gate dielectric layer and the pseudo-gate electrode that covers the common source district; Comprise at the side formation side wall of said gate electrode near lightly doped drain: the both sides at said pseudo-gate electrode form side wall.
3. the manufacturing approach with MOS transistor of common source configuration according to claim 2 is characterized in that, also comprises: after forming side wall, before carrying out source/drain electrode and injecting, remove the part in said pseudo-gate electrode and gate dielectric layer covering common source district.
4. the manufacturing approach with MOS transistor of common source configuration according to claim 1; It is characterized in that said gate electrode at formation gate dielectric layer and adjacent mos transistors on the Semiconductor substrate comprises: on Semiconductor substrate, form and expose the gate dielectric layer in common source district and the gate electrode of adjacent mos transistors.
5. the manufacturing approach with MOS transistor of common source configuration according to claim 4; It is characterized in that; Also comprise: before carrying out the LDD injection, on said gate electrode, form photoresist layer and patterning, the photoresist layer of said patterning covers said common source district; After forming side wall, carry out source/drain electrode injection before, remove said photoresist layer.
6. the manufacturing approach with MOS transistor of common source configuration according to claim 1 is characterized in that, the material of said gate dielectric layer is a silicon dioxide.
7. the manufacturing approach with MOS transistor of common source configuration according to claim 1 is characterized in that, the dosage that said LDD injects is 10
12～10
13/ cm
2
8. the manufacturing approach with MOS transistor of common source configuration according to claim 1 is characterized in that, the dosage that said source/drain electrode is injected is 10
14～10
15/ cm
2
9. the manufacturing approach with MOS transistor of common source configuration according to claim 1 is characterized in that, said type with MOS transistor of common source configuration is a nmos pass transistor.
10. the manufacturing approach with MOS transistor of common source configuration according to claim 9 is characterized in that, the ionic type that said LDD injects is arsenic or antimony.
11. the manufacturing approach with MOS transistor of common source configuration according to claim 9 is characterized in that, the ionic type that said source/drain electrode is injected is arsenic or antimony.
12. the manufacturing approach with MOS transistor of common source configuration according to claim 1 is characterized in that, said type with MOS transistor of common source configuration is the PMOS transistor.
13. the manufacturing approach with MOS transistor of common source configuration according to claim 12 is characterized in that, the ionic type that said LDD injects is a boron.
14. the manufacturing approach with MOS transistor of common source configuration according to claim 12 is characterized in that, the ionic type that said source/drain electrode is injected is a boron.
15. the MOS transistor with common source configuration comprises:
Semiconductor substrate;
The gate electrode of gate dielectric layer and adjacent mos transistors is formed on the said Semiconductor substrate successively;
The drain electrode of adjacent mos transistors and common source configuration are formed at respectively in the Semiconductor substrate of said gate electrode both sides, and wherein, said common source configuration is formed in the Semiconductor substrate between the gate electrode of said adjacent mos transistors;
Lightly doped drain and side wall, said formation drain electrode and common source configuration are than high two one magnitude of implantation dosage of said formation lightly doped drain;
It is characterized in that said lightly doped drain only is formed in the Semiconductor substrate of said drain electrode one side, said side wall is formed at the side of said gate electrode near drain electrode.
16. the MOS transistor with common source configuration according to claim 15 is characterized in that, said type with MOS transistor of common source configuration is a nmos pass transistor.
17. the MOS transistor with common source configuration according to claim 16 is characterized in that, the dopant ion type of said drain electrode and common source configuration is arsenic or antimony.
18. the MOS transistor with common source configuration according to claim 15 is characterized in that, said type with MOS transistor of common source configuration is the PMOS transistor.
19. the MOS transistor with common source configuration according to claim 18 is characterized in that, the dopant ion type of said drain electrode and common source configuration is a boron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197457A CN102044435B (en) | 2009-10-20 | 2009-10-20 | MOS (Metal Oxide Semiconductor) transistor with common source structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200910197457A CN102044435B (en) | 2009-10-20 | 2009-10-20 | MOS (Metal Oxide Semiconductor) transistor with common source structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102044435A CN102044435A (en) | 2011-05-04 |
| CN102044435B true CN102044435B (en) | 2012-10-03 |
Family
ID=43910456
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200910197457A Active CN102044435B (en) | 2009-10-20 | 2009-10-20 | MOS (Metal Oxide Semiconductor) transistor with common source structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102044435B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794483B (en) * | 2012-10-30 | 2016-12-21 | 中芯国际集成电路制造(上海)有限公司 | There is the manufacture method of the semiconductor device of metal gates |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060346A (en) * | 1996-12-27 | 2000-05-09 | Lg Semicon Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6180443B1 (en) * | 1998-05-04 | 2001-01-30 | Lg Semicon Co., Ltd. | Semiconductor device and method of fabricating the same |
-
2009
- 2009-10-20 CN CN200910197457A patent/CN102044435B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6060346A (en) * | 1996-12-27 | 2000-05-09 | Lg Semicon Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6180443B1 (en) * | 1998-05-04 | 2001-01-30 | Lg Semicon Co., Ltd. | Semiconductor device and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102044435A (en) | 2011-05-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103378134B (en) | Grid structure and formation method, semiconductor structure and formation method | |
| CN102044438B (en) | MOS (Metal Oxide Semiconductor) transistor and manufacturing method thereof | |
| CN102800595B (en) | NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method and corresponding COMOS structure forming method | |
| CN101599459B (en) | Fabricating method of semiconductor device | |
| CN101281870A (en) | Method for manufacturing semiconductor device | |
| CN102737995B (en) | The manufacture method of semiconductor device | |
| CN102044435B (en) | MOS (Metal Oxide Semiconductor) transistor with common source structure and manufacturing method thereof | |
| CN112071909A (en) | Three-dimensional metal-oxide field effect transistor and preparation method thereof | |
| CN106033727A (en) | Manufacturing method of field effect transistor | |
| CN104992943A (en) | Manufacturing technique method of SONOS memory | |
| CN102487007A (en) | Method for forming semiconductor device | |
| CN115732556A (en) | NMOS (N-channel metal oxide semiconductor) device, preparation method thereof and integrated circuit | |
| CN102087981A (en) | Manufacture method for MOS (metal oxide semiconductor) transistor | |
| CN102208449B (en) | A kind of SOI body contact MOS transistor and forming method thereof | |
| CN111916448B (en) | Semiconductor device, manufacturing method thereof and electronic equipment | |
| CN105470134A (en) | Semiconductor device and manufacturing method thereof and electronic device | |
| CN102709162A (en) | Method of forming silicon germanium channel and PMOS (P-channel metal oxide semiconductor) transistor | |
| CN101989550B (en) | Method for manufacturing n-metal-oxide-semiconductor (NMOS) transistor | |
| CN102376560A (en) | Manufacturing method of semi-conductor device | |
| CN109524457B (en) | Semiconductor device with a plurality of semiconductor chips | |
| CN102479709A (en) | Transistor and manufacturing method thereof | |
| CN102376574B (en) | Manufacturing method of semiconductor device | |
| CN105336611A (en) | Manufacturing method of Fin FET device | |
| CN102479814B (en) | Transistor and manufacturing method thereof | |
| CN104425271A (en) | Mos transistor and forming method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING (BEIJING) INTERNATIONA Effective date: 20121105 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20121105 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Patentee after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |