CN102376560A - Manufacturing method of semi-conductor device - Google Patents
Manufacturing method of semi-conductor device Download PDFInfo
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- CN102376560A CN102376560A CN2010102537855A CN201010253785A CN102376560A CN 102376560 A CN102376560 A CN 102376560A CN 2010102537855 A CN2010102537855 A CN 2010102537855A CN 201010253785 A CN201010253785 A CN 201010253785A CN 102376560 A CN102376560 A CN 102376560A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 122
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 222
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 111
- 235000012239 silicon dioxide Nutrition 0.000 claims abstract description 95
- 238000000034 method Methods 0.000 claims abstract description 71
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 53
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 52
- 238000001039 wet etching Methods 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims description 95
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 46
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 33
- 238000005516 engineering process Methods 0.000 claims description 27
- 238000002347 injection Methods 0.000 claims description 16
- 239000007924 injection Substances 0.000 claims description 16
- 238000010884 ion-beam technique Methods 0.000 claims description 6
- -1 nitrogen ions Chemical class 0.000 abstract description 42
- 230000015572 biosynthetic process Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 127
- 150000002500 ions Chemical class 0.000 description 15
- 238000000151 deposition Methods 0.000 description 6
- 230000008021 deposition Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000001259 photo etching Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention discloses a manufacturing method of a semi-conductor device, which comprises the steps that: before silicon dioxide which is not covered by a second side wall layer is etched through a wet etching process, nitrogen ions are injected into the silicon dioxide which is not covered by the second side wall layer to improve the wet etching rate of an injected area. The method can prevent the formation of gaps, so that the power consumption of the semi-conductor device is reduced.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of manufacture method of semiconductor device.
Background technology
Fabricate is meant chemistry or the physical operations of on Semiconductor substrate, carrying out a series of complicacies, to form the process of semiconductor device.Fig. 1～Fig. 6 is the process generalized section of the manufacture method of semiconductor device in the prior art, and this method mainly comprises:
Step 101 referring to Fig. 1, provides semi-conductive substrate 1001, at Semiconductor substrate 1001 superficial growth gate oxides 1002, and deposit polysilicon 1003, utilize technologies such as photoetching, etching and ion injection to form grid structure.
In this step, at first carry out the growth of gate oxide 1002; Then, through chemical vapor deposition method, at wafer surface deposit one deck polysilicon 1003, thickness is about 500～2000 dusts; Afterwards, through technologies such as photoetching, etching and ion injections, produce grid structure, grid structure according to the invention comprises grid that is made up of polysilicon 1003 and the gate oxide 1002 that is positioned at the grid below.
Step 102 referring to Fig. 2, is carried out lightly doped drain (LDD) to Semiconductor substrate 1001 and is injected, and on the Semiconductor substrate 1001 of grid structure both sides, forms lightly doped drain 1004 and light dope source electrode 1005.
Under the promotion of demands such as semiconductor device miniatureization, densification, high speed and system integration, the width of grid structure constantly reduces, and the channel length of its below also constantly reduces; Yet the voltage of drain terminal does not significantly reduce; This has just caused the increase at the electric field of drain terminal, and near the electric charge making has bigger energy, and these hot carriers might be passed through gate oxide; Caused the increase of leakage current; Therefore, need to adopt some means to reduce the possibility that leakage current occurs, inject like LDD.
Step 103 is referring to Fig. 3, at Semiconductor substrate 1001 surface deposition silicon dioxide (SiO
2) 1006.
In subsequent step, silica 1 006 will be etched and form the first side wall layer.
Step 104 is referring to Fig. 4, at silica 1 006 surface deposition silicon nitride (Si
3N
4) 1007.
In subsequent step, silicon nitride 007 will be etched and form second side wall layer.
Step 105 referring to Fig. 5, adopts the silicon nitride 1007 on dry etch process etched wafer surface, forms second side wall layer 1008, adopts the silica 1 006 on wet-etching technology etched wafer surface then, forms the first side wall layer 1009.
First and second side wall layer can be used for preventing that follow-up carrying out from too leaking break-through near raceway groove so that generation source when the source leak to be injected, and produce leakage current thereby diffusion takes place the impurity that promptly injects.
When adopting the silica 1 006 on wet-etching technology etched wafer surface, the silicon dioxide of the second side wall layer both sides is only removed in expectation, keeps the silicon dioxide of second side wall layer below.
Step 106 referring to Fig. 6, is carried out ion to Semiconductor substrate 1001 and is injected, thereby forms drain electrode 1010 and source electrode 1011.
Need to prove; Because the first side wall layer 1009 and second side wall layer 1008 can be used as the protective layer of grid structure; Therefore the ion that injects is difficult to get into grid, thereby only the Semiconductor substrate 1001 of grid both sides has been realized injection, and final drain electrode 1010 and the source electrode 1011 of forming.
So far, this flow process finishes.
Yet; In above-mentioned steps 105; When adopting the wet-etching technology etching silicon dioxide; Because the isotropism (wet isotropic etch property) of wet etching; When the silicon dioxide of the semiconductor substrate surface of the etching second side wall layer both sides, the silicon dioxide of second side wall layer below also can be etched, thereby below second side wall layer, forms the breach shown in Fig. 5 and Fig. 6 dashed circle; Shown in breach can increase any leakage current, any two leakage currents or whole three kinds of leakage currents in the leakage current, these three kinds of leakage currents of the leakage current between the drain and gate between leakage current, source electrode and the grid between drain electrode and the source electrode, improved the power consumption of semiconductor device.
Summary of the invention
In view of this, the present invention provides a kind of manufacture method of semiconductor device, can reduce the power consumption of semiconductor device.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that
A kind of manufacture method of semiconductor device, this method comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Deposit is used to form the silicon dioxide and the silicon nitride that is used to form second side wall layer of the first side wall layer successively; And said silicon dioxide and the said silicon nitride that is used to form second side wall layer that is used to form the first side wall layer covers semiconductor substrate surface, grid structure upper surface and grid structure two sides; Adopt the dry etch process etching to cover the silicon nitride of grid structure upper surface and semiconductor substrate surface, the silicon nitride that covers the grid structure two sides forms second side wall layer;
The silicon dioxide and the second side wall layer injecting nitrogen ion that are not covered to semiconductor substrate surface by second side wall layer;
The silicon dioxide that adopts the wet-etching technology etching not covered by second side wall layer forms the first side wall layer;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of the first side wall layer and the second side wall layer both sides, form drain electrode and source electrode.
The dosage that said nitrogen ion injects is 3 * 10
14Individual atom/cm
2To 4 * 10
15Individual atom/cm
2
The energy that said nitrogen ion injects is 2000 electron-volts to 30000 electron-volts.
The angle of ion beam and vertical direction was that-0.5 degree is to 0.5 degree when said nitrogen ion injected.
Before Semiconductor substrate was carried out the ion injection, this method further comprised:
Deposit is used to form the silicon dioxide of the 3rd side wall layer; And the said silicon dioxide that is used to form the 3rd side wall layer covers the surface of second side wall layer of semiconductor substrate surface, grid structure upper surface and grid structure two sides; Adopt the wet-etching technology etching to cover the silicon dioxide of semiconductor substrate surface, the silicon dioxide that covers second side wall layer surface of grid structure upper surface and grid structure two sides forms the 3rd side wall layer;
Said drain electrode and source electrode are formed on the Semiconductor substrate of the first side wall layer, second side wall layer and the 3rd side wall layer both sides.
A kind of manufacture method of semiconductor device, this method comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Deposit is used to form the silicon dioxide and the silicon nitride that is used to form second side wall layer of the first side wall layer successively; And said silicon dioxide and the said silicon nitride that is used to form second side wall layer that is used to form the first side wall layer covers semiconductor substrate surface, grid structure upper surface and grid structure two sides; To silicon dioxide and silicon nitride injecting nitrogen ion, wherein the silicon dioxide that silicon nitride covered of grid structure two sides is not injected into the nitrogen ion;
Adopt the dry etch process etching to cover the silicon nitride of grid structure upper surface and semiconductor substrate surface, the silicon nitride that covers the grid structure two sides forms second side wall layer;
The silicon dioxide that adopts the wet-etching technology etching not covered by second side wall layer forms the first side wall layer;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of the first side wall layer and the second side wall layer both sides, form drain electrode and source electrode.
The dosage that said nitrogen ion injects is 5 * 10
14Individual atom/cm
2To 8 * 10
15Individual atom/cm
2
The energy that said nitrogen ion injects is 20000 electron-volts to 50000 electron-volts.
The angle of ion beam and vertical direction was that-0.5 degree is to 0.5 degree when said nitrogen ion injected.
Before Semiconductor substrate was carried out the ion injection, this method further comprised:
Deposit is used to form the silicon dioxide of the 3rd side wall layer; And the said silicon dioxide that is used to form the 3rd side wall layer covers the surface of second side wall layer of semiconductor substrate surface, grid structure upper surface and grid structure both sides; Adopt the wet-etching technology etching to cover the silicon dioxide of semiconductor substrate surface, the silicon dioxide that covers second side wall layer surface of grid structure upper surface and grid structure both sides forms the 3rd side wall layer;
Said drain electrode and source electrode are formed on the Semiconductor substrate of the first side wall layer, second side wall layer and the 3rd side wall layer both sides.
It is thus clear that; In the manufacture method of a kind of semiconductor device provided by the present invention; Before the silicon dioxide that adopts the wet-etching technology etching not covered by second side wall layer, to the silicon dioxide injecting nitrogen ion that is not covered by second side wall layer, and the silicon dioxide that is covered by second side wall layer is not injected into the nitrogen ion; Like this; Do not had the difference of significant etch rate by second side wall layer silicon dioxide that covers and the silicon dioxide that is covered by second side wall layer, after the silicon dioxide etching that is not covered by second side wall layer finished, the silicon dioxide that is covered by second side wall layer was not etched basically yet; Avoid the formation of breach, thereby reduced the power consumption of semiconductor device.
Description of drawings
Fig. 1～Fig. 6 is the process generalized section of the manufacture method of semiconductor device in the prior art.
The flow chart of first embodiment of the manufacture method of Fig. 7 a kind of semiconductor device provided by the present invention.
Fig. 8～Figure 15 is the process generalized section of first embodiment of the manufacture method of a kind of semiconductor device provided by the present invention.
The flow chart of second embodiment of the manufacture method of Figure 16 a kind of semiconductor device provided by the present invention.
Figure 17～Figure 24 is the process generalized section of second embodiment of the manufacture method of a kind of semiconductor device provided by the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below scheme according to the invention is done to specify further with reference to the accompanying drawing embodiment that develops simultaneously.
Core concept of the present invention is: before the silicon dioxide that adopts the wet-etching technology etching not covered by second side wall layer; To the silicon dioxide injecting nitrogen ion that is not covered by second side wall layer to improve the wet-etch rate of institute's injection zone; And the silicon dioxide that is covered by second side wall layer is not injected into the nitrogen ion; Like this; The silicon dioxide that is not covered by second side wall layer is compared with the silicon dioxide that is covered by second side wall layer has etch rate faster, and after the silicon dioxide etching that is not covered by second side wall layer finished, the silicon dioxide that is covered by second side wall layer was not etched basically; Avoid the formation of breach, reduced the power consumption of semiconductor device.
Through two embodiment the present invention is described in detail below.
First embodiment
The flow chart of first embodiment of the manufacture method of Fig. 7 a kind of semiconductor device provided by the present invention, as shown in Figure 7, this method comprises:
So far, this flow process finishes.
Fig. 8～Figure 15 is the process generalized section of first embodiment of the manufacture method of a kind of semiconductor device provided by the present invention, and this method mainly comprises:
Step 201 referring to Fig. 8, provides semi-conductive substrate 1001, at Semiconductor substrate 1001 superficial growth gate oxides 1002 and deposit polysilicon 1003, and utilizes technologies such as photoetching, etching and ion injection to form grid structure.
Step 202 referring to Fig. 9, is carried out LDD and is injected, and on the Semiconductor substrate 1001 of grid structure both sides, forms lightly doped drain 1004 and light dope source electrode 1005.
Step 203 is referring to Figure 10, at Semiconductor substrate 1001 surface deposition silica 1s 006.
Silica 1 006 covers Semiconductor substrate 1001 surfaces, grid structure upper surface and grid structure two sides.
Step 204 is referring to Figure 11, at silica 1 006 surface deposition silicon nitride 1007.
Step 205 referring to Figure 12, adopts the dry etch process etching to cover the silicon nitride 1007 on grid structure upper surface and Semiconductor substrate 1001 surfaces, and the silicon nitride 1007 that covers the grid structure two sides forms second side wall layer 1008.
Above-mentioned steps 201 to 205 is identical with prior art, will not give unnecessary details here.
Step 206 referring to Figure 13, is not injected nitrogen (N) ion by the silica 1 006 and second side wall layer 1008 that second side wall layer 1008 covers to Semiconductor substrate 1001 surfaces.
In this step, to the semiconductor substrate surface injecting nitrogen ion, but because energy and dosage are selected more suitablely; And a part of silicon dioxide is covered by second side wall layer, and actual have only semiconductor substrate surface not to be doped the nitrogen ion by the silicon dioxide and second side wall layer that second side wall layer covers, behind the doping nitrogen ion; Can improve the wet-etch rate of institute's injection zone; In the doping process, the silicon dioxide of second side wall layer below is owing to covered by second side wall layer, so it is not injected into the nitrogen ion; Its silicon dioxide than institute's injection zone has slow wet-etch rate; Like this, when follow-up when carrying out wet etching, the silicon dioxide that is covered by second side wall layer does not have the difference of significant etch rate with the silicon dioxide below second side wall layer; Even there is isotropic influence of wet etching; After the silicon dioxide etching that is not covered by second side wall layer finished, the silicon dioxide of second side wall layer below was not etched basically yet, has avoided the formation of breach.
In order to clearly illustrate that zones of different has different wet-etch rate among Figure 13; Shown in figure 13; Wherein zone shown in the solid line circle has been injected into the nitrogen ion; It has wet-etch rate faster, and zone shown in the dashed circle is not injected into the nitrogen ion, and it has slower wet-etch rate.
In addition, though second side wall layer also has been injected into the nitrogen ion, can not influence the performance of second side wall layer.
Preferably, the dosage of nitrogen ion injection is 3 * 10
14Individual atom/cm
2To 4 * 10
15Individual atom/cm
2, the energy that the nitrogen ion injects be 2000 electron-volts (eV) to 30000 electron-volts (eV), to be-0.5 degree spend to 0.5 the angle of ion beam and vertical direction.
Step 207 referring to Figure 14, adopts the silica 1 006 that is not covered by second side wall layer on wet-etching technology etched wafer surface, forms the first side wall layer 1009.
The method of wet etching is identical with prior art.
Need to prove that even the silicon dioxide of wafer surface has been doped the nitrogen ion, but it is identical with prior art with process conditions that silicon dioxide is carried out the solution of wet etching.
Step 208 referring to Figure 15, is carried out ion and is injected, thereby forms drain electrode 1010 and source electrode 1011.
In addition; Before step 208; Also can further comprise: deposit is used to form the silicon dioxide (scheming not shown) of the 3rd side wall layer; And the silicon dioxide that is used to form the 3rd side wall layer covers the surface of second side wall layer 1008 of Semiconductor substrate 1001 surfaces, grid structure upper surface and grid structure two sides; Adopt the wet-etching technology etching to cover the silicon dioxide on Semiconductor substrate 1001 surfaces, the silicon dioxide that covers second side wall layer, 1008 surfaces of grid structure upper surface and grid structure two sides forms the 3rd side wall layer.
The drain electrode 1010 and the source electrode 1011 that then form in the step 208 are positioned on the Semiconductor substrate 1001 of the first side wall layer 1006, second side wall layer 1008 and the 3rd side wall layer both sides.
So far, this flow process finishes.
Second embodiment
The flow chart of second embodiment of the manufacture method of Figure 16 a kind of semiconductor device provided by the present invention, shown in figure 16, this method comprises:
So far, this flow process finishes.
Figure 17～Figure 24 is the process generalized section of second embodiment of the manufacture method of a kind of semiconductor device provided by the present invention, and this method mainly comprises:
Step 301 referring to Figure 17, provides semi-conductive substrate 1001, at Semiconductor substrate 1001 superficial growth gate oxides 1002 and deposit polysilicon 1003, and utilizes technologies such as photoetching, etching and ion injection to form grid structure.
Step 302 referring to Figure 18, is carried out LDD and is injected, and on the Semiconductor substrate 1001 of grid structure both sides, forms lightly doped drain 1004 and light dope source electrode 1005.
Step 303 is referring to Figure 19, at Semiconductor substrate 1001 surface deposition silica 1s 006.
Silica 1 006 covers Semiconductor substrate 1001 surfaces, grid structure upper surface and grid structure two sides.
Step 304 is referring to Figure 20, at silica 1 006 surface deposition silicon nitride 1007.
Above-mentioned steps 301 to 304 is identical with prior art, will not give unnecessary details here.
Step 305, referring to Figure 21, silica 1 006 and silicon nitride 1007 injecting nitrogen ions to Semiconductor substrate 1001 surfaces.
In this step; To the semiconductor substrate surface injecting nitrogen ion; But because energy and dosage are selected more suitablely; And preset second side wall layer near the grid structure both sides has bigger thickness, so the silicon dioxide of (promptly preset second side wall layer below) that silicon nitride covered of grid structure two sides is not doped the nitrogen ion.
Shown in figure 21, wherein zone shown in the solid line circle has been injected into the nitrogen ion, and it has wet-etch rate faster, and zone shown in the dashed circle is not injected into the nitrogen ion, and it has slower wet-etch rate.
The injection energy of nitrogen ion and dosage are slightly larger than the injection energy and the dosage of the related nitrogen ion of step 206 in the present embodiment; This be because: the purpose of injecting nitrogen ion is the etch rate of the silicon dioxide accelerating not to be covered by second side wall layer, so the nitrogen ion that is injected in this step must be able to pass silicon nitride and get into the inside of silicon dioxide.
Preferably, the dosage of nitrogen ion injection is 5 * 10
14Individual atom/cm
2To 8 * 10
15Individual atom/cm
2, the energy that the nitrogen ion injects be 20000 electron-volts (eV) to 50000 electron-volts (eV), to be-0.5 degree spend to 0.5 the angle of ion beam and vertical direction.
Step 306, referring to Figure 22, adopt the dry etch process etching cover grid structure upper surface and Semiconductor substrate 1001 surfaces silicon nitride 1007, cover silicon nitride 1007 formation second side wall layer 1008 of grid structure two sides.
The method of dry etching is identical with prior art.
Need to prove that even the silicon nitride of wafer surface has been doped the nitrogen ion, but it is identical with prior art with process conditions that silicon nitride is carried out the gas of dry etching.
Step 307, referring to Figure 23, the silica 1 006 that adopts wet-etching technology etched wafer surface not covered by second side wall layer forms the first side wall layer 1009.
The method of wet etching is identical with prior art.
Need to prove that even the silicon dioxide of wafer surface has been doped the nitrogen ion, but it is identical with prior art with process conditions that silicon dioxide is carried out the solution of wet etching.
Step 308 referring to Figure 24, is carried out ion and is injected, thereby forms drain electrode 1010 and source electrode 1011.
In addition; Before step 208; Also can further comprise: deposit is used to form the silicon dioxide (scheming not shown) of the 3rd side wall layer; And the silicon dioxide that is used to form the 3rd side wall layer covers the surface of second side wall layer 1008 of Semiconductor substrate 1001 surfaces, grid structure upper surface and grid structure two sides; Adopt the wet-etching technology etching to cover the silicon dioxide on Semiconductor substrate 1001 surfaces, the silicon dioxide that covers second side wall layer, 1008 surfaces of grid structure upper surface and grid structure two sides forms the 3rd side wall layer.
The drain electrode 1010 and the source electrode 1011 that then form in the step 208 are positioned on the Semiconductor substrate 1001 of the first side wall layer 1006, second side wall layer 1008 and the 3rd side wall layer both sides.
So far, this flow process finishes.
In the manufacture method of a kind of semiconductor device provided by the present invention; Before the silicon dioxide that adopts the wet-etching technology etching not covered by second side wall layer, to the silicon dioxide injecting nitrogen ion that is not covered by second side wall layer, and the silicon dioxide that is covered by second side wall layer is not injected into the nitrogen ion; Like this; Do not had the difference of significant etch rate by second side wall layer silicon dioxide that covers and the silicon dioxide that is covered by second side wall layer, after the silicon dioxide etching that is not covered by second side wall layer finished, the silicon dioxide that is covered by second side wall layer was not etched basically yet; Avoid the formation of breach, reduced the power consumption of semiconductor device.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. the manufacture method of a semiconductor device, this method comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Deposit is used to form the silicon dioxide and the silicon nitride that is used to form second side wall layer of the first side wall layer successively; And said silicon dioxide and the said silicon nitride that is used to form second side wall layer that is used to form the first side wall layer covers semiconductor substrate surface, grid structure upper surface and grid structure two sides; Adopt the dry etch process etching to cover the silicon nitride of grid structure upper surface and semiconductor substrate surface, the silicon nitride that covers the grid structure two sides forms second side wall layer;
The silicon dioxide and the second side wall layer injecting nitrogen ion that are not covered to semiconductor substrate surface by second side wall layer;
The silicon dioxide that adopts the wet-etching technology etching not covered by second side wall layer forms the first side wall layer;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of the first side wall layer and the second side wall layer both sides, form drain electrode and source electrode.
2. method according to claim 1 is characterized in that, the dosage that said nitrogen ion injects is 3 * 10
14Individual atom/cm
2To 4 * 10
15Individual atom/cm
2
3. method according to claim 2 is characterized in that, the energy that said nitrogen ion injects is 2000 electron-volts to 30000 electron-volts.
4. method according to claim 3 is characterized in that, the angle of ion beam and vertical direction was that-0.5 degree is to 0.5 degree when said nitrogen ion injected.
5. method according to claim 1 is characterized in that, before Semiconductor substrate was carried out the ion injection, this method further comprised:
Deposit is used to form the silicon dioxide of the 3rd side wall layer; And the said silicon dioxide that is used to form the 3rd side wall layer covers the surface of second side wall layer of semiconductor substrate surface, grid structure upper surface and grid structure two sides; Adopt the wet-etching technology etching to cover the silicon dioxide of semiconductor substrate surface, the silicon dioxide that covers second side wall layer surface of grid structure upper surface and grid structure two sides forms the 3rd side wall layer;
Said drain electrode and source electrode are formed on the Semiconductor substrate of the first side wall layer, second side wall layer and the 3rd side wall layer both sides.
6. the manufacture method of a semiconductor device, this method comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Deposit is used to form the silicon dioxide and the silicon nitride that is used to form second side wall layer of the first side wall layer successively; And said silicon dioxide and the said silicon nitride that is used to form second side wall layer that is used to form the first side wall layer covers semiconductor substrate surface, grid structure upper surface and grid structure two sides; To silicon dioxide and silicon nitride injecting nitrogen ion, wherein the silicon dioxide that silicon nitride covered of grid structure two sides is not injected into the nitrogen ion;
Adopt the dry etch process etching to cover the silicon nitride of grid structure upper surface and semiconductor substrate surface, the silicon nitride that covers the grid structure two sides forms second side wall layer;
The silicon dioxide that adopts the wet-etching technology etching not covered by second side wall layer forms the first side wall layer;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of the first side wall layer and the second side wall layer both sides, form drain electrode and source electrode.
7. method according to claim 6 is characterized in that, the dosage that said nitrogen ion injects is 5 * 10
14Individual atom/cm
2To 8 * 10
15Individual atom/cm
2
8. method according to claim 7 is characterized in that, the energy that said nitrogen ion injects is 20000 electron-volts to 50000 electron-volts.
9. method according to claim 8 is characterized in that, the angle of ion beam and vertical direction was that-0.5 degree is to 0.5 degree when said nitrogen ion injected.
10. method according to claim 6 is characterized in that, before Semiconductor substrate was carried out the ion injection, this method further comprised:
Deposit is used to form the silicon dioxide of the 3rd side wall layer; And the said silicon dioxide that is used to form the 3rd side wall layer covers the surface of second side wall layer of semiconductor substrate surface, grid structure upper surface and grid structure both sides; Adopt the wet-etching technology etching to cover the silicon dioxide of semiconductor substrate surface, the silicon dioxide that covers second side wall layer surface of grid structure upper surface and grid structure both sides forms the 3rd side wall layer;
Said drain electrode and source electrode are formed on the Semiconductor substrate of the first side wall layer, second side wall layer and the 3rd side wall layer both sides.
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| CN107591398A (en) * | 2016-07-06 | 2018-01-16 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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