CN102456556A - Formation method of metal silicide - Google Patents
Formation method of metal silicide Download PDFInfo
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- CN102456556A CN102456556A CN2010105102130A CN201010510213A CN102456556A CN 102456556 A CN102456556 A CN 102456556A CN 2010105102130 A CN2010105102130 A CN 2010105102130A CN 201010510213 A CN201010510213 A CN 201010510213A CN 102456556 A CN102456556 A CN 102456556A
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- metal silicide
- semiconductor substrate
- grid structure
- silicide
- blocking layer
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Abstract
The invention discloses a formation method of metal silicide. The method comprises the following steps: after depositing a metal silicide barrier layer, carrying out ultraviolet ray irradiation, etching the metal silicide barrier layer, exposing a semiconductor substrate surface or a grid structure corresponding to a contact hole formation area, depositing metal, carrying out rapid annealing processing, and forming the metal silicide on the exposed semiconductor substrate surface or on an exposed grid structure surface. By employing the method in the invention, difference of unit area resistance values of metal silicide barrier layers of a same batch of products can be reduced.
Description
Technical field
The present invention relates to semiconductor technology, particularly a kind of formation method of metal silicide.
Background technology
Along with the development of semiconductor fabrication process, dimensions of semiconductor devices is dwindled the lifting that has brought relative contact resistance, and in order to reduce relative contact resistance, the formation technology of metal silicide (salicide) has obtained using widely.Fig. 1 a～Fig. 6 a is the process generalized section of the formation method of metal silicide in the prior art, and this method mainly comprises:
Step 101 referring to Fig. 1 a, provides semi-conductive substrate 1001, at Semiconductor substrate 1001 superficial growth gate oxides 1002, and deposit polysilicon 1003, utilize technologies such as photoetching, etching and ion injection to form grid structure.
In this step, at first carry out the growth of gate oxide 1002; Then, through chemical vapor deposition method, at wafer surface deposit one deck polysilicon 1003, thickness is about 500～2000 dusts; Afterwards, through technologies such as photoetching, etching and ion injections, produce grid structure, grid structure according to the invention comprises grid that is made up of polysilicon 1003 and the gate oxide 1002 that is positioned at the grid below.
Step 102 referring to Fig. 2 a, is carried out lightly doped drain (LDD) to Semiconductor substrate 1001 and is injected, and on the Semiconductor substrate 1001 of grid structure both sides, forms lightly doped drain 1004 and light dope source electrode 1005.
Under the promotion of demands such as semiconductor device miniatureization, densification, high speed and system integration, the width of grid structure constantly reduces, and the channel length of its below also constantly reduces; Yet the voltage of drain terminal does not significantly reduce; This has just caused the increase at the electric field of drain terminal, and near the electric charge making has bigger energy, and these hot carriers might be passed through gate oxide; Caused the increase of leakage current; Therefore, need to adopt some means to reduce the possibility that leakage current occurs, inject like LDD.
Step 103 is referring to Fig. 3 a, on Semiconductor substrate 1001 surfaces deposit silicon dioxide (SiO successively
2) and silicon nitride (Si
3N
4), adopt the silicon nitride on dry etch process etched wafer surface then, form second side wall layer 1006, adopt the silicon dioxide on wet-etching technology etched wafer surface, form the first side wall layer 1007.
The common side wall layer that constitute semiconductor device of the first side wall layer 1007 and second side wall layer 1006 can be used for preventing that the follow-up source of carrying out from leaking when injecting and too leak break-through near raceway groove so that generation source, produce leakage current thereby diffusion takes place the impurity that promptly injects.
In addition, possibly also comprise the additive method that forms side wall layer in the prior art, for example: side wall layer also might be the NON structure; That is to say that side wall layer comprises: the first side wall layer, second side wall layer and the 3rd side wall layer, wherein, the first side wall layer and the 3rd side wall layer are silicon nitride; Second side wall layer is a silicon dioxide, and the formation method is: at deposited silicon nitride, adopt the dry etch process etch silicon nitride then; Silicon nitride overlies gate structure surface after the etching forms the 3rd side wall layer; Deposition of silica and silicon nitride successively; Adopt the dry etch process etch silicon nitride; Adopt the wet-etching technology etching silicon dioxide, silicon nitride after the etching and silicon dioxide cover the 3rd side wall layer surface, form the first side wall layer and second side wall layer; The first side wall layer is the silicon nitride after the etching, and second side wall layer is the silicon dioxide after the etching.
Step 104 referring to Fig. 4 a, is carried out ion to Semiconductor substrate 1001 and is injected, thereby forms drain electrode 1008 and source electrode 1009.
Need to prove; Because the first side wall layer 1007 and second side wall layer 1006 can be used as the protective layer of grid structure; Therefore the ion that injects is difficult to get into grid, thereby only the Semiconductor substrate 1001 of grid both sides has been realized injection, and final drain electrode 1008 and the source electrode 1009 of forming.
Step 105, referring to Fig. 5 a, plated metal silicide barrier layer (salicide block oxide) 1010.
Blocking layer of metal silicide 1010 can be Si oxide, for example silicon dioxide (SiO
2).
Step 106; Referring to Fig. 6 a, blocking layer of metal silicide 1010 is carried out etching, contact hole is formed area relative blocking layer of metal silicide 1010 remove; Expose contact hole and form corresponding Semiconductor substrate 1001 surfaces, zone or grid structure surface; Plated metal carries out short annealing then and handles (RTA) and since metal can with pasc reaction; But not can with Si oxide such as silicon dioxde reaction, form metal silicide 1011 so metal only can react with the Semiconductor substrate that exposes 1001 surfaces or grid structure surface.
Follow-up can be with the metal removal that does not react, for example can adopt acid solution to remove responseless metal on the blocking layer of metal silicide 1010.
In this step, the metal of deposition can be (Ni), titanium (Ti) or cobalt (Co) and waits any metal, and correspondingly, formed metal silicide 1011 can be tweezer base silicide, titanium base silicide or cobalt-based silicide etc.
It is thus clear that after this step was finished, the metal silicide 1011 that is equivalent to form was embedded in the blocking layer of metal silicide 1010; In the subsequent technique flow process; Contact hole will be formed on the metal silicide 1011, that is to say, the bottom of each contact hole of follow-up formation is a metal silicide 1011; Metal silicide 1011 is a kind of chemical combination attitudes that formed through physical-chemical reaction by metal and silicon, and its conductive characteristic is between metal and silicon.
So far, this flow process finishes.
Yet; In practical application, when at step 105 plated metal silicide barrier layer, because the performance difference of different platform; When being positioned at wafer on the different platform and carrying out the step of plated metal silicide barrier layer; Deposition rate is incomplete same, and this just might make that the density of the blocking layer of metal silicide between the different chips is significantly different in a collection of product, and when follow-up execution in step 106 is carried out the short annealing processing; The ion that injects in grid, lightly doped drain, light dope source electrode, drain electrode and the source electrode can pass blocking layer of metal silicide to a certain extent and spread outward to blocking layer of metal silicide; Because the density of the blocking layer of metal silicide between the different chips is significantly different, the amount of ions that then diffuses to blocking layer of metal silicide also exists than big-difference, makes to differ greatly with a collection of performance of products; Can find through measuring; This performance difference is mainly reflected in the unit area resistance value difference of the blocking layer of metal silicide of a collection of product different bigger, and on principle, the amount of ions that the diffuses to blocking layer of metal silicide unit area resistance value of blocking layer of metal silicide more at most is big more.And in practical application, we expect to have consistency with the unit area resistance value of the blocking layer of metal silicide of a collection of product, and are visible, and the method for prior art is difficult to realize above-mentioned purpose.
Summary of the invention
In view of this, the present invention provides a kind of formation method of metal silicide, can reduce the difference with the unit area resistance value of the blocking layer of metal silicide of a collection of product.
For solving the problems of the technologies described above, technical scheme of the present invention is achieved in that
A kind of formation method of metal silicide, this method comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Form side wall layer in the grid structure both sides;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of side wall layer both sides, form drain electrode and source electrode;
Behind the plated metal silicide barrier layer, carry out ultraviolet irradiation;
Blocking layer of metal silicide is carried out etching; After exposing contact hole and forming zone corresponding semiconductor substrate surface or grid structure; Plated metal carries out short annealing then and handles, and forms metal silicide at semiconductor substrate surface that exposes or grid structure surface.
Said blocking layer of metal silicide is a Si oxide.
Said Si oxide is a silicon dioxide.
The temperature of said ultraviolet irradiation is 100 ℃ to 500 ℃, and the time of ultraviolet irradiation is 0.5 minute to 20 minutes.
The environment of said ultraviolet irradiation is an airtight chamber; Air pressure in the said airtight chamber is that 10 holders are to 780 holders.
The metal of said deposition is nickel, titanium or cobalt;
The metal silicide of said formation is tweezer base silicide, titanium base silicide or cobalt-based silicide.
Thus it is clear that, in the formation method of a kind of metal silicide provided by the present invention, behind the plated metal silicide barrier layer; Carry out ultraviolet irradiation; And then blocking layer of metal silicide carried out etching, and after exposing contact hole and forming zone corresponding semiconductor substrate surface or grid structure, plated metal; Carry out short annealing at last and handle, form metal silicide at semiconductor substrate surface that exposes or grid structure surface.Like this; Owing to carried out ultraviolet irradiation; Make density with the blocking layer of metal silicide of a collection of product all have and promote and be stabilized on the essentially identical density, when follow-up when carrying out short annealing and handling, because the density of the blocking layer of metal silicide between the different chips is roughly the same; It is also basic identical that then different chips diffuses to the amount of ions of blocking layer of metal silicide, therefore reduced the difference with the unit area resistance value of the blocking layer of metal silicide of a collection of product.
Description of drawings
Fig. 1 a～Fig. 6 a is the process generalized section of the formation method of metal silicide in the prior art.
The flow chart of the formation method of Fig. 1 a kind of metal silicide provided by the present invention.
Fig. 1 b～Fig. 7 b is the process generalized section of embodiment of the formation method of a kind of metal silicide provided by the present invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, scheme according to the invention is done to specify further.
Core concept of the present invention is: behind the plated metal silicide barrier layer; Carry out ultraviolet irradiation, and then blocking layer of metal silicide is carried out etching, after exposing contact hole and forming zone corresponding semiconductor substrate surface or grid structure; Plated metal; Carry out short annealing at last and handle, form metal silicide at semiconductor substrate surface that exposes or grid structure surface, owing to carried out ultraviolet irradiation behind the plated metal silicide barrier layer; Making density with the blocking layer of metal silicide of a collection of product all have promotes and is stabilized on the essentially identical density; When follow-up when carrying out short annealing and handling, it is also basic identical that different chips diffuses to the amount of ions of blocking layer of metal silicide, therefore can reduce the difference with the unit area resistance value of the blocking layer of metal silicide of a collection of product.
The flow chart of the formation method of Fig. 1 a kind of metal silicide provided by the present invention, as shown in Figure 1, this method comprises:
So far, this flow process finishes.
Below, through an embodiment formation method of a kind of metal silicide provided by the present invention is described in detail.
Fig. 1 b～Fig. 7 b is the process generalized section of embodiment of the formation method of a kind of metal silicide provided by the present invention, and this method mainly comprises:
Step 201 referring to Fig. 1 b, provides semi-conductive substrate 1001, at Semiconductor substrate 1001 superficial growth gate oxides 1002 and deposit polysilicon 1003, and utilizes technologies such as photoetching, etching and ion injection to form grid structure.
Step 202 referring to Fig. 2 b, is carried out LDD and is injected, and on the Semiconductor substrate 1001 of grid structure both sides, forms lightly doped drain 1004 and light dope source electrode 1005.
Step 203 is referring to Fig. 3 b, on Semiconductor substrate 1001 surfaces deposit silicon dioxide (SiO successively
2) and silicon nitride (Si
3N
4), adopt the silicon nitride on dry etch process etched wafer surface then, form second side wall layer 1006 in the two sides of grid structure, adopt the silicon dioxide on wet-etching technology etched wafer surface, form the first side wall layer 1007 in the grid structure two sides.
Certainly, also can adopt additive method of the prior art to form the side wall layer of other structures, the method that forms side wall layer among Fig. 3 b is merely and illustrates.
Step 204 referring to Fig. 4 b, is carried out ion to Semiconductor substrate 1001 and is injected, thereby forms drain electrode 1008 and source electrode 1009.
Step 205, referring to Fig. 5 b, plated metal silicide barrier layer (salicide block oxide) 1010.
Blocking layer of metal silicide 1010 can be Si oxide, for example silicon dioxide (SiO
2).
Above-mentioned steps 201 to 205 is identical with prior art, will not give unnecessary details here.
Step 206 referring to Fig. 6 b, is carried out ultraviolet irradiation.
In this step; When wafer is carried out ultraviolet irradiation; Can improve the density of blocking layer of metal silicide; Make the blocking layer of metal silicide of different product all become fine and close more, and be stabilized on the essentially identical density, thereby solved the different bigger problem of unit area resistance value difference owing to the blocking layer of metal silicide of the different same a collection of products that bring of blocking layer of metal silicide deposition rate.
Specifically; Though when when being positioned at wafer on the different platform and carrying out the step of plated metal silicide barrier layer; Deposition rate is incomplete same, makes that the density of the blocking layer of metal silicide between the different chips is significantly different in a collection of product, yet; Owing to carried out ultraviolet irradiation in this step; Make density with the blocking layer of metal silicide of a collection of product all have and promote and be stabilized on the essentially identical density, when follow-up when carrying out short annealing and handling, because the density of the blocking layer of metal silicide between the different chips is roughly the same; Therefore then the amount of ions of the grid of different chips, lightly doped drain, light dope source electrode, drain electrode and source electrode outdiffusion to blocking layer of metal silicide is also basic identical, makes with the unit area resistance value of the blocking layer of metal silicide of a collection of product basic identical.
Preferably, the temperature of ultraviolet irradiation is 100 ℃ to 500 ℃, and the time of ultraviolet irradiation is 0.5 minute to 20 minutes.
In addition, during ultraviolet irradiation wafer is placed airtight chamber, the air pressure in the airtight chamber is that 10 holders (torr) are to 780 holders (torr).
Need to prove that the ultraviolet irradiation in this step has significantly changed the density of blocking layer of metal silicide, but other structures of semiconductor device are not influenced, can not reduce other performances of semiconductor device.
Step 207; Referring to Fig. 7 b, blocking layer of metal silicide 1010 is carried out etching, contact hole is formed area relative blocking layer of metal silicide 1010 remove; Expose contact hole and form corresponding Semiconductor substrate 1001 surfaces, zone or grid structure surface; Plated metal carries out short annealing then and handles (RTA), on the Semiconductor substrate that exposes 1001 surfaces or the grid structure surface form metal silicide 1011; Follow-up can be with the metal removal that does not react, for example can adopt acid solution to remove responseless metal on the blocking layer of metal silicide 1010.
The metal of deposition can be nickel (Ni), titanium (Ti) or cobalt (Co) and waits any metal, and correspondingly, formed metal silicide 1011 can be tweezer base silicide, titanium base silicide or cobalt-based silicide.
This step is identical with prior art, no longer details.
So far, this flow process finishes.
To sum up, in the formation method of a kind of metal silicide provided by the present invention, behind the plated metal silicide barrier layer; Carry out ultraviolet irradiation; And then blocking layer of metal silicide carried out etching, and after exposing contact hole and forming zone corresponding semiconductor substrate surface or grid structure, plated metal; Carry out short annealing at last and handle, form metal silicide at semiconductor substrate surface that exposes or grid structure surface.Like this; Owing to carried out ultraviolet irradiation; Make density with the blocking layer of metal silicide of a collection of product all have and promote and be stabilized on the essentially identical density, when follow-up when carrying out short annealing and handling, because the density of the blocking layer of metal silicide between the different chips is roughly the same; It is also basic identical that then different chips diffuses to the amount of ions of blocking layer of metal silicide, therefore can reduce the difference with the unit area resistance value of the blocking layer of metal silicide of a collection of product.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. the formation method of a metal silicide, this method comprises:
Form grid structure at semiconductor substrate surface;
Carry out lightly doped drain LDD to Semiconductor substrate and inject, on the Semiconductor substrate of grid structure both sides, form lightly doped drain and light dope source electrode;
Form side wall layer in the grid structure both sides;
Carry out ion to Semiconductor substrate and inject, on the Semiconductor substrate of side wall layer both sides, form drain electrode and source electrode;
Behind the plated metal silicide barrier layer, carry out ultraviolet irradiation;
Blocking layer of metal silicide is carried out etching; After exposing contact hole and forming zone corresponding semiconductor substrate surface or grid structure; Plated metal carries out short annealing then and handles, and forms metal silicide at semiconductor substrate surface that exposes or grid structure surface.
2. method according to claim 1 is characterized in that, said blocking layer of metal silicide is a Si oxide.
3. method according to claim 2 is characterized in that, said Si oxide is a silicon dioxide.
4. method according to claim 1 is characterized in that, the temperature of said ultraviolet irradiation is 100 ℃ to 500 ℃, and the time of ultraviolet irradiation is 0.5 minute to 20 minutes.
5. method according to claim 4 is characterized in that, the environment of said ultraviolet irradiation is an airtight chamber; Air pressure in the said airtight chamber is that 10 holders are to 780 holders.
6. method according to claim 1 is characterized in that, the metal of said deposition is nickel, titanium or cobalt;
The metal silicide of said formation is tweezer base silicide, titanium base silicide or cobalt-based silicide.
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| CN2010105102130A CN102456556A (en) | 2010-10-18 | 2010-10-18 | Formation method of metal silicide |
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| CN2010105102130A CN102456556A (en) | 2010-10-18 | 2010-10-18 | Formation method of metal silicide |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515293A (en) * | 2012-06-25 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN109148272A (en) * | 2017-06-16 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN111799159A (en) * | 2020-09-09 | 2020-10-20 | 南京晶驱集成电路有限公司 | Method and system for detecting detection sensitivity of semiconductor equipment |
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| US20050104135A1 (en) * | 2003-10-02 | 2005-05-19 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN1949464A (en) * | 2005-10-14 | 2007-04-18 | 联华电子股份有限公司 | Method for mfg. silicon nitride layer and method for mfg. semiconductor element |
| US20090004800A1 (en) * | 2007-06-29 | 2009-01-01 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices |
-
2010
- 2010-10-18 CN CN2010105102130A patent/CN102456556A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050104135A1 (en) * | 2003-10-02 | 2005-05-19 | Sanyo Electric Co., Ltd. | Semiconductor device and manufacturing method thereof |
| CN1949464A (en) * | 2005-10-14 | 2007-04-18 | 联华电子股份有限公司 | Method for mfg. silicon nitride layer and method for mfg. semiconductor element |
| US20090004800A1 (en) * | 2007-06-29 | 2009-01-01 | Samsung Electronics Co., Ltd. | Methods of manufacturing semiconductor devices |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103515293A (en) * | 2012-06-25 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Method for forming contact hole |
| CN103515293B (en) * | 2012-06-25 | 2016-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of method for the formation of contact hole |
| CN109148272A (en) * | 2017-06-16 | 2019-01-04 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN109148272B (en) * | 2017-06-16 | 2020-10-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and method of forming the same |
| CN111799159A (en) * | 2020-09-09 | 2020-10-20 | 南京晶驱集成电路有限公司 | Method and system for detecting detection sensitivity of semiconductor equipment |
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