CN103165440A - Manufacturing method of high-dielectric-constant metal grid electrode semiconductor device - Google Patents
Manufacturing method of high-dielectric-constant metal grid electrode semiconductor device Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
Abstract
The invention discloses a manufacturing method of a high-dielectric-constant metal grid electrode semiconductor device. The method includes: a semiconductor device with a high-dielectric-constant metal grid electrode structure is provided, the semiconductor device comprises a substrate, a high-dielectric-constant layer and a metal grid electrode are formed on the substrate, and side wall oxidation layers are arranged on two sides of the high-dielectric-constant layer and two sides of the metal grid electrode; and low-temperature annealing is carried out on the semiconductor device. After the high-dielectric-constant metal grid electrode structure is formed, the low-temperature annealing is carried out on the semiconductor device, defects of the metal grid electrode are reduced, threshold voltages are reduced, performance of the semiconductor device is improved, meanwhile in the annealing process, and the phenomenon that due to the fact that the temperature of the annealing is too high, grid electrode metal evaporates to pollute an annealing chamber and then the device is damaged is avoided.
Description
Technical field
The present invention relates to semiconductor fabrication, particularly a kind of high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method.
Background technology
High-k (High-K) metal gate stacks is introduced at the 45nm process node, the technology barrier that is faced to solve traditional grid, as reduce EOT (Equivalent Oxide Thickness, the equivalence gate oxide thickness) and reduction Vt (threshold voltage) etc., thus promoted the performance of semiconductor device.
The technological process of existing a kind of high-dielectric constant metal grid utmost point (HKMG, High-K Metal Gate) semiconductor device as an example of CMOS (complementary metal oxide semiconductors (CMOS)) device example and referring to Fig. 1 a～Fig. 1 d, is described below.
As shown in Figure 1a, CMOS comprises nmos area and PMOS district, is formed with shallow trench isolation from (STI, Shallow Trench Isolation) 8 between nmos area and PMOS district; Be formed with the high dielectric layer 1 of NMOS on nmos area and be arranged on NMOS dummy poly 6 on the high dielectric layer 1 of NMOS, be formed with NMOS sidewall oxide 4 in the both sides of the high dielectric layer 1 of NMOS and NMOS dummy poly 6, form the NMOS grid structure; Be formed with equally the PMOS sidewall oxide 5 of the high dielectric layer 2 of PMOS, PMOS dummy poly 7 and the high dielectric layer 2 of PMOS and PMOS dummy poly 7 both sides in the PMOS district, form the PMOS grid structure; After forming above-mentioned semiconductor structure, deposition interlayer insulative layer 3 between NMOS sidewall oxide 4 and PMOS sidewall oxide 5 carries out cmp and removes unnecessary deposition materials, to expose dummy poly 6 and 7.
Then as shown in Fig. 1 b, form the photoresist 9 that covers the NMOS grid structure on the NMOS grid structure, remove PMOS dummy poly 7 by dry etching.
As shown in Fig. 1 c, after removing photoresist 9, deposition one deck PMOS metal work function layer 10 on whole CMOS, and on PMOS metal work function layer 10 depositing metal layers, as metallic aluminium (Al), carry out cmp, remove PMOS metal work function layer 10 and unnecessary metal on interlayer insulative layer 3, just formed like this PMOS metal gates 11 to expose interlayer insulative layer 3 on the position of former PMOS dummy poly 7.
As shown in Fig. 1 d, with same operation, mask covers the PMOS grid structure with photoresist, utilizes dry etching to remove NMOS dummy poly 6, removes the photoresist mask that covers PMOS, deposition NMOS metal work function layer and metal level, carry out cmp, remove NMOS metal work function layer 12 and metal level on interlayer insulative layer 3, so just formed NMOS metal gates 13 in the position of former NMOS dummy poly 6, and then, formed high-dielectric constant metal grid utmost point CMOS structure.
For further improving the performance of semiconductor device, in prior art after forming metal gate structure, device is carried out the high temperature anneal, as carry out 1000 ℃ of spike annealings (spike annealing), can reduce the metal gates defective, further reduce the threshold voltage vt of semiconductor device, thereby further improve the performance of semiconductor device.But, adopt the high temperature anneal to make metal gates produce evaporation of metal, thereby can pollute annealing chamber, even cause damage of equipment.
Summary of the invention
In view of this, the invention provides a kind of high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method, when promoting the HKMG performance of semiconductor device, avoid pollution and device damage to the annealing chamber.
Technical scheme of the present invention is achieved in that
A kind of high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method comprises:
The semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is provided, and described semiconductor device comprises substrate, is formed with high dielectric layer and metal gates on described substrate, is provided with sidewall oxide in the both sides of high dielectric layer and metal gates;
Described semiconductor device is carried out process annealing.
Further, the described semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is made by the following method:
Substrate is provided, forms successively high dielectric layer and dummy poly on described substrate, and form sidewall oxide in the both sides of high dielectric layer and dummy poly;
Remove dummy poly and form groove, plated metal grid in described groove is to form the semiconductor device of metal gate structure.
Further, described metal gates comprises metal work function layer and the metal level that is deposited on successively in described groove.
Further, after the semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is provided, described semiconductor device is carried out also comprising before process annealing: at described semiconductor device surface deposition one silicon nitride layer.Further, described silicon nitride layer thickness is 50～500
Further, adopt ultraviolet ray irradiation or microwave in described process annealing process, adopt D in annealing atmosphere
2, H
2Perhaps both mist, protective gas adopts N
2, Ar, NH
3The perhaps mist of at least two kinds of gases wherein, wherein, D
2Flow 0.1～5slm, H
2Flow 1～50slm, NH
3Flow 1～50slm, N
2Flow 1～100slm, Ar flow 1～100slm, the process annealing temperature is 200～500 ℃, the process annealing time is 10～120min.
Further, described annealing gas to chamber also comprises N
2, Ar and/or NH
3
Further, described semiconductor device is CMOS.
Further, described CMOS makes by the following method:
Definition nmos area and PMOS district on substrate, and between nmos area and PMOS district the formation shallow trench isolation from; Form respectively the high dielectric layer of NMOS and the high dielectric layer of PMOS in nmos area and PMOS district, and NMOS dummy poly and PMOS dummy poly, and in the both sides of the high dielectric layer of NMOS, NMOS dummy poly and the both sides of the high dielectric layer of PMOS, PMOS dummy poly form sidewall oxide;
Form interlayer insulative layer on substrate, and carry out cmp to expose dummy poly;
Form the photoresist that covers the NMOS grid structure, remove the PMOS dummy poly by dry etching;
Remove photoresist, deposition one deck PMOS metal work function layer on whole CMOS, and on PMOS metal work function layer depositing metal layers, carry out cmp to expose interlayer insulative layer, form the PMOS metal gates;
Form the photoresist that covers the PMOS grid structure, remove the NMOS dummy poly by dry etching;
Remove photoresist, deposition NMOS metal work function layer and metal level carry out cmp, remove NMOS metal work function layer and metal level on interlayer insulative layer, have formed the NMOS metal gates.
Further, after forming sidewall oxide, before forming interlayer insulative layer, also be included in the step of formation source-drain area in nmos area and PMOS district.
Further, after forming sidewall oxide, in PMOS district before the formation source-drain area, also be included in the step of embedment stress film in the PMOS district.
Further, described stress film material is SiGe.
Can find out from such scheme, high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method of the present invention, after forming the high-dielectric constant metal grid electrode structure, semiconductor device is carried out process annealing, make in annealing process, annealing chamber, cause damage of equipment are polluted in the gate metal generation evaporation of avoiding causing because annealing temperature is too high; And, adopting ultraviolet ray irradiation or microwave in the process annealing process, the annealing gas to chamber adopts D
2, H
2Perhaps both mists, make D in annealing process
2, H
2Be easy to penetrate in metal gates D
+, H
+The ion easily oxygen defect in metal gates is combined, and to reduce the defective of metal gates, regulates the metal gates work function, reduces threshold voltage, improves described performance of semiconductor device; In described semiconductor device surface deposited silicon nitride layer, because silicon nitride is comparatively fine and close, do not affecting D
2, H
2Perhaps both mists infiltrate in the situation of metal gates, can further guarantee in carrying out the process annealing process, and the metal material of grid can evaporation and diffusion, and pollutes the annealing chamber, cause damage of equipment.
Description of drawings
Fig. 1 a to Fig. 1 d is CMOS structure evolution schematic diagram in existing a kind of CMOS manufacture process;
Fig. 2 is high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method flow chart of the present invention;
Fig. 3 is the manufacture method flow chart of the high-dielectric constant metal grid electrode structure in the present invention;
Fig. 4 and Fig. 5 are for adopting CMOS structure evolution schematic diagram in the inventive method process;
Fig. 6 a is that NMOS does not adopt process annealing and adopts stress relief annealed threshold voltage variation curve chart;
Fig. 6 b is that PMOS does not adopt process annealing and adopts stress relief annealed threshold voltage variation curve chart.
In accompanying drawing, the title of each label representative is as follows:
1, the high dielectric layer of NMOS, 2, the high dielectric layer of PMOS, 3, interlayer insulative layer, 4, sidewall oxide, 6, the NMOS dummy poly, 7, the PMOS dummy poly, 8, shallow trench isolation from, 9, photoresist, 10, PMOS metal work function layer, 11, the PMOS metal gates, 12, NMOS metal work function layer, 13, the NMOS metal gates, 14, silicon nitride layer, 15 process annealings are processed, 21, do not adopt stress relief annealed NMOS threshold voltage curve, 22, adopt stress relief annealed NMOS threshold voltage curve, 31, do not adopt stress relief annealed PMOS threshold voltage curve, 32, adopt stress relief annealed PMOS threshold voltage curve
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in further detail.
As shown in Figure 2, high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method of the present invention comprises:
The semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is provided, and described semiconductor device comprises substrate, is formed with high dielectric layer and metal gates on described substrate, is provided with sidewall oxide in the both sides of high dielectric layer and metal gates;
Described semiconductor device is carried out process annealing.
Wherein, as shown in Figure 3, this semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is made by the following method:
Substrate is provided, forms successively high dielectric layer and dummy poly on described substrate, and form sidewall oxide in the both sides of high dielectric layer and dummy poly;
Remove dummy poly and form groove, plated metal grid in described groove is to form the semiconductor device of metal gate structure.
Wherein, described substrate can comprise any can be as the basic material that builds semiconductor device thereon, such as silicon substrate, perhaps make silicon substrate or the silicon-on-insulator substrate of an isolated area.High dielectric layer material can be selected HfO
2(hafnium oxide), the existing methods such as employing ald (ALD, Atomic Layer Deposition) deposit, and the deposition of the deposition of dummy poly and sidewall oxide, the removal of dummy poly, metal gates all can adopt existing techniques in realizing.
After the semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is provided, described semiconductor device is carried out can also comprising step before process annealing: at described semiconductor device surface deposition one silicon nitride layer.Described silicon nitride layer thickness is 50～500
Can adopt the existing methods such as chemical vapour deposition (CVD) (CVD) to deposit.
The deposition of this silicon nitride layer is mainly further to guarantee in follow-up process annealing process, and the metal material of grid can evaporation and diffusion, and pollutes the annealing chamber, cause damage of equipment.
Adopt ultraviolet ray irradiation or microwave in the process annealing process, annealing atmosphere adopts D
2(deuterium gas), H
2(hydrogen) or both mists, wherein D
2Flow 0.1～5slm, H
2Flow 1～50slm, the protective gas in annealing atmosphere can adopt N
2(nitrogen), Ar (argon gas), NH
3(ammonia) or N
2, Ar, NH
3The mist of at least two kinds of gases, wherein NH in three kinds of gas
3Flow 1～50slm, N
2Flow 1～100slm, Ar flow 1～100slm, the air pressure in the annealing chamber can be selected normal pressure (760Torr), and ultraviolet ray or microwave power can be 100～500W, and the process annealing temperature is 200～500 ℃, and the process annealing time is 10～120min.Adopt ultraviolet ray irradiation or microwave in the process annealing process, make D
2, H
2During perhaps both mists can be easy to penetrate into metal gates in the process annealing process, D
+, H
+The ion easily oxygen defect in metal gates is combined, and to reduce the metal gates defective, regulates the metal gates work function, reduces threshold voltage, improves performance of semiconductor device.
Now take CMOS as example, high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method of the present invention is further introduced.
Please refer to Fig. 1 a, a substrate be provided, definition nmos area and PMOS district on substrate, and between nmos area and PMOS district the formation shallow trench isolation from 8; Form respectively the high dielectric layer 1 of NMOS and the high dielectric layer 2 of PMOS in nmos area and PMOS district, and NMOS dummy poly 6 and PMOS dummy poly 7, and in the both sides of the high dielectric layer 1 of NMOS, NMOS dummy poly 6 and the both sides of the high dielectric layer 2 of PMOS, PMOS dummy poly 7 form sidewall oxide 4; Form interlayer insulative layer 3 on substrate, and carry out cmp (CMP) to expose NMOS dummy poly 6 and PMOS dummy poly 7.
As shown in Fig. 1 b, form the photoresist 9 that covers the NMOS grid structure on the NMOS grid structure, remove PMOS dummy poly 7 by dry etching.
As shown in Fig. 1 c, remove photoresist 9, deposition one deck PMOS metal work function layer 10 on whole CMOS, and on PMOS metal work function layer 10 depositing metal layers, as metallic aluminium (Al), then carry out cmp, remove PMOS metal work function layer 10 and unnecessary metal on interlayer insulative layer 3, exposing interlayer insulative layer 3, thereby form PMOS metal gates 11.
As shown in Fig. 1 d, with aforementioned same operation, form the photoresist that covers the PMOS grid structure, remove NMOS dummy poly 6 by dry etching; Remove afterwards the photoresist that covers PMOS, deposition NMOS metal work function layer 12 and metal level, then carry out cmp, remove NMOS metal work function layer 12 and metal level on interlayer insulative layer 3, thereby form NMOS metal gates 13.
In said process, also comprise other existing CMOS manufacturing steps, such as: after forming sidewall oxide 4, before forming interlayer insulative layer 3, also be included in the step of formation source-drain area in nmos area and PMOS district; And the stress technique of introducing for strengthening the PMOS performance, such as, after forming sidewall oxide 4, form source-drain area in the PMOS district before, the step of embedment stress film in the PMOS district, in prior art, this step often adopts the SiGe material to embed as stress film.
Said process all can adopt existing semiconductor fabrication process to realize, ins and outs repeat no more herein more specifically.
As shown in Figure 4, after forming PMOS metal gates 11 and NMOS metal gates 13, deposition one silicon nitride (SiN) layer 14 on whole CMOS, this silicon nitride layer 14 can adopt the existing method such as CVD to deposit, and thickness is 50～500
Its Main Function is the evaporation and diffusion that prevents the metal material of grid in follow-up process annealing process, and then the pollution of the chamber of avoiding annealing, and prevents device damage.
As shown in Figure 5, carry out process annealing processing 15 to forming silicon nitride layer 14 CMOS afterwards.This process annealing is processed and is adopted ultraviolet ray (UV) irradiation in 15 processes, mixes D in the annealing chamber
2, H
2Perhaps both mists; Perhaps this process annealing is processed in 15 processes and is adopted microwave (microwave) radiation, and annealing atmosphere adopts D
2, H
2Perhaps both mist, protective gas adopts N
2, Ar, NH
3The perhaps mist of at least two kinds of gases wherein, D
2Flow 0.1～5slm, H
2Flow 1～50slm, NH
3Flow 1～50slm, N
2Flow 1～100slm, Ar flow 1～100slm, ultraviolet ray or microwave power adopt 100～500W, and the chamber pressure of annealing is normal pressure, and the process annealing temperature is 200～500 ℃, and the process annealing time is 10～120min.This process annealing is processed 15 processes, can avoid that in annealing process, the metal material of metal gates diffuses in the annealing chamber, and pollutes chamber.
Adopt process annealing to process 15 processes in high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method of the present invention.In this process, in high-temperature annealing process the present invention due to annealing temperature, thereby in annealing process, the metal material of metal gates is difficult for diffusing in the annealing chamber and causes pollution to chamber.And deposited silicon nitride layer 14 is also in order to prevent the diffusion of metal gates in annealing process, so from this angle, the deposition step of silicon nitride layer 14 is optional steps, but after increasing this step, its effect that prevents the metal diffusion is inevitable better.
Fig. 6 a and Fig. 6 b are respectively NMOS and PMOS does not adopt above-mentioned process annealing process and the threshold voltage variation figure that adopts above-mentioned process annealing process, wherein ordinate be cumulative curve (cumulation curve) representative be percentage, abscissa is threshold voltage (unit: volt).In Fig. 6 a, do not adopt stress relief annealed NMOS threshold voltage curve 21 to be in the right side of adopting stress relief annealed NMOS threshold voltage curve 22, can find out from Fig. 6 a, after adopting above-mentioned process annealing, the Vt of NMOS (threshold voltage) value is significantly less than the Vt value of the NMOS that does not adopt the process annealing process.In Fig. 6 b, do not adopt stress relief annealed PMOS threshold voltage curve 31 to be in the right side of adopting stress relief annealed PMOS threshold voltage curve 32, can find out from Fig. 6 b, after adopting above-mentioned process annealing, the Vt of PMOS (threshold voltage) value is significantly less than the Vt value of the PMOS that does not adopt the process annealing process.
What further illustrate is, in Fig. 6 a and Fig. 6 b, adopting stress relief annealed NMOS threshold voltage curve 22 and adopting in the zone of stress relief annealed PMOS threshold voltage curve 32 all has many curves, and wherein each curve is to adopt respectively the resulting different threshold voltages curve of different parameters result in the process annealing process.Its concrete technology parameter is: gas and flow-rate ratio are selected respectively N
2: H
2=15: 5slm, N
2: H
2=17: 1.7slm, the annealing chamber pressure is normal pressure, and annealing temperature is selected respectively 400 ℃, 410 ℃, and annealing time is selected respectively 30min, 60min.It should be noted that shown in this technological parameter and Fig. 6 a and Fig. 6 b, content is all illustrating beneficial effect of the present invention; be not limited to protection scope of the present invention; for reaching more excellent device performance, all should be included in protection scope of the present invention to the adjustment of technological parameter in the spirit and principles in the present invention within.
After the above results had shown employing above-mentioned process annealing process of the present invention, the threshold voltage of CMOS had all produced reduction in various degree.This shows, the process annealing process that adopts in high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method of the present invention has reduced the threshold voltage of CMOS, thereby further improved the performance of semiconductor device, and as previously mentioned, adopt low temperature annealing process in high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method of the present invention, annealing chamber, cause damage of equipment are polluted in the gate metal generation evaporation of having avoided causing because annealing temperature is too high.
The above is only preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (12)
1. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method comprises:
The semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is provided, and described semiconductor device comprises substrate, is formed with high dielectric layer and metal gates on described substrate, is provided with sidewall oxide in the both sides of high dielectric layer and metal gates;
Described semiconductor device is carried out process annealing.
2. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 1, is characterized in that, the described semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is made by the following method:
Substrate is provided, forms successively high dielectric layer and dummy poly on described substrate, and form sidewall oxide in the both sides of high dielectric layer and dummy poly;
Remove dummy poly and form groove, plated metal grid in described groove is to form the semiconductor device of metal gate structure.
3. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 2, is characterized in that, described metal gates comprises metal work function layer and the metal level that is deposited on successively in described groove.
4. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 1, it is characterized in that, after the semiconductor device that is formed with the high-dielectric constant metal grid electrode structure is provided, described semiconductor device is carried out also comprising before process annealing: at described semiconductor device surface deposition one silicon nitride layer.
5. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 4, is characterized in that, described silicon nitride layer thickness is 50～500
6. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 1, is characterized in that, adopts ultraviolet ray irradiation or microwave in described process annealing process, adopts D in annealing atmosphere
2, H
2Perhaps both mist, protective gas adopts N
2, Ar, NH
3The perhaps mist of at least two kinds of gases wherein, wherein, D
2Flow 0.1～5slm, H
2Flow 1～50slm, NH
3Flow 1～50slm, N
2Flow 1～100slm, Ar flow 1～100slm, the process annealing temperature is 200～500 ℃, the process annealing time is 10～120min.
7. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 6, is characterized in that, described annealing gas to chamber also comprises N
2, Ar and/or NH
3
8. the described high-dielectric constant metal grid utmost point of according to claim 1 to 7 any one method, semi-conductor device manufacturing method, is characterized in that, described semiconductor device is CMOS.
9. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 8, is characterized in that, described CMOS makes by the following method:
Definition nmos area and PMOS district on substrate, and between nmos area and PMOS district the formation shallow trench isolation from; Form respectively the high dielectric layer of NMOS and the high dielectric layer of PMOS in nmos area and PMOS district, and NMOS dummy poly and PMOS dummy poly, and in the both sides of the high dielectric layer of NMOS, NMOS dummy poly and the both sides of the high dielectric layer of PMOS, PMOS dummy poly form sidewall oxide;
Form interlayer insulative layer on substrate, and carry out cmp to expose dummy poly;
Form the photoresist that covers the NMOS grid structure, remove the PMOS dummy poly by dry etching;
Remove photoresist, deposition one deck PMOS metal work function layer on whole CMOS, and on PMOS metal work function layer depositing metal layers, carry out cmp to expose interlayer insulative layer, form the PMOS metal gates;
Form the photoresist that covers the PMOS grid structure, remove the NMOS dummy poly by dry etching;
Remove photoresist, deposition NMOS metal work function layer and metal level carry out cmp, remove NMOS metal work function layer and metal level on interlayer insulative layer, have formed the NMOS metal gates.
10. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 9, is characterized in that, after forming sidewall oxide, before forming interlayer insulative layer, also is included in the step of formation source-drain area in nmos area and PMOS district.
11. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 10 is characterized in that, after forming sidewall oxide, in PMOS district before the formation source-drain area, also is included in the step of embedment stress film in the PMOS district.
12. high-dielectric constant metal grid utmost point method, semi-conductor device manufacturing method according to claim 10 is characterized in that described stress film material is SiGe.
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