CN103579077B - A kind of semiconductor structure and forming method thereof - Google Patents

A kind of semiconductor structure and forming method thereof Download PDF

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Publication number
CN103579077B
CN103579077B CN201210265059.4A CN201210265059A CN103579077B CN 103579077 B CN103579077 B CN 103579077B CN 201210265059 A CN201210265059 A CN 201210265059A CN 103579077 B CN103579077 B CN 103579077B
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trench isolation
shallow trench
semiconductor structure
substrate
formation method
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CN103579077A (en
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张彬
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

The invention discloses a kind of semiconductor structure and forming method thereof, adopt UV-irradiation process shallow trench isolation, free oxygen concentration in it is reduced greatly, form a barrier layer afterwards, prevent the diffusion of free oxygen further, make high-K dielectric layer can not be subject to the erosion of free oxygen, avoid the leakage current that generation is larger, effectively can control the skew (shift) of threshold voltage vt simultaneously, thus improve the performance of device.

Description

A kind of semiconductor structure and forming method thereof
Technical field
The present invention relates to IC manufacturing field, particularly a kind of semiconductor structure that high-K dielectric layer can be avoided to damage and forming method thereof.
Background technology
Along with constantly reducing of transistor size, HKMG(high-K dielectric layer+metal gates) technology almost become the indispensable technology of below 45nm rank processing procedure.High-K dielectric layer, because of its larger dielectric constant, can realize when having same equivalent oxide thickness (EOT:equivalentoxidethickness) with silicon dioxide, and its actual Thickness Ratio silicon dioxide is much bigger, thus is deeply welcome in the industry.
But hafnium is ionic metal oxide mostly, this stock characteristic causes hafnium as causing a lot of unreliable problem during dielectric layer.
In actual production process, due to the cause of etching technics etc., there will be the free oxygens such as more Si-OH in shallow trench isolation, these materials can produce harmful effect to high-K dielectric layer, for the hafnium with transition metal, n the valence electron of () d state and (n=1) s state is just easy on the unoccupied orbital of 3s or 3p transferring to oxygen, form the metal-oxygen bonding of the corpuscular property of high ligancy, the comparatively macroion of this metal-oxygen bonding can make conduction band reduce, then will cause larger leakage current and higher trap density, cause threshold voltage vt variation etc.
Summary of the invention
The object of the present invention is to provide a kind of semiconductor structure and forming method thereof, be adversely affected to solve high-K dielectric layer in prior art and affect the situation of device performance.
For solving the problems of the technologies described above, the invention provides a kind of formation method of semiconductor structure, comprising:
There is provided substrate, in described substrate, form shallow trench isolation, described shallow trench isolation exceeds described substrate;
Treatment with ultraviolet light is carried out to described shallow trench isolation;
Form barrier layer, described barrier layer is positioned at shallow trench isolation both sides.
Optionally, for the formation method of described semiconductor structure, the atmosphere of described treatment with ultraviolet light is: in helium atmosphere, when 200 ~ 800 DEG C, irradiates 1 ~ 30min.
Optionally, for the formation method of described semiconductor structure, described helium gas flow is 100 ~ 10000sccm.
Optionally, for the formation method of described semiconductor structure, the process conditions on described formation barrier layer are: nitrogen flow is 10 ~ 1000sccm, and reaction temperature is 200 ~ 650 DEG C, and power is 10 ~ 500W.
Optionally, for the formation method of described semiconductor structure, described substrate is formed with active area oxide layer and active area mask layer.
Optionally, for the formation method of described semiconductor structure, in described substrate, form shallow trench isolation, comprise the steps:
Adopt lithographic etch process to run through described active area oxide layer and active area mask layer, and etched substrate is to form groove;
Form liner at described groove inner wall, afterwards, continue to form shallow trench isolation.
Optionally, for the formation method of described semiconductor structure, before treatment with ultraviolet light is carried out to described shallow trench isolation, comprise the steps:
Remove described active area oxide layer and active area mask layer.
Optionally, for the formation method of described semiconductor structure, after forming barrier layer, also comprise following processing step:
Form grid oxic horizon over the substrate;
Described grid oxic horizon forms high-K dielectric layer, and described high-K dielectric layer is positioned at both sides, described barrier layer.
The semiconductor structure that a kind of formation method that the invention provides semiconductor structure as above is formed, comprising:
Substrate, is formed with shallow trench isolation in described substrate, and described shallow trench isolation is through treatment with ultraviolet light;
Be formed at the barrier layer of described shallow trench isolation both sides.
Optionally, for described semiconductor structure, described shallow trench isolation exceeds described substrate.
Optionally, for described semiconductor structure, also comprise: the high-K dielectric layer being positioned at the grid oxic horizon on described substrate and being positioned on described grid oxic horizon.
Optionally, for described semiconductor structure, described grid oxic horizon and high-K dielectric layer are all positioned at both sides, described barrier layer.
Compared with prior art, in semiconductor structure provided by the invention and forming method thereof, adopt UV-irradiation process shallow trench isolation, free oxygen concentration in it is reduced greatly, forms a barrier layer afterwards, prevent the diffusion of free oxygen further, make high-K dielectric layer can not be subject to the erosion of free oxygen, avoid the leakage current that generation is larger, effectively can control the skew (shift) of threshold voltage vt simultaneously, thus improve the performance of device.
Accompanying drawing explanation
Fig. 1 ~ Fig. 4 is the process schematic that the embodiment of the present invention forms semiconductor structure.
Embodiment
Be described in further detail below in conjunction with the formation method of the drawings and specific embodiments to semiconductor structure provided by the invention.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that, accompanying drawing all adopts the form simplified very much, only in order to object that is convenient, the aid illustration embodiment of the present invention lucidly.
A forming process for semiconductor structure, comprising: please refer to Fig. 1, provides substrate 1; Shallow trench isolation 4 is formed in described substrate 1.Concrete, adopt following processing step: deposit source region oxide layer 2 and active area mask layer 3 on substrate 1, described active area oxide layer 2 is generally silicon dioxide, active area mask layer 3 can be silicon nitride etc., then lithographic etch process is adopted to etch the groove having and be generally 86 ° of inclination angles, liner (liner is formed at described groove inner wall, not shown), afterwards, continue to form shallow trench isolation 4, preferably, after deposition shallow trench isolation 4, annealing in process is carried out to it, reach objects such as eliminating stress, and planarization is carried out to it, as adopted chemical mechanical milling tech.
Please refer to Fig. 2, remove described active area oxide layer and active area mask layer, preferably, adopt wet-etching technology to remove.But, the part that can be positioned on substrate 1 shallow trench isolation 4 in etching process produces and corrodes, can cause producing more free oxygen 5 in shallow trench isolation 4 simultaneously, as such as hydroxyl (-OH), the generation of this kind of material has larger damage to high-K dielectric layer, high-K dielectric layer can be made to be damaged, thus to have influence on the electrical property of device.
In order to solve the problem, please continue to refer to Fig. 2, adopt shallow trench isolation 4 described in UV-irradiation, concrete, the atmosphere of employing treatment with ultraviolet light is: select helium (He) atmosphere, when 200 ~ 800 DEG C, irradiate 1 ~ 30min, preferably, described helium gas flow is 100 ~ 10000sccm.
Treatment with ultraviolet light is adopted to remove free oxygen, especially the meeting that the free oxygen that shallow trench isolation 4 is positioned at the lateral side regions of described substrate 1 upper part is removed is better, adopt helium atmosphere also further can remove stress, thus the impact that the mobility of raceway groove carriers is subject to diminish simultaneously.
But said method can not ensure that free oxygen is removed completely, the both sides that so free oxygen is then likely positioned at substrate upper part from shallow trench isolation continue to spread out, and then have influence on high-K dielectric layer.
Please refer to Fig. 3, continue the formation barrier layer, both sides 6 being positioned at substrate 1 upper part in shallow trench isolation 4.Described barrier layer 6 can be nitration case, described barrier layer 6 adopts following process conditions to be formed: in chemical vapor deposition chamber, pass into the nitrogen that flow is 10 ~ 1000sccm, preferably, using plasma, reaction temperature controls at 200 ~ 650 DEG C, power is 10 ~ 500W, and adopts dry etching to form the barrier layer 6 abutting against shallow trench isolation 4 both sides.
After barrier layer is formed, ion implantation can be carried out in the substrate, form the N trap and the P trap that are positioned at shallow trench isolation both sides, and continue to carry out heavy doping in N trap and P trap, form source-drain electrode.Existing process can be adopted to be formed, therefore the present invention does not illustrate.
Then, please refer to Fig. 4, deposition of gate oxide layer 7 on described substrate 1, it can be silicon dioxide, and described grid oxic horizon 7 is near barrier layer 6.Afterwards, continue to deposit high K dielectric material layer on grid oxic horizon 7, adopt chemical mechanical milling tech to carry out planarization to high K dielectric material layer after deposit, form the high-K dielectric layer 8 near barrier layer 6.
As seen from Figure 4, barrier layer 6 encloses the both sides that shallow trench isolation 4 is positioned at substrate 1 upper part, shallow trench isolation 4 is not contacted with high-K dielectric layer, and barrier layer 6 itself can completely cut off the infiltration of free oxygen, this just can ensure high-K dielectric layer in side, barrier layer 6 can not corrode by free oxygen, also just ensure that the electrical property of device.
Afterwards, can proceed, as formed the related process such as metal gates, to complete the manufacture of transistor.
In semiconductor structure that above-described embodiment provides and forming method thereof, adopt UV-irradiation process shallow trench isolation, free oxygen concentration in it is reduced greatly, form a barrier layer afterwards, prevent the diffusion of free oxygen further, make high-K dielectric layer can not be subject to the erosion of free oxygen, avoid the leakage current that generation is larger, effectively can control the skew (shift) of threshold voltage vt simultaneously, thus improve the performance of device.
Obviously, those skilled in the art can carry out various change and modification to invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.

Claims (12)

1. a formation method for semiconductor structure, is characterized in that, comprising:
There is provided substrate, in described substrate, form shallow trench isolation, described shallow trench isolation exceeds described substrate, has free oxygen in described shallow trench isolation;
Treatment with ultraviolet light is carried out to described shallow trench isolation;
Form barrier layer, described barrier layer is positioned at shallow trench isolation both sides, and
Form high-K dielectric layer, described high-K dielectric layer is positioned at both sides, described barrier layer; Wherein treatment with ultraviolet light is for removing free oxygen, avoids producing described high-K dielectric layer damaging, and forms the infiltration that barrier layer is isolated free oxygen, avoids further producing described high-K dielectric layer damaging.
2. the formation method of semiconductor structure as claimed in claim 1, it is characterized in that, the atmosphere of described treatment with ultraviolet light is: in helium atmosphere, when 200 ~ 800 DEG C, irradiates 1 ~ 30min.
3. the formation method of semiconductor structure as claimed in claim 2, it is characterized in that, described helium gas flow is 100 ~ 10000sccm.
4. the formation method of semiconductor structure as claimed in claim 3, it is characterized in that, the process conditions on described formation barrier layer are: nitrogen flow is 10 ~ 1000sccm, and reaction temperature is 200 ~ 650 DEG C, and power is 10 ~ 500W.
5. the formation method of semiconductor structure as claimed in claim 1, is characterized in that, described substrate is formed with active area oxide layer and active area mask layer.
6. the formation method of semiconductor structure as claimed in claim 5, is characterized in that, form shallow trench isolation, comprise the steps: in described substrate
Adopt lithographic etch process to run through described active area oxide layer and active area mask layer, and etched substrate is to form groove;
Form liner at described groove inner wall, afterwards, continue to form shallow trench isolation.
7. the formation method of semiconductor structure as claimed in claim 6, is characterized in that, before carrying out treatment with ultraviolet light, comprise the steps: described shallow trench isolation
Remove described active area oxide layer and active area mask layer.
8. the formation method of semiconductor structure as claimed in claim 7, is characterized in that, after forming barrier layer, before forming high-K dielectric layer, also comprises following processing step:
Form grid oxic horizon over the substrate, described high-K dielectric layer is formed on described grid oxic horizon.
9. the formation method of the semiconductor structure as described in any one in claim 1 ~ 8 the semiconductor structure that formed, it is characterized in that, comprising:
Substrate, is formed with shallow trench isolation in described substrate, and described shallow trench isolation is through treatment with ultraviolet light;
Be formed at the barrier layer of described shallow trench isolation both sides.
10. semiconductor structure as claimed in claim 9, it is characterized in that, described shallow trench isolation exceeds described substrate.
11. semiconductor structures as claimed in claim 10, is characterized in that, also comprise: the high-K dielectric layer being positioned at the grid oxic horizon on described substrate and being positioned on described grid oxic horizon.
12. semiconductor structures as claimed in claim 11, it is characterized in that, described grid oxic horizon and high-K dielectric layer are all positioned at both sides, described barrier layer.
CN201210265059.4A 2012-07-27 2012-07-27 A kind of semiconductor structure and forming method thereof Active CN103579077B (en)

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CN106783574A (en) * 2017-02-14 2017-05-31 上海华虹宏力半导体制造有限公司 A kind of method for solving the problems, such as stripping metal processing procedure threshold voltage shift

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130467A (en) * 1997-12-18 2000-10-10 Advanced Micro Devices, Inc. Shallow trench isolation with spacers for improved gate oxide quality
US7622162B1 (en) * 2007-06-07 2009-11-24 Novellus Systems, Inc. UV treatment of STI films for increasing tensile stress
CN102569162A (en) * 2010-12-22 2012-07-11 中芯国际集成电路制造(上海)有限公司 Forming method of shallow groove isolating structure

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JP2002124563A (en) * 2001-09-03 2002-04-26 Toshiba Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6130467A (en) * 1997-12-18 2000-10-10 Advanced Micro Devices, Inc. Shallow trench isolation with spacers for improved gate oxide quality
US7622162B1 (en) * 2007-06-07 2009-11-24 Novellus Systems, Inc. UV treatment of STI films for increasing tensile stress
CN102569162A (en) * 2010-12-22 2012-07-11 中芯国际集成电路制造(上海)有限公司 Forming method of shallow groove isolating structure

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