CN106952810B - Method for manufacturing semiconductor structure - Google Patents

Method for manufacturing semiconductor structure Download PDF

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CN106952810B
CN106952810B CN201610006560.7A CN201610006560A CN106952810B CN 106952810 B CN106952810 B CN 106952810B CN 201610006560 A CN201610006560 A CN 201610006560A CN 106952810 B CN106952810 B CN 106952810B
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CN106952810A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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Abstract

A method of fabricating a semiconductor structure, comprising: forming a semiconductor base, wherein the semiconductor base comprises a substrate and a fin part protruding out of the substrate; performing threshold voltage adjustment doping process on the fin part; forming ion barrier layers on the top and the side wall surfaces of the fin part; annealing the fin part with the ion blocking layer; and forming a gate structure which crosses the fin part and covers part of the top surface and the side wall surface of the fin part. After the threshold voltage adjusting doping process is carried out, ion blocking layers are formed on the top and the side wall surfaces of the fin portion, then the fin portion is subjected to an annealing process, the surface smoothness of the fin portion is improved through the annealing process so as to improve the mobility of current carriers in a channel, meanwhile, the ion blocking layers can protect the fin portion, the annealing process is prevented from enabling threshold voltage adjusting doping ions injected into the fin portion through the doping process to be lost, and therefore the electrical performance of the semiconductor device is optimized.

Description

Method for manufacturing semiconductor structure
Technical Field
The invention relates to the field of semiconductors, in particular to a manufacturing method of a semiconductor structure.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFET devices has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, the electrical performance of the semiconductor device formed by the prior art is poor.
Disclosure of Invention
The invention solves the problem of providing a manufacturing method of a semiconductor structure, which optimizes the electrical performance of a semiconductor device.
To solve the above problems, the present invention provides a method for fabricating a semiconductor structure. The method comprises the following steps: forming a semiconductor base, wherein the semiconductor base comprises a substrate and a fin part protruding out of the substrate; performing a threshold voltage adjustment doping process on the fin portion; forming ion blocking layers on the top and the side wall surface of the fin part after the threshold voltage adjusting doping process; annealing the fin part with the ion blocking layer; and forming a gate structure which crosses the fin part and covers part of the top surface and the side wall surface of the fin part.
Optionally, the step of performing the threshold voltage adjustment doping process on the fin portion includes: the ion implanted into the fin part is an N-type ion, the N-type ion is an arsenic ion, the energy of the implanted ion is 5Kev to 12Kev, and the dose of the implanted ion is 1E12 to 5E13 atoms per square centimeter; or, the ions implanted into the fin portion are P-type ions, the P-type ions are boron difluoride ions, the energy of the implanted ions is 3Kev to 10Kev, and the dose of the implanted ions is 5E12 to 5E14 atoms per square centimeter.
Optionally, the ion blocking layer is a nitrogen-doped layer.
Optionally, the material of the ion blocking layer is silicon nitride.
Optionally, the process for forming the ion blocking layer is a plasma nitridation process.
Optionally, the process parameters of the plasma nitridation process include: the power is 600 watts to 1000 watts, the pressure is 10 mtorr to 30 mtorr, the process time is 10 seconds to 30 seconds, the reaction gas is nitrogen, the auxiliary gas is helium, the gas flow rate of the nitrogen is 50 standard milliliters per minute to 120 standard milliliters per minute, and the gas flow rate of the helium is 80 standard milliliters per minute to 150 standard milliliters per minute.
Optionally, the thickness of the ion barrier layer is
Figure BDA0000901602030000021
To
Figure BDA0000901602030000022
Optionally, the fin portion is annealed using a hydrogen-containing gas.
Optionally, the process parameters of the annealing process include: the annealing temperature is 950 ℃ to 1100 ℃, the process time is 10 seconds to 200 seconds, the pressure is 0.4 torr to 1 torr, the reaction gas is hydrogen or deuterium, and the gas flow of the reaction gas is 0.5 standard liter per minute to 2 standard liters per minute.
Optionally, after the annealing process is performed on the fin portion and before the gate structure is formed, the manufacturing method further includes: and carrying out surface treatment on the fin part to remove hydrogen-containing byproducts on the surface of the fin part.
Optionally, the step of performing surface treatment on the fin portion includes: carrying out oxidation treatment on the surface of the fin part to form an oxide layer on the surface of the fin part; and removing the oxide layer.
Optionally, the process of performing oxidation treatment on the fin portion is a wet oxidation process.
Optionally, the fin portion is subjected to a wet oxidation process with an aqueous ozone solution, and the process time is 60S to 150S.
Optionally, the material of the oxide layer is silicon oxide.
Optionally, the process of removing the oxide layer is a wet etching process.
Optionally, the solution used in the wet etching process is hydrofluoric acid.
Optionally, the gate structure is a dummy gate structure, and the step of forming the gate structure includes: forming a pseudo gate oxide layer which spans the fin part and covers partial top surface and side wall surface of the fin part; and forming a dummy gate electrode layer on the surface of the dummy gate oxide layer.
Optionally, the process for forming the pseudo gate oxide layer is an in-situ steam generation oxidation process.
Optionally, the process parameters of the in-situ steam generation oxidation process include: providing O2And H2，O2The flow rate is 1sccm to 30sccm, H2The flow rate is 1.5sccm to 15sccm, and the chamber temperature is 700 ℃ to 1200 ℃.
Optionally, in the step of forming the dummy gate oxide layer, an oxidation process is performed on the ion blocking layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
after the fin part is subjected to the threshold voltage adjusting doping process, ion blocking layers are formed on the top and the side wall surfaces of the fin part, then the fin part is subjected to an annealing process, the surface smoothness of the fin part is improved through the annealing process so as to improve the mobility of current carriers in a channel, meanwhile, the ion blocking layers can protect the fin part, the annealing process is prevented from enabling threshold voltage adjusting doping ions injected into the fin part through the doping process to be lost, and therefore the electrical performance of a semiconductor device is optimized.
In an alternative scheme, an annealing process is performed on the fin portion by using a hydrogen-containing gas, and after the annealing process, hydrogen-containing byproducts are easily formed on the surface of the fin portion, so that the electrical performance and the reliability performance of the semiconductor device are easily affected. Before the grid electrode structure is formed, the surface of the fin part is treated to remove the hydrogen-containing by-products on the surface of the fin part, so that the electrical property and the reliability of the semiconductor device are improved.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in an embodiment of a method for manufacturing a semiconductor structure according to the present invention.
Detailed Description
The electrical performance of the semiconductor device of the prior art is poor, and the reason for analyzing is that: in order to improve the surface smoothness of the fin to improve the mobility of carriers in the channel, an annealing process is performed on the fin after a threshold voltage adjustment doping process is performed on the fin. However, under the effect of the annealing process, the threshold voltage adjusting dopant ions injected into the fin portion through the doping process are prone to loss, especially ions with lighter atomic mass, and therefore electrical performance of the semiconductor device is prone to being reduced.
In order to solve the technical problem, the present invention provides a method for manufacturing a semiconductor structure, comprising: forming a semiconductor base, wherein the semiconductor base comprises a substrate and a fin part protruding out of the substrate; performing a threshold voltage adjustment doping process on the fin portion; forming ion blocking layers on the top and the side wall surface of the fin part after the threshold voltage adjusting doping process; annealing the fin part with the ion blocking layer; and forming a gate structure which crosses the fin part and covers part of the top surface and the side wall surface of the fin part.
After the fin part is subjected to the threshold voltage adjusting doping process, ion blocking layers are formed on the top and the side wall surfaces of the fin part, then the fin part is subjected to an annealing process, the surface smoothness of the fin part is improved through the annealing process so as to improve the mobility of current carriers in a channel, meanwhile, the ion blocking layers can protect the fin part, the annealing process is prevented from enabling threshold voltage adjusting doping ions injected into the fin part through the doping process to be lost, and therefore the electrical performance of a semiconductor device is optimized.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 6 are schematic structural diagrams corresponding to steps in an embodiment of a method for manufacturing a semiconductor structure according to the present invention.
Referring to fig. 1, a semiconductor base is formed, and the semiconductor base includes a substrate 100 and a fin 110 protruding from the substrate 100.
In this embodiment, the semiconductor substrate is used to form an N-type device or a P-type device.
The substrate 100 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 100 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the material of the fin 110 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 100 is a silicon substrate, and the fin 110 is made of silicon.
Specifically, the step of forming the semiconductor substrate includes: providing an initial substrate, and forming a patterned hard mask layer 200 on the substrate; etching the initial substrate by taking the hard mask layer 200 as a mask to form a plurality of discrete protrusions; the etched initial base serves as a substrate 100, and the protrusions are fins 110.
In this embodiment, the top dimension of the fin 110 is smaller than the bottom dimension. In other embodiments, the sidewalls of the fins 110 can also be perpendicular to the surface of the substrate 100, i.e., the top dimension of the fins 110 is equal to the bottom dimension.
In this embodiment, the hard mask layer 200 is made of silicon nitride, and when a planarization process is performed subsequently, the surface of the hard mask layer 200 can serve as a stop position for the planarization process, and the hard mask layer 200 can also play a role in protecting the top of the fin 110.
With reference to fig. 2, after the semiconductor substrate is formed, the method further includes: forming a pad oxide layer 101 on a portion of the surface of the fin 110; an isolation layer 102 is formed on the surface of the substrate 100.
The liner oxide layer 101 is used to repair the fin 110.
In the process of etching the initial substrate to form the fin 110, a convex corner is easily formed on the surface of the fin 110 or the surface has defects due to an etching process, which easily affects the device performance of the finfet.
Therefore, in the present embodiment, the fin portion 110 is oxidized to form the liner oxide layer 101 on the surface of the fin portion 110. In the oxidation treatment process, because the convex edge part of fin portion 110 is bigger than the surface, and is easier to be oxidized, follow-up getting rid of after liner oxide layer 101, not only the defect layer on fin portion 110 surface is got rid of, and the convex edge part is also got rid of, makes fin portion 110's surface is smooth, and the crystal lattice quality improves, avoids fin portion 110's apex angle point discharge problem is favorable to improving fin field effect transistor's performance.
It should be noted that the oxidation process also oxidizes the surface of the substrate 100, and therefore, the pad oxide layer 101 is also located on the surface of the substrate 100. In this embodiment, the fin 110 and the substrate 100 are made of silicon, and correspondingly, the pad oxide layer 101 is made of silicon oxide.
The isolation layer 102 serves as an isolation structure of the semiconductor structure, and is used for isolating adjacent devices. In this embodiment, the isolation layer 102 is a shallow trench isolation layer, but is not limited to a shallow trench isolation layer.
Specifically, the step of forming the isolation layer 102 includes: forming an isolation film on the surface of the pad oxide layer 101, wherein the top of the isolation film is higher than the top of the hard mask layer 200 (shown in fig. 1); grinding to remove the isolation film higher than the top of the hard mask layer 200; removing a partial thickness of the isolation film to form isolation layer 102; the hard mask layer 200 is removed.
It should be noted that, in the process of removing a portion of the thickness of the isolation film, a portion of the liner oxide layer 101 on the surface of the fin 110 is also removed.
Referring to fig. 3, a threshold voltage adjustment doping process is performed on the fin 110.
The threshold voltage adjusting doping process is used for adjusting the threshold voltage of the semiconductor device.
In this embodiment, the semiconductor substrate is used to form an N-type device or a P-type device. The number of the fins 110 is multiple, and accordingly, the fins 110 include N-type fins for forming N-type devices and P-type fins for forming P-type devices; in the step of performing the threshold voltage adjusting doping process on the fin portion 110, an N-type threshold voltage adjusting doping process and a P-type threshold voltage adjusting doping process are performed on the N-type fin portion and the P-type fin portion, respectively.
Specifically, the semiconductor substrate is used to form an N-type device, and the step of performing the threshold voltage adjustment doping process on the fin 110 includes: the fin 110 is implanted with N-type ions, the N-type ions are arsenic ions, the energy of the implanted ions is 5Kev to 12Kev, and the dose of the implanted ions is 1E12 to 5E13 atoms per square centimeter.
Alternatively, the semiconductor substrate is used to form a P-type device, and the step of performing the threshold voltage adjustment doping process on the fin 110 includes: the ions implanted into the fin 110 are P-type ions, the P-type ions are boron difluoride ions, the energy of the implanted ions is 3Kev to 10Kev, and the dose of the implanted ions is 5E12 to 5E14 atoms per square centimeter.
It should be noted that, before the threshold voltage adjustment doping process is performed on the fin 110, the method further includes: a shielding layer 103 is formed on the top surface and the sidewall surface of the fin 110.
The shielding layer 103 serves as an injection buffer layer for reducing lattice damage to the fin 110 caused by the threshold voltage adjusting doping process.
The material of the shielding layer 103 may be silicon oxide or silicon oxynitride. In this embodiment, the material of the shielding layer 103 is silicon oxide. The shielding layer 103 is formed on the top and sidewall surfaces of the fin 110, and the shielding layer 103 is further formed on the surface of the isolation layer 101.
It should be further noted that, after the threshold voltage adjustment doping process is completed, the shielding layer 103 is removed.
The process for removing the shielding layer 103 may be a dry etching process or a wet etching process. In this embodiment, the shielding layer 103 is removed by a dry etching process, which is a SiCoNi etching process.
It should be noted that the removal rate of the mask layer 103 by the SiCoNi etching process is greater than that of the isolation layer 102, so that the loss of the isolation layer 102 can be reduced while the mask layer 103 is removed; and the SiCoNi etching process is beneficial to improving the load effect of the etching process on the pattern dense region and the pattern sparse region, thereby improving the uniformity of the height of the fin portion 110.
Referring to fig. 4, after the threshold voltage adjustment doping process, an ion blocking layer 104 is formed on the top and sidewall surfaces of the fin 110.
The ion blocking layer 104 is used to prevent loss of threshold voltage adjusting dopant ions implanted into the fin 110 by a doping process during subsequent processes.
In this embodiment, the ion blocking layer 104 is a nitrogen-doped layer. Specifically, the material of the ion blocking layer 104 is silicon nitride, and the process of forming the ion blocking layer 104 is a plasma nitridation process.
It should be noted that the density of the nitrogen-doped layer is high, and the nitrogen ions in the nitrogen-doped layer are also located in the interstitial sites in the crystal lattice, so that the loss of the threshold voltage adjusting dopant ions injected into the fin portion through the doping process from the interstitial sites in the crystal lattice can be prevented.
Specifically, the process parameters of the plasma nitridation process include: the power is 600 watts to 1000 watts, the pressure is 10 mtorr to 30 mtorr, the process time is 10 seconds to 30 seconds, the reaction gas is nitrogen, the auxiliary gas is helium, the gas flow rate of the nitrogen is 50 standard milliliters per minute to 120 standard milliliters per minute, and the gas flow rate of the helium is 80 standard milliliters per minute to 150 standard milliliters per minute.
It should be noted that the thickness of the ion blocking layer 104 is not too thick nor too thin. If the thickness of the ion blocking layer 104 is too thick, nitrogen ions on the surface of the channel are too much, and thus the reliability of the semiconductor device is easily affected; if the thickness of the ion blocking layer 104 is too thin, the effect of preventing the loss of the dopant ions is poor. For this reason, in the present embodiment, the thickness of the ion blocking layer 104 is
Figure BDA0000901602030000081
To
Figure BDA0000901602030000082
Referring to fig. 5, an annealing process 300 is performed on the fin 110 with the ion blocking layer 104 formed thereon.
The anneal process 300 is used to improve the surface smoothness of the fin 110, thereby improving the mobility of carriers in the channel.
During the annealing process 300, silicon atoms in the fin 110 migrate, and the silicon atoms fill the defect layer on the surface of the fin 110, thereby improving the smoothness of the top, top angle, and sidewall surface of the fin 110, and further improving the mobility of carriers in the channel.
In this embodiment, the fin 110 is annealed using a hydrogen-containing gas 300.
Specifically, the process parameters of the annealing process 300 include: the annealing temperature is 950 ℃ to 1100 ℃, the process time is 10 seconds to 200 seconds, the pressure is 0.4 torr to 1 torr, the reaction gas is hydrogen or deuterium, and the gas flow of the reaction gas is 0.5 standard liter per minute to 2 standard liters per minute.
It should be noted that the annealing temperature of the annealing process 300 is not too high, nor too low. If the annealing temperature of the annealing process 300 is too high, the distribution of ions injected in the threshold voltage adjusting doping process is easily affected, and thus the electrical properties of the semiconductor device are easily affected; if the annealing temperature of the annealing process 300 is too low, the improvement effect on the surface smoothness of the fin 110 is not good. Therefore, in this embodiment, the annealing temperature is 950 to 1100 degrees celsius.
It is further noted that, after the annealing process 300 is performed on the fin 110, the method further includes: the fin portion 110 is subjected to a surface treatment to remove hydrogen-containing byproducts from the surface of the fin portion 110.
In this embodiment, the annealing process 300 is performed on the fin portion 110 by using a hydrogen-containing gas, after the annealing process 300, a hydrogen-containing byproduct is easily formed on the surface of the fin portion 110, and the hydrogen remaining on the surface of the fin portion 110 is likely to reduce the reliability of the semiconductor device, so that the fin portion 110 is subjected to a surface treatment after the annealing process is performed on the fin portion 110.
Specifically, the step of performing surface treatment on the fin 110 includes: performing oxidation treatment on the surface of the fin portion 110, and forming an oxide layer (not shown) on the surface of the fin portion 110; and removing the oxide layer.
In this embodiment, the oxidation process performed on the fin portion 110 is a wet oxidation process. Specifically, a wet oxidation process is carried out on the fin portion by adopting an ozone water solution, and the process time of the wet oxidation process is 60-150S.
In this embodiment, the oxide layer is made of silicon oxide. The process for removing the oxide layer is a wet etching process, and the solution adopted by the wet etching process is hydrofluoric acid.
In another embodiment, the fin 110 may be oxidized by a dry oxidation process.
Referring to fig. 6, a gate structure 105 is formed across the fin 110 and covering a portion of the top surface and sidewall surfaces of the fin 110.
In this embodiment, the gate structure 105 is a dummy gate structure, and the gate structure includes: the gate structure comprises a dummy gate oxide layer 106 spanning the fin portion 110 and covering part of the top surface and the side wall surface of the fin portion 110, and a dummy gate electrode layer 107 located on the surface of the dummy gate oxide layer 106.
The gate structure 105 is used to occupy a spatial location for an actual gate structure to be subsequently formed.
Specifically, the step of forming the gate structure 105 includes: forming a pseudo gate oxide film covering the fin portion 110; forming a pseudo gate electrode film on the surface of the pseudo gate oxide film; carrying out planarization treatment on the dummy gate electrode film; patterning the pseudo gate electrode film and the pseudo gate oxide film, forming a pseudo gate oxide layer 106 which stretches across the fin portion 110 and covers the partial top surface and the side wall surface of the fin portion 110, and forming a pseudo gate electrode layer 107 on the surface of the pseudo gate oxide layer 106; the dummy gate oxide layer 106 and the dummy gate electrode layer 107 constitute the gate structure 105.
The material of the dummy gate electrode layer 107 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the dummy gate electrode layer 107 is made of polysilicon.
In this embodiment, the process of forming the dummy gate oxide layer 106 is an in-situ steam generation oxidation process. The process parameters of the in-situ steam generation oxidation process comprise: providing O2And H2，O2The flow rate is 1sccm to 30sccm, H2The flow rate is 1.5sccm to 15sccm, and the chamber temperature is 700 ℃ to 1200 ℃.
It should be noted that in the step of forming the dummy gate oxide layer 106, the oxidation process oxidizes the ion blocking layer 104, so that the ion blocking layer 104 is a part of the material of the dummy gate oxide layer 106.
In this embodiment, the material of the ion blocking layer 104 is silicon nitride, in the step of forming the dummy gate oxide 106, the ion blocking layer 104 is oxidized, the material of the ion blocking layer 104 is changed into silicon oxynitride, and correspondingly, the material of the dummy gate oxide 106 is silicon oxynitride.
After the fin part is subjected to the threshold voltage adjusting doping process, ion blocking layers are formed on the top and the side wall surfaces of the fin part, then the fin part is subjected to an annealing process, the surface smoothness of the fin part is improved through the annealing process so as to improve the mobility of current carriers in a channel, meanwhile, the ion blocking layers can protect the fin part, the annealing process is prevented from enabling threshold voltage adjusting doping ions injected into the fin part through the doping process to be lost, and therefore the electrical performance of a semiconductor device is optimized.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (16)

1. A method of fabricating a semiconductor structure, comprising:
forming a semiconductor base, wherein the semiconductor base comprises a substrate and a fin part protruding out of the substrate;
performing a threshold voltage adjustment doping process on the fin portion;
after the threshold voltage adjusting doping process, forming ion blocking layers on the top and the side wall surfaces of the fin portion, wherein the ion blocking layers are nitrogen-doped layers, nitrogen ions in the nitrogen-doped layers are located in gap positions in crystal lattices, so that loss of threshold voltage adjusting doping ions injected into the fin portion through the doping process from the gap positions in the crystal lattices is prevented, and the process for forming the ion blocking layers is a plasma nitridation process;
annealing the fin part with the ion blocking layer;
forming a gate structure which crosses the fin part and covers part of the top surface and the side wall surface of the fin part, wherein the gate structure is a pseudo gate structure and comprises: the method comprises the steps that a pseudo gate oxide layer which stretches across a fin portion and covers partial top surface and side wall surface of the fin portion and a pseudo gate electrode layer which is located on the surface of the pseudo gate oxide layer are formed, in the step of forming the pseudo gate oxide layer, an oxidation process is carried out on an ion blocking layer, and therefore the ion blocking layer serves as a part of a material of the pseudo gate oxide layer.
2. The method of claim 1, wherein the step of performing a threshold voltage adjustment doping process on the fin comprises:
the ion implanted into the fin part is an N-type ion, the N-type ion is an arsenic ion, the energy of the implanted ion is 5Kev to 12Kev, and the dose of the implanted ion is 1E12 to 5E13 atoms per square centimeter;
or, the ions implanted into the fin portion are P-type ions, the P-type ions are boron difluoride ions, the energy of the implanted ions is 3Kev to 10Kev, and the dose of the implanted ions is 5E12 to 5E14 atoms per square centimeter.
3. The method of claim 1, wherein the ion blocking layer is silicon nitride.
4. The method of claim 1, wherein the process parameters of the plasma nitridation process comprise: the power is 600 watts to 1000 watts, the pressure is 10 mtorr to 30 mtorr, the process time is 10 seconds to 30 seconds, the reaction gas is nitrogen, the auxiliary gas is helium, the gas flow rate of the nitrogen is 50 standard milliliters per minute to 120 standard milliliters per minute, and the gas flow rate of the helium is 80 standard milliliters per minute to 150 standard milliliters per minute.
5. The method of fabricating a semiconductor structure of claim 1, wherein the ion blocking layer has a thickness of
Figure FDA0002469104680000021
To
Figure FDA0002469104680000022
6. The method of claim 1, wherein the fin is annealed using a hydrogen containing gas.
7. The method of claim 6, wherein the process parameters of the annealing process comprise: the annealing temperature is 950 ℃ to 1100 ℃, the process time is 10 seconds to 200 seconds, the pressure is 0.4 torr to 1 torr, the reaction gas is hydrogen or deuterium, and the gas flow of the reaction gas is 0.5 standard liter per minute to 2 standard liters per minute.
8. The method of claim 6, wherein after the annealing the fin and before forming the gate structure, the method further comprises: and carrying out surface treatment on the fin part to remove hydrogen-containing byproducts on the surface of the fin part.
9. The method of claim 8, wherein the step of surface treating the fin comprises: carrying out oxidation treatment on the surface of the fin part to form an oxide layer on the surface of the fin part; and removing the oxide layer.
10. The method of claim 9, wherein the oxidizing the fin is performed by a wet oxidation process.
11. The method of claim 10, wherein the fin portion is wet oxidized with an aqueous ozone solution for a time period of 60S to 150S.
12. The method of claim 9, wherein the oxide layer is formed of silicon oxide.
13. The method of manufacturing a semiconductor structure of claim 9, wherein the process of removing the oxide layer is a wet etching process.
14. The method of claim 13, wherein the wet etching process uses a solution of hydrofluoric acid.
15. The method of fabricating a semiconductor structure of claim 1, wherein the process of forming said dummy gate oxide layer is an in-situ steam-generated oxidation process.
16. The method of fabricating a semiconductor structure of claim 15, wherein the step of forming a gate electrode comprises forming a gate electrode on the substrateThe process parameters of the in-situ steam generation oxidation process comprise: providing O2And H2，O2The flow rate is 1sccm to 30sccm, H2The flow rate is 1.5sccm to 15sccm, and the chamber temperature is 700 ℃ to 1200 ℃.
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