CN107591364B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN107591364B CN107591364B CN201610531703.6A CN201610531703A CN107591364B CN 107591364 B CN107591364 B CN 107591364B CN 201610531703 A CN201610531703 A CN 201610531703A CN 107591364 B CN107591364 B CN 107591364B
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Abstract
The invention provides a semiconductor structure and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate comprising: the device comprises a substrate, and a first fin part and a second fin part which are adjacent to each other and are positioned on the substrate; forming an isolation structure on the substrate, wherein the isolation structure covers the side walls of the first fin portion and the second fin portion, and the surface of the isolation structure is higher than or flush with the top surfaces of the first fin portion and the second fin portion; performing ion implantation on the isolation structure between the first fin part and the second fin part to form an isolation layer; and after forming the isolation layer, etching the isolation structure to enable the isolation structure to expose partial side walls of the fin part, wherein the etching rate of the isolation layer is lower than that of the isolation structure in the process of etching the isolation structure. The etching rate of the isolation layer is less than that of the isolation structure, so that the etching loss of the isolation layer can be reduced, and the performance of the transistor can be improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the increase of the integration level of semiconductor devices, the critical dimensions of transistors are continuously shrinking. However, with the rapid decrease of the transistor size, the thickness of the gate dielectric layer and the operating voltage cannot be changed correspondingly, so that the difficulty of suppressing the short channel effect is increased, and the channel leakage current of the transistor is increased.
The gate of a Fin-Field-Effect Transistor (FinFET) is a fork-shaped 3D structure similar to a Fin. A fin part is formed by the protrusion of the channel of the FinFET out of the surface of the substrate, and the grid electrode covers the top surface and the side wall of the fin part, so that an inversion layer is formed on each side of the channel, and the connection and disconnection of circuits can be controlled on two sides of the fin part. The design can increase the control of the gate to the channel region, thereby well inhibiting the short-channel effect of the transistor. However, the short channel effect still exists in the fin field effect transistor.
In addition, in order to further reduce the influence of the short channel effect on the semiconductor device, the channel leakage current is reduced. The technical field of semiconductors introduces a strained silicon technology, and the method of the strained silicon technology comprises the following steps: forming grooves in the fin parts on two sides of the grid structure; and forming a source drain doped region in the groove by an epitaxial growth process. In order to reduce the exposure of the isolation structure around the fin part in the process of forming the groove at the edge of the fin part and ensure that the structure of the formed source-drain doped region is incomplete, so that the stress on a channel is reduced, and a pseudo-gate structure is formed at the edge of the fin part before the groove is formed. In order to improve the integration of the semiconductor structure, a dummy gate structure is generally formed on the edge of the adjacent fin and the isolation structure.
However, if the surface of the isolation structure at the edge of the fin is lower than the top surface of the fin, after the dummy gate structure is formed, the dummy gate structure is difficult to fully cover the edge of the fin, so that it is difficult to ensure that the formed source-drain doped region can provide sufficient stress for a channel, and the performance of a transistor is easily affected.
Therefore, the performance of the semiconductor structure formed by the method for forming the semiconductor structure is poor.
Disclosure of Invention
The invention solves the problem of providing a method for forming a semiconductor structure, which can improve the performance of the semiconductor structure.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate comprising: the device comprises a substrate, and a first fin part and a second fin part which are adjacent to each other and are positioned on the substrate; forming an isolation structure on the substrate, wherein the isolation structure covers the side walls of the first fin portion and the second fin portion, and the surface of the isolation structure is higher than or flush with the top surfaces of the first fin portion and the second fin portion; performing ion implantation on the isolation structure between the first fin part and the second fin part to form an isolation layer; and after forming the isolation layer, etching the isolation structure to enable the isolation structure to expose partial side walls of the first fin part and the second fin part, wherein the etching rate of the isolation layer is lower than that of the isolation structure in the etching process of the isolation structure.
Optionally, the ions implanted in the ion implantation process include: silicon ions, carbon ions or germanium ions.
Optionally, the process parameters of the ion implantation include: the implantation dose is 1.0E13atoms/cm2～1.0E16atoms/cm2(ii) a The injection energy is 1eV to 30 eV.
Optionally, the process for forming the isolation structure includes: a fluid chemical vapor deposition process.
Optionally, before etching the isolation structure, the method further includes: and forming a protective layer on the isolation layer.
Optionally, the step of performing ion implantation on the isolation structure between the first fin portion and the second fin portion includes: forming initial pattern layers on the top of the first fin portion, the top of the second fin portion and the isolation structure; removing the initial pattern layer on the isolation structure between the first fin part and the second fin part to form a pattern layer; and performing ion implantation by taking the graphic layer as a mask.
Optionally, the pattern layer is made of silicon nitride or silicon oxynitride.
Optionally, after the ion implantation, the forming method further includes: forming an initial protective layer on the pattern layer and the isolation layer; and removing the pattern layer and the initial protective layer on the pattern layer, and reserving the initial protective layer on the isolation layer to form a protective layer.
Optionally, the material of the protective layer is different from the material of the graphic layer.
Optionally, the material of the protective layer is silicon oxide.
Optionally, the process for forming the initial protection layer includes: high density plasma deposition process.
Optionally, the process parameters for forming the initial protection layer include: the reaction gas includes: silane or tetraethoxysilane, oxygen and argon or hydrogen; the reaction temperature is 300-500 ℃.
Optionally, the method further includes: after the isolation structure is etched, forming a pseudo gate structure on a region, adjacent to the isolation layer, of the first fin portion and a region, adjacent to the isolation layer, of the second fin portion; forming a first gate structure crossing the first fin portion, wherein the first gate structure covers the side wall and the top surface of the first fin portion; forming a second gate structure crossing the second fin portion, wherein the second gate structure covers the side wall and the top surface of the second fin portion; forming a first source drain doped region in the first fin part between the first grid structure and the dummy grid structure; and forming a second source-drain doped region in the second fin part between the second grid structure and the dummy grid structure.
Accordingly, the present invention also provides a semiconductor structure comprising: a substrate, the substrate comprising: the device comprises a substrate, and a first fin part and a second fin part which are adjacent to each other and are positioned on the substrate; the isolation structure and the isolation layer are located on the substrate, the isolation structure and the isolation layer cover partial side walls of the first fin portion and the second fin portion, the isolation layer is located on the substrate between the first fin portion and the second fin portion, doped ions are arranged in the isolation layer, and the surface of the isolation layer is higher than or flush with the top surfaces of the first fin portion and the second fin portion.
Optionally, the doping ions are silicon ions, carbon ions or germanium ions.
Optionally, the concentration of the doping ions is 1.0E13atoms/cm2～1.0E16atoms/cm2。
Optionally, the material of the isolation layer is silicon oxide containing the dopant ions.
Optionally, the method further includes: a protective layer on the isolation layer.
Optionally, the protective layer is made of silicon oxide or silicon oxynitride.
Optionally, the method further includes: the dummy gate structure is positioned on the region, adjacent to the isolation layer, of the first fin part and the region, adjacent to the isolation layer, of the second fin part; a first gate structure spanning the first fin, the first gate structure covering a portion of the sidewall and a top surface of the first fin; a second gate structure crossing the second fin portion, the second gate structure covering a portion of the sidewall and a top surface of the second fin portion; the first source-drain doped region is positioned in the first fin part between the first gate structure and the dummy gate structure; and the second source-drain doped region is positioned in the second fin part between the second gate structure and the dummy gate structure.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the method for forming the semiconductor structure, the isolation structure between the first fin part and the second fin part is subjected to ion implantation to form the isolation layer, and the etching rate of the isolation layer is smaller than that of the isolation structure in the process of etching the isolation structure. Therefore, in the process of etching the isolation structure, the isolation layer is not easy to etch, so that the isolation layer has better isolation performance. Therefore, the forming method can improve the performance of the formed semiconductor structure.
Furthermore, in the process of etching the isolation structure, the etching rate of the isolation layer is less than that of the isolation structure, so that the isolation layer is not easy to etch, and the formed pseudo gate structure can cover the edge of the fin part. The dummy gate structure can protect the first fin portion and the second fin portion below the dummy gate structure in the process of forming the first source drain doping area and the second source drain doping area, so that seeds are provided for forming the first source drain doping area and the second source drain doping area, the first source drain doping area and the second source drain doping area which are complete in structure are formed, sufficient stress can be provided for a channel by the first source drain doping area and the second source drain doping area, and the performance of the formed semiconductor structure is improved.
Furthermore, the process temperature for forming the initial protection layer through the high-density plasma deposition process is lower, and the influence on the formed semiconductor structure is smaller.
In the semiconductor structure, an isolation layer is arranged on the substrate between the first fin part and the second fin part, and the etching rate of the isolation layer is less than that of the isolation structure. Therefore, the isolation layer is not easy to be damaged in the process of etching the isolation structure, so that the performance of the formed semiconductor structure can be improved.
Drawings
FIGS. 1-4 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 5 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The formation method of the semiconductor structure has many problems, such as: the performance of the formed semiconductor structure is poor.
Now, with reference to a method for forming a semiconductor structure, the reason for the poor performance of the semiconductor structure formed by the method is analyzed:
fig. 1 to 4 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, the substrate includes: a substrate 100 and adjacent first and second fins 101, 102 on the substrate 100.
With continued reference to fig. 1, an isolation structure 110 is formed on the substrate 100 by a fluid chemical deposition process, the isolation structure covers the sidewalls of the first fin and the second fin, and the surface of the isolation structure 110 is flush with the top surfaces of the first fin 101 and the second fin 102.
Referring to fig. 2, a protection layer 131 is formed on the isolation structure 110 between the first fin 101 and the second fin 102.
Referring to fig. 3 and 4, fig. 4 is a side cross-sectional view taken along line 1-1' of fig. 3, and the isolation structure 110 is etched using the protection layer 131 as a mask so that the surface of the isolation structure 110 is lower than the top surfaces of the first fin 101 and the second fin 102.
After the isolation structure 110 is etched, forming a pseudo gate structure on the protection layer 131 and on portions of the first fin portion 101 and the second fin portion 102 which are in contact with the protection layer 131; and forming a source-drain doped region in a region of the first fin portion 101 adjacent to the pseudo-gate structure and a region of the second fin portion 102 adjacent to the second fin portion 101 through an epitaxial growth process.
In the method for forming the semiconductor structure, the isolation structure 110 is formed through a fluid chemical vapor deposition process, and the fluid chemical vapor deposition process enables the isolation structure 110 to fully fill a gap between the first fin 101 and the second fin 102. However, the isolation structure 110 formed by the fluid chemical vapor deposition process is not dense and is easily etched.
In the process of etching the isolation structure 110, the isolation structure 110 between the first fin portion 101 and the second fin portion 102 is easily etched, so that the isolation structure 110 between the first fin portion 101 and the second fin portion 102 is easily etched through, which results in a reduction in isolation performance of the isolation structure 110, and further easily affects performance of the formed semiconductor structure.
For example, the isolation structure 110 between the first fin 101 and the second fin 102 is etched through, which may easily cause the surface of the protection layer 131 to be lower than the top surface of the first fin 101 or the second fin 102. The surface of the protection layer 131 is lower than the surface of the first fin portion 101 or the surface of the second fin portion 102, so that the edges of the first fin portion 101 and the second fin portion 102 are difficult to be covered by the dummy gate structure, and in the process of forming the source-drain grooves, portions of the first fin portion 101 and the second fin portion 102 adjacent to the isolation structure 110 are easily removed by etching, and the isolation structure 110 between the first fin portion 101 and the second fin portion 102 is exposed. Since it is difficult to grow a source-drain doped region on the exposed isolation structure 110, the structure of the formed source-drain doped region is incomplete, and it is difficult to provide sufficient stress for the channel. Therefore, the performance of the semiconductor structure formed by the forming method is poor.
In order to solve the technical problem, the invention provides a method for forming a semiconductor structure, which comprises the following steps: providing a substrate comprising: the device comprises a substrate, and a first fin part and a second fin part which are adjacent to each other and are positioned on the substrate; forming an isolation structure on the substrate, wherein the surface of the isolation structure is higher than or flush with the top surfaces of the first fin part and the second fin part; performing ion implantation on the isolation structure between the first fin part and the second fin part to form an isolation layer; and after forming the isolation layer, etching the isolation structure to enable the isolation structure to expose partial side walls of the fin part, wherein the etching rate of the isolation layer is lower than that of the isolation structure in the process of etching the isolation structure.
The isolation structure between the first fin portion and the second fin portion is subjected to ion implantation to form an isolation layer, and in the process of etching the isolation structure, the etching rate of the isolation layer is smaller than that of the isolation structure. Therefore, in the process of etching the isolation structure, the isolation layer is not easy to etch, so that the isolation layer has better isolation performance. Therefore, the forming method can improve the performance of the formed semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 15 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 5, a substrate is provided, the substrate includes: a substrate 200 and adjacent first and second fins 201, 202 on the substrate 200.
In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In this embodiment, the first fin portion 201 and the second fin portion 202 are made of silicon. In other embodiments, the material of the first fin portion and the second fin portion may also be germanium or silicon germanium.
In this embodiment, the forming of the substrate includes: providing an initial substrate; forming a patterned mask layer 203 on the initial substrate; and etching the initial substrate by taking the mask layer 203 as a mask to form the substrate 200 and a first fin portion 201 and a second fin portion 202 which are adjacent to each other and located on the substrate 200.
In this embodiment, the mask layer 203 is made of silicon nitride or silicon oxynitride.
In this embodiment, the substrate includes a plurality of fin portions.
Referring to fig. 6, an isolation structure 210 is formed on the substrate 200, the isolation structure covers sidewalls of the first fin 201 and the second fin 202, and a surface of the isolation structure 210 is higher than or flush with top surfaces of the first fin 201 and the second fin 202.
The isolation structure 210 is used to achieve electrical insulation between the first fin 201 and the second fin 202.
In this embodiment, the isolation structure 210 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be germanium oxide or silicon oxynitride.
In the present embodiment, the isolation structure 210 is formed by a Fluid Chemical Vapor Deposition (FCVD) process. The isolation structures 210 formed by the bulk cvd process can substantially fill the gap between the first fin 201 and the second fin 202.
In this embodiment, the step of forming the isolation structure 210 by a fluid chemical vapor deposition process includes: forming a precursor on the substrate 200 between the first fin 201 and the second fin 202; the precursor is subjected to a water vapor anneal process to activate the precursor, forming isolation structures 210.
The precursor has certain fluidity and can fully fill the gap between the first fin 201 and the second fin 202, so as to form the isolation structure 210 fully filling the gap between the first fin 201 and the second fin 202. The principle of the fluid chemical vapor deposition process is as follows: the precursor is a polymer composed of atoms such as silicon, hydrogen, oxygen, nitrogen and the like, and in the water vapor annealing process, the hydrogen and nitrogen atoms in the polymer are replaced by oxygen atoms to form silicon oxide. However, during the water vapor annealing process, the hydrogen and nitrogen atoms in the polymer are difficult to be sufficiently replaced by oxygen atoms, so that the stoichiometric silicon oxide content in the formed isolation structure 210 is low, and the formed isolation structure 210 has low compactness and is easy to etch.
In this embodiment, after the forming the isolation structure 210, the method further includes: the isolation structure 210 is planarized.
The planarization process is used to planarize the surface of the isolation structure 210, thereby providing a relatively planar etching surface for the subsequent etching process.
In this embodiment, the planarization process is implemented by a chemical mechanical polishing process.
Referring to fig. 7 and 8, in the present embodiment, after the isolation structure 210 is formed, the forming method further includes: well regions are formed in the first and second fin portions 201 and 202.
In this embodiment, the step of forming the well region is as shown in fig. 7 and fig. 8.
Referring to fig. 7, the mask layer 203 is removed (as shown in fig. 5), exposing the top surfaces of the first and second fins 201 and 202.
In this embodiment, the mask layer 203 is removed by using dry etching, wet etching, or dry and wet etching.
Referring to fig. 8, well region ion implantation is performed on the first fin portion 201 and the second fin portion 202 to form a well region.
In this embodiment, if the first fin portion 201 and the second fin portion 202 are used to form a PMOS transistor, the implanted ions implanted by the well region ions include phosphorus ions or arsenic ions; if the first fin portion 201 and the second fin portion 202 are used to form an NMOS transistor, the implanted ions implanted by the well region ions include boron ions.
Referring to fig. 9 to 11, ion implantation is performed on the isolation structure 210 between the first fin 201 and the second fin 202 to form an isolation layer 211.
In this embodiment, the steps of performing ion implantation on the isolation structure 210 between the first fin portion 201 and the second fin portion 202 are as shown in fig. 9 to 11.
Referring to fig. 9, an initial pattern layer 220 is formed on top of the first and second fins 201 and 202 and on the isolation structure 210.
The initial graphics layer 220 is used to form a graphics layer.
In this embodiment, the material of the initial pattern layer 220 is different from that of the isolation structure 210. The initial pattern layer 220 and the isolation structure 210 having different materials can reduce damage to the isolation structure 210 during subsequent etching of the initial pattern layer 220. Specifically, the material of the initial pattern layer 220 is silicon nitride. In other embodiments, the material of the initial pattern layer 220 may also be silicon oxynitride or photoresist.
In this embodiment, the initial pattern layer 220 may be formed by a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
Referring to fig. 10, the initial pattern layer 220 on the isolation structure 210 between the first fin portion 201 and the second fin portion 202 is removed (as shown in fig. 9), and a pattern layer 221 is formed.
In this embodiment, the initial pattern layer 220 on the isolation structure 210 between the first fin portion 201 and the second fin portion 202 is removed by dry etching, wet etching, or a combination of dry etching and wet etching.
In the process of etching the initial pattern layer 220 on the isolation structure 210 between the first fin portion 201 and the second fin portion 202, the isolation structure 210 between the first fin portion 201 and the second fin portion 202 is also easily etched to form a pit. In other embodiments, the dimples may not be formed.
In this embodiment, the graphics layer 221 is formed by the initial graphics layer 220. Therefore, the material of the graphic layer 221 is the same as that of the initial graphic layer 220. Specifically, the pattern layer 221 is made of silicon nitride.
Referring to fig. 11, ion implantation is performed using the pattern layer 221 as a mask to form the isolation layer 211.
The ion implantation is used to increase the compactness of the isolation structure 210 between the first fin portion 201 and the second fin portion 202, so as to reduce the etching rate of the isolation layer 211 in the subsequent etching process of the isolation structure 210 and reduce the loss of the isolation layer. Therefore, the ion implantation enables a subsequently formed dummy gate structure to fully cover the edges of the first fin portion 201 and the second fin portion 202, so that a source-drain doped region with a complete structure can be formed, the stress of the source-drain doped region on a channel is increased, and the performance of a transistor is improved.
In this embodiment, the implanted ions are silicon ions, and the isolation structure 210 is made of silicon oxide. After silicon ions are implanted into the silicon oxide, the implanted silicon ions can form silicon-silicon bonds with silicon atoms in the isolation structure 210, so that the compactness of the formed isolation layer 211 is increased, and the etching rate of the isolation layer 211 in the process of etching the isolation structure is reduced. In other embodiments, the implanted ions may also be carbon or germanium.
In this embodiment, the process parameters of the ion implantation include: the implantation dose is 1.0E13atoms/cm2～1.0E16atoms/cm2(ii) a The injection energy is 1eV to 30 eV.
In this embodiment, after the ion implantation and before the etching of the isolation structure, the forming method further includes: a protective layer is formed on the isolation layer 211.
In this embodiment, the step of forming the protective layer is as shown in fig. 12 and 13.
Referring to fig. 12, an initial protection layer 230 is formed on the isolation layer 211 and the pattern layer 221.
The initial protective layer 230 is used to form a protective layer.
In this embodiment, the material of the initial protection layer 230 is different from that of the pattern layer 221. The initial protection layer 230 and the pattern layer 221, which have different materials, can make it difficult to remove the initial protection layer above the isolation layer 211 in the subsequent process of removing the pattern layer 221. Specifically, in this embodiment, the material of the initial protection layer 230 is silicon oxide. In other embodiments, the material of the initial protection layer may also be silicon oxynitride.
In this embodiment, the process of forming the initial protection layer 230 includes: a High Density Plasma (HDP) deposition process. The reaction temperature of the high-density plasma deposition process is low, and the influence on the performance of the formed semiconductor structure is small. And the compactness of the protective layer 230 formed by the high-density plasma deposition process is better than that of the isolation structure 210, and the protective layer 211 is stronger. In other embodiments, the initial protective layer may also be formed by a high aspect ratio process.
In this embodiment, the process parameters for forming the initial protection layer 230 by the high density plasma deposition process include: the reaction gas comprises silane or tetraethoxysilane, oxygen and argon or hydrogen; the reaction temperature is 300-500 ℃.
Referring to fig. 13, the pattern layer 221 (shown in fig. 12) and the initial protection layer 230 on the pattern layer 221 (shown in fig. 12) are removed, and the initial protection layer 230 on the isolation layer 211 is remained to form a protection layer 231.
The protection layer 231 is used to protect the isolation layer 211 during the subsequent etching of the isolation structure 210.
In this embodiment, the pattern layer 221 is etched to remove the pattern layer 221, so that the initial protection layer 230 on the pattern layer 221 is separated from the substrate, thereby removing the initial protection layer 230.
In this embodiment, the pattern layer 221 is removed by wet etching or dry etching.
In this embodiment, the material of the protection layer 231 is the same as that of the initial protection layer 230. Specifically, the material of the protection layer 231 is silicon oxide.
Before forming the protective layer 231, the forming method further includes: the surface of the initial protection layer 230 is planarized by chemical mechanical polishing.
Referring to fig. 14, after forming an isolation layer, the isolation structure 210 is etched to expose partial sidewalls of the first fin 201 and the second fin 202, and an etching rate of the isolation layer 211 is lower than an etching rate of the isolation structure 210 in a process of etching the isolation structure 210.
In the process of etching the isolation structure 210, the etching rate of the isolation layer 211 is lower than that of the isolation structure 210, so that the loss of the isolation layer 211 can be reduced, and the performance of the formed semiconductor structure can be improved.
In this embodiment, the isolation structure 210 may be etched by dry etching, wet etching, or a common application of dry etching and wet etching.
It should be noted that, in this embodiment, after the etching is performed on the isolation structure 210, the method further includes: the protection layer 231 is etched, so that the surface of the protection layer 230 is flush with the top surfaces of the first fin portion 201 and the second fin portion 202, or the surface of the protection layer 230 is slightly higher than the top surfaces of the first fin portion 201 and the second fin portion 202.
Referring to fig. 15, in the present embodiment, the forming method further includes: forming a dummy gate structure 240 on a region of the first fin 201 adjacent to the isolation layer 211 and a region of the second fin 202 adjacent to the isolation layer 211;
forming a first gate structure 241 crossing the first fin 201, wherein the first gate structure 241 covers part of the sidewall and the top surface of the first fin 201;
forming a second gate structure 242 crossing the second fin 202, wherein the second gate structure 242 covers part of the sidewall and the top surface of the second fin 201;
forming a first source drain doped region 251 in the first fin portion 201 between the first gate structure 241 and the dummy gate structure 240;
a second source-drain doped region 252 is formed in the second fin 202 between the second gate structure 242 and the dummy gate structure 240.
In summary, in the method for forming the semiconductor structure, the isolation structure between the first fin portion and the second fin portion is ion implanted to form the isolation layer, and an etching rate of the isolation layer is smaller than an etching rate of the isolation structure in a process of etching the isolation structure. Therefore, in the process of etching the isolation structure, the isolation layer is not easy to etch, so that the isolation layer has better isolation performance. Therefore, the forming method can improve the performance of the formed semiconductor structure.
Furthermore, in the process of etching the isolation structure, the etching rate of the isolation layer is less than that of the isolation structure, so that the isolation layer is not easy to etch, and the formed pseudo gate structure can cover the edge of the fin part. The dummy gate structure can protect the first fin portion and the second fin portion below the dummy gate structure in the process of forming the first source drain doping area and the second source drain doping area, so that seeds are provided for forming the first source drain doping area and the second source drain doping area, the first source drain doping area and the second source drain doping area which are complete in structure are formed, sufficient stress can be provided for a channel by the first source drain doping area and the second source drain doping area, and the performance of the formed semiconductor structure is improved.
Furthermore, the process temperature for forming the initial protection layer through the high-density plasma deposition process is lower, and the influence on the formed semiconductor structure is smaller.
With continued reference to fig. 15, the present invention also provides a semiconductor structure comprising: a substrate, the substrate comprising: a substrate 200 and a first fin portion 201 and a second fin portion 202 which are adjacent to each other and located on the substrate 200; the isolation structure 210 and the isolation layer 211 are located on the substrate 200, the isolation structure 210 and the isolation layer 211 cover the side walls of the first fin portion 201 and the second fin portion 202, the surface of the isolation structure 210 is lower than the top surfaces of the first fin portion 201 and the second fin portion 202, the isolation layer 211 is located on the substrate 200 between the first fin portion 201 and the second fin portion 202, doped ions are located in the isolation layer 211, the etching rate of the isolation layer 211 is lower than that of the isolation structure 210, and the surface of the isolation layer 211 is higher than or flush with the top surfaces of the first fin portion 201 and the second fin portion 202.
The semiconductor structure is described in detail below with reference to the accompanying drawings.
In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator substrate, or a germanium-on-insulator substrate.
In this embodiment, the first fin portion 201 and the second fin portion 202 are made of silicon. In other embodiments, the material of the first fin portion and the second fin portion may also be germanium or silicon germanium.
In this embodiment, the substrate includes a plurality of fin portions.
The isolation structure 210 is used to achieve electrical insulation between the first fin 201 and the second fin 202.
In this embodiment, the isolation structure 210 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be germanium oxide or silicon oxynitride.
The doped ions can increase the compactness of the isolation layer 211, so that the compactness of the isolation layer 211 is greater than that of the isolation structure 210, and thus the etching rate of the isolation layer 211 can be reduced when the isolation structure 210 is etched, the dummy gate structure 240 can fully cover the edges of the first fin portion 201 and the second fin portion 202, and the incompleteness of the structures of the first source drain doped region 251 and the second source drain doped region 252 can be avoided. Therefore, the first source drain doped region 251 and the second source drain doped region 252 in the semiconductor structure can provide sufficient stress for a channel, so that the performance of the semiconductor structure is improved.
In this embodiment, the material of the isolation layer 211 is silicon oxide containing the dopant ions.
In this embodiment, the doped ions are silicon ions, and the isolation structure 210 is made of silicon oxide. Silicon ions can form silicon-silicon bonds with silicon atoms in the isolation structure 210, so that the compactness of the formed isolation layer 211 is increased, and the etching rate of the isolation layer 211 in the etching process of the isolation structure is reduced. In other embodiments, the dopant ion may also be carbon or germanium.
If the concentration of the dopant ions is too low, it is difficult to increase the compactness of the isolation layer 211 and reduce the etching rate; if the concentration of the dopant ions is too high, material and energy waste is easily generated. Specifically, in this embodiment, the concentration of the dopant ions is 1.0E13atoms/cm2～1.0E16atoms/cm2。
In this embodiment, the semiconductor structure further includes: a protective layer 231 on the isolation layer 211. In other embodiments, the semiconductor structure may further not include the protection layer if a surface of the isolation layer is flush with top surfaces of the first and second fins.
In this embodiment, the material of the protection layer 231 is silicon oxide or silicon oxynitride.
In this embodiment, the semiconductor structure further includes:
a dummy gate structure 240 on a region of the first fin adjacent to the isolation layer and a region of the second fin adjacent to the isolation layer;
a first gate structure 241 spanning the first fin 201, the first gate structure 241 covering a portion of the sidewalls and a top surface of the first fin 201;
a second gate structure 242 spanning the second fin 202, the second gate structure 242 covering a portion of sidewalls and a top surface of the second fin 202;
a first source-drain doped region 251 in the first fin portion 201 between the first gate structure 241 and the dummy gate structure 240;
and a second source-drain doped region 252 in the second fin 202 between the second gate structure 242 and the dummy gate structure 240.
In summary, in the semiconductor structure of the present invention, an isolation layer is disposed on the substrate between the first fin portion and the second fin portion, and an etching rate of the isolation layer is less than an etching rate of the isolation structure. Therefore, the isolation layer is not easy to be damaged in the process of etching the isolation structure, so that the performance of the formed semiconductor structure can be improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (18)
1. A method of forming a semiconductor structure, comprising:
providing a substrate comprising: the device comprises a substrate, and a first fin part and a second fin part which are adjacent to each other and are positioned on the substrate;
forming an isolation structure on the substrate, wherein the isolation structure covers the side walls of the first fin portion and the second fin portion, and the surface of the isolation structure is higher than or flush with the top surfaces of the first fin portion and the second fin portion;
performing ion implantation on the isolation structure between the first fin part and the second fin part to form an isolation layer;
forming a protective layer on the isolation layer;
etching the isolation structure by taking the protective layer as a mask to enable the isolation structure to expose partial side walls of the first fin part and the second fin part, wherein the etching rate of the isolation layer is lower than that of the isolation structure in the process of etching the isolation structure;
etching the protective layer to enable the surface of the protective layer to be flush with the top surfaces of the first fin portion and the second fin portion or enable the surface of the protective layer to be slightly higher than the top surfaces of the first fin portion and the second fin portion;
and after the protective layer is etched, forming a pseudo gate structure in the area of the first fin part adjacent to the isolation layer and the area of the second fin part adjacent to the isolation layer, wherein the formed pseudo gate structure covers the edges of the first fin part and the second fin part.
2. The method of claim 1, wherein the ions implanted during the ion implantation comprise: silicon ions, carbon ions or germanium ions.
3. The method of claim 2, wherein the ion implantation process parameters comprise: the implantation dose is 1.0E13atoms/cm2～1.0E16atoms/cm2(ii) a The injection energy is 1eV to 30 eV.
4. The method of forming a semiconductor structure of claim 1, wherein the process of forming the isolation structure comprises: a fluid chemical vapor deposition process.
5. The method of forming a semiconductor structure of claim 1, wherein the step of ion implanting the isolation structure between the first fin and the second fin comprises:
forming an initial pattern layer on the top of the first fin portion, the top of the second fin portion and the isolation structure;
removing the initial pattern layer on the isolation structure between the first fin part and the second fin part to form a pattern layer; and performing ion implantation by taking the graphic layer as a mask.
6. The method of claim 5, wherein the pattern layer is made of silicon nitride or silicon oxynitride.
7. The method of forming a semiconductor structure of claim 5, wherein the forming a protective layer on the isolation layer after ion implantation comprises:
forming an initial protective layer on the pattern layer and the isolation layer;
and removing the pattern layer and the initial protective layer on the pattern layer, and reserving the initial protective layer on the isolation layer to form a protective layer.
8. The method of forming a semiconductor structure according to claim 7, wherein a material of the protective layer is different from a material of the pattern layer.
9. The method of forming a semiconductor structure of claim 7, wherein a material of the protective layer is silicon oxide.
10. The method of forming a semiconductor structure of claim 7, wherein the process of forming the initial protective layer comprises: high density plasma deposition process.
11. The method of forming a semiconductor structure of claim 10, wherein the process parameters for forming the initial protection layer comprise: the reaction gas includes: silane or tetraethoxysilane, oxygen and argon or hydrogen; the reaction temperature is 300-500 ℃.
12. The method of forming a semiconductor structure of claim 1, wherein after forming the dummy gate structure, further comprising:
forming a first gate structure crossing the first fin portion, wherein the first gate structure covers the side wall and the top surface of the first fin portion;
forming a second gate structure crossing the second fin portion, wherein the second gate structure covers the side wall and the top surface of the second fin portion;
forming a first source drain doped region in the first fin part between the first grid structure and the dummy grid structure;
and forming a second source-drain doped region in the second fin part between the second grid structure and the dummy grid structure.
13. A semiconductor structure, comprising:
a substrate, the substrate comprising: the device comprises a substrate, and a first fin part and a second fin part which are adjacent to each other and are positioned on the substrate;
the isolation structure and the isolation layer are positioned on the substrate, the isolation structure and the isolation layer cover the side walls of the first fin portion and the second fin portion, the surface of the isolation structure is lower than the top surfaces of the first fin portion and the second fin portion, the isolation layer is positioned on the substrate between the first fin portion and the second fin portion, doped ions are arranged in the isolation layer, and the surface of the isolation layer is higher than or flush with the top surfaces of the first fin portion and the second fin portion;
the surface of the protective layer is flush with the top surfaces of the first fin portion and the second fin portion or the surface of the protective layer is slightly higher than the top surfaces of the first fin portion and the second fin portion;
and the dummy gate structure is positioned on the region of the first fin part adjacent to the isolation layer and the region of the second fin part adjacent to the isolation layer.
14. The semiconductor structure of claim 13, wherein the dopant ions are silicon ions, carbon ions, or germanium ions.
15. The semiconductor structure of claim 14, wherein said dopant ions are silicon ions and the concentration of said dopant ions is 1.0E13atoms/cm2～1.0E16atoms/cm2。
16. The semiconductor structure of claim 13, wherein a material of the isolation layer is silicon oxide containing the dopant ions.
17. The semiconductor structure of claim 13, wherein a material of the protective layer is silicon oxide or silicon oxynitride.
18. The semiconductor structure of claim 13, further comprising:
a first gate structure spanning the first fin, the first gate structure covering a portion of the sidewall and a top surface of the first fin;
a second gate structure crossing the second fin portion, the second gate structure covering a portion of the sidewall and a top surface of the second fin portion;
the first source-drain doped region is positioned in the first fin part between the first gate structure and the dummy gate structure;
and the second source-drain doped region is positioned in the second fin part between the second gate structure and the dummy gate structure.
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| CN104465486A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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| US9337318B2 (en) * | 2012-10-26 | 2016-05-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET with dummy gate on non-recessed shallow trench isolation (STI) |
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| CN104465486A (en) * | 2013-09-18 | 2015-03-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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