CN113782440A - Threshold voltage adjusting method of FinFET - Google Patents
Threshold voltage adjusting method of FinFET Download PDFInfo
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- CN113782440A CN113782440A CN202111010144.1A CN202111010144A CN113782440A CN 113782440 A CN113782440 A CN 113782440A CN 202111010144 A CN202111010144 A CN 202111010144A CN 113782440 A CN113782440 A CN 113782440A
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 239000012535 impurity Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000007943 implant Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 238000002347 injection Methods 0.000 claims abstract description 15
- 239000007924 injection Substances 0.000 claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 44
- 238000002513 implantation Methods 0.000 claims description 25
- 239000007779 soft material Substances 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 100
- 238000004088 simulation Methods 0.000 description 9
- 239000013078 crystal Substances 0.000 description 7
- 150000002500 ions Chemical class 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000005465 channeling Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005280 amorphization Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention discloses a threshold voltage adjusting method of a FinFET, which comprises the following steps: step one, carrying out graphical etching on a semiconductor substrate to form a fin body; filling an isolation dielectric layer in the spaced area of the fin body; etching the isolation medium layer to expose the top part of the fin body; forming a cap layer to cover the top part of the fin body, wherein the structural parameters of the cap layer are set according to the required value of the threshold voltage; and fifthly, carrying out threshold voltage adjustment injection, wherein impurities of the threshold voltage adjustment injection penetrate through the cap layer and enter the top part of the fin body to be used for adjusting the threshold voltage of the FinFET. The invention can adjust the threshold voltage of the device by changing the structural parameters of the cap layer, and for the same type of devices, the same threshold voltage can be adopted to adjust and implant to form devices with different threshold voltages.
Description
Technical Field
The present invention relates to the Field of semiconductor integrated circuit manufacturing, and in particular, to a method for adjusting a threshold voltage of a Fin Field Effect Transistor (FinFET).
Background
The channel region of the FinFET is formed in the fin body, the gate structure covers the top surface and two side surfaces of the fin body at the same time, and the fin body is covered by the gate structure from the channel region. The gate structure inverts the channel region to form an inversion layer on the surface of the channel region, and the conductive channel is composed of the inversion layer. The gate-source voltage required to form the inversion layer is the threshold voltage. The magnitude of the threshold voltage is related to the doping concentration of the channel region. In the conventional method, after the fin body is formed, an impurity is implanted into the channel region by threshold voltage adjustment implantation to adjust the threshold voltage.
The single crystal material layer is implanted to generate channel effect, and the fin body is formed by performing patterned etching on a single crystal semiconductor substrate such as a silicon substrate, so that the material of the fin body has a single crystal structure. The method for overcoming the channeling effect comprises the following steps:
the first method is to perform pre-amorphization ion implantation (PAI), which can amorphize the surface of a single crystal structure so as to randomly change the moving direction of implanted ions, thereby overcoming the channeling effect.
The second method is to form a cap layer on the surface of the single crystal structure, and the movement direction of the implanted ions is randomly changed through the cap layer. The cap layer forming process does not generate loss to the single crystal structure and can generate protection to the single crystal structure in ion implantation.
The third method is to perform angled ion implantation so that the ion implantation direction and the channeling direction are different.
In the existing threshold voltage adjusting method of the FinFET, the threshold voltage is mainly adjusted by threshold voltage adjusting implantation or a metal gate work function, and a cap layer is usually formed in the top portion of the fin body before the threshold voltage adjusting implantation to protect the top portion of the fin body. If a plurality of finfets with different threshold voltages need to be integrated on the same semiconductor substrate, threshold voltage adjustment injection with different parameters needs to be performed for a plurality of times, which is not only complicated in process but also unfavorable for threshold voltage adjustment.
Disclosure of Invention
The invention aims to provide a threshold voltage adjusting method of a FinFET, which can adjust the threshold voltage under the condition of not changing the threshold voltage adjusting injection, thereby increasing the process means of threshold voltage adjustment, being more beneficial to the accurate adjustment of the threshold voltage and having lower cost.
In order to solve the above technical problem, the threshold voltage adjusting method of the FinFET provided in the present invention includes the following steps:
step one, providing a semiconductor substrate, and carrying out graphical etching on the semiconductor substrate to form a fin body.
And secondly, filling an isolation dielectric layer in the interval area of the fin body.
And step three, etching the isolation medium layer to expose the top part of the fin body.
And fourthly, forming a cap layer to cover the top part of the fin body, wherein the structural parameters of the cap layer are set according to the required value of the threshold voltage.
And fifthly, carrying out threshold voltage adjusting injection, wherein impurities of the threshold voltage adjusting injection penetrate through the cap layer and enter the top part of the fin body to be used for adjusting the threshold voltage of the FinFET, and the size of the threshold voltage is determined by the parameters of the threshold voltage adjusting injection and the structural parameters of the cap layer.
In a further improvement, finfets integrated on the same semiconductor substrate include N-type finfets and P-type finfets.
In a further improvement, in step five, the threshold voltage adjustment implanted impurity type of the N-type FinFET is P-type, and the threshold voltage adjustment implanted impurity type of the P-type FinFET is N-type;
in step five, the threshold voltage adjustment implant of the N-type FinFET and the threshold voltage adjustment implant of the P-type FinFET are performed separately.
The further improvement is that the N-type FinFETs are classified into multiple types according to different threshold voltages;
in the fourth step, the cap layers of the N-type finfets of the same class and having the same threshold voltage have the same structural parameters, and the cap layers of the N-type finfets of the different classes and having the same threshold voltage have different structural parameters;
in the fifth step, all the N-type FinFETs are simultaneously realized by adopting the threshold voltage adjustment injection with the same parameters, and the difference of the threshold voltages of the N-type FinFETs is adjusted by the difference of the structural parameters of the cap layer.
The further improvement is that the P-type FinFETs are classified into multiple types according to different threshold voltages;
in the fourth step, the cap layers of the P-type finfets of the same class and with the same threshold voltage have the same structural parameters, and the cap layers of the P-type finfets of the different classes and with the same threshold voltage have different structural parameters;
in the fifth step, all the P-type finfets are simultaneously implemented by adopting the threshold voltage adjustment injection with the same parameters, and the difference of the threshold voltages of the various P-type finfets is adjusted by the difference of the structural parameters of the cap layer.
In a further improvement, in the first step, the semiconductor substrate comprises a silicon substrate.
The further improvement is that the isolation dielectric layer is made of an oxide layer.
In a further improvement, the isolation dielectric layer is formed by adopting an FCVD process.
In a further improvement, in step four, the structural parameters of the cap layer are adjusted by growing different material layers.
In a further improvement, the material of the cap layer comprises a soft material and a hard material, and the threshold voltage is adjusted by utilizing the characteristic that the ion blocking capability of the hard material for the threshold voltage adjustment implantation is greater than that of the soft material for the threshold voltage adjustment implantation; the larger the number of impurities which are injected into the fin body after passing through the soft material and the larger the obtained threshold voltage is, the larger the thickness is, the larger the threshold voltage is.
In a further refinement, the soft material comprises an oxide layer formed using an FCVD process and the hard material comprises a silicon nitride layer.
In a further improvement, in the fourth step, the structural parameters of the cap layer are also adjusted by adjusting the thickness of the material layer; when the material of the material layer is the same, the thinner the material layer is, the greater the number of the impurities implanted into the top portion of the fin body after passing through the material layer and the greater the obtained threshold voltage is.
In a further refinement, the material layer of the cap layer includes a plurality of material layers having different atomic dimensions; the smaller the atomic size of the material layer is, the larger the number of the impurities implanted into the top portion of the fin body after passing through the material layer and the larger the obtained threshold voltage is.
In a further improvement, in the fifth step, after the step is completed, the step of removing the cap layer is further included.
In a further improvement, in step five, the threshold voltage adjustment implantation is angled ion implantation.
In the prior art, a cap layer is formed before threshold voltage adjustment implantation and covers the surface of the top part of the fin body, and the cap layer is used for protecting the fin body in the threshold voltage adjustment implantation so as to prevent the fin body from being damaged by the threshold voltage adjustment implantation; the invention breaks through the conventional knowledge of the existing cap layer, utilizes the characteristic that the cap layer can block the ion implantation so as to cause the energy loss of the implantation, further adjusts the structural parameters of the cap layer and causes the cap layers with different structural parameters to have different impedance effects on the threshold voltage adjustment implantation and further causes the concentration of impurities implanted into the top part of the fin body to be different, thereby realizing the adjustment of the threshold voltage; therefore, the structural parameters of the cap layer covering the top part of the fin body are set according to the requirement of the threshold voltage, so that the threshold voltage can be adjusted under the condition of not changing the threshold voltage adjusting injection, the technological means of threshold voltage adjustment can be increased, the accurate adjustment of the threshold voltage is facilitated, and the cost is lower.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a process flow diagram of a method of threshold voltage adjustment for a FinFET in accordance with an embodiment of the present invention;
fig. 2 is a cross-sectional structure diagram of a device corresponding to a threshold voltage adjustment implantation performed in the method for adjusting threshold voltage of a FinFET of the present invention;
FIG. 3A is a simulation plot of the doping concentration profile of a fin formed with two different capping layers in a method in accordance with an embodiment of the present invention;
fig. 3B is a simulation plot of drain current and gate voltage for the FinFET of fig. 3A for two cap layers.
Detailed Description
Fig. 1 is a process flow diagram of a threshold voltage adjustment method of a FinFET in accordance with an embodiment of the present invention; as shown in fig. 2, it is a cross-sectional structure diagram of a device corresponding to the threshold voltage adjustment implantation 104 in the threshold voltage adjustment method of the FinFET in the embodiment of the present invention; the threshold voltage adjusting method of the FinFET comprises the following steps:
step one, providing a semiconductor substrate 101a, and performing patterned etching on the semiconductor substrate 101a to form a fin body 101.
In the embodiment of the present invention, the semiconductor substrate 101a includes a silicon substrate.
And step two, filling an isolation dielectric layer 102 in the spaced area of the fin body 101.
In the embodiment of the present invention, the isolation dielectric layer 102 is made of an oxide layer.
The isolation dielectric layer 102 is formed by an FCVD process.
And step three, etching the isolation medium layer 102 to expose the top part of the fin body 101.
And step four, forming a cap layer 103 to cover the top part of the fin body 101, wherein the structural parameters of the cap layer 103 are set according to the required value of the threshold voltage.
And step five, performing a threshold voltage adjusting implantation 104, wherein impurities of the threshold voltage adjusting implantation 104 penetrate through the cap layer 103 and enter the top part of the fin body 101 to adjust the threshold voltage of the FinFET, and the size of the threshold voltage is determined by parameters of the threshold voltage adjusting implantation 104 and structural parameters of the cap layer 103.
In the embodiment of the present invention, the finfets integrated on the same semiconductor substrate 101a include N-type finfets and P-type finfets.
In step five, the impurity type of the threshold voltage adjustment implant 104 of the N-type FinFET is P-type, and the impurity type of the threshold voltage adjustment implant 104 of the P-type FinFET is N-type.
In step five, the threshold voltage adjustment implant 104 of the N-type FinFET and the threshold voltage adjustment implant 104 of the P-type FinFET are performed separately.
The N-type FinFETs are classified into multiple types according to different threshold voltages.
In the fourth step, the cap layer 103 of the N-type finfets of the same class and having the same threshold voltage have the same structural parameters, and the cap layer 103 of each class of N-type finfets having different and the same threshold voltage have different structural parameters.
In step five, all the N-type finfets are simultaneously implemented by using the threshold voltage adjustment implant 104 with the same parameters, and the difference of the threshold voltages of the N-type finfets is adjusted by the difference of the structural parameters of the cap layer 103.
The P-type FinFETs are divided into a plurality of types according to different threshold voltages;
in the fourth step, the cap layer 103 of the P-type FinFET of the same type and with the same threshold voltage has the same structural parameters, and the cap layer 103 of the P-type FinFET of the different types and with the same threshold voltage has different structural parameters.
In step five, all the P-type finfets are implemented simultaneously by using the threshold voltage adjustment implants 104 with the same parameters, and the difference of the threshold voltages of the P-type finfets is adjusted by the difference of the structural parameters of the cap layer 103.
In step four, the structural parameters of the cap layer 103 are adjusted by growing different material layers.
The material of the cap layer 103 comprises a soft material and a hard material, and the threshold voltage is adjusted by utilizing the characteristic that the ion blocking capability of the hard material to the threshold voltage adjusting implantation 104 is greater than the ion blocking capability of the soft material to the threshold voltage adjusting implantation 104; the greater the number of impurities of the threshold voltage adjustment implant 104 that penetrate the soft material into the top portion of the fin 101 and the greater the resulting threshold voltage, when the thicknesses are the same.
The soft material comprises an oxide layer formed by adopting an FCVD process, and the hard material comprises a silicon nitride layer.
In the fourth step, the structural parameters of the cap layer 103 are further adjusted by adjusting the thickness of the material layer; the same material is used, the thinner the material layer is, the greater the number of impurities of the threshold voltage adjustment implant 104 that penetrate through the material layer and enter the top portion of the fin 101 and the greater the resulting threshold voltage.
The material layer of the cap layer 103 comprises a plurality of material layers with different atomic sizes; the smaller the atomic size of the material layer, the greater the number of impurities of the threshold voltage adjustment implant 104 that penetrate the material layer into the top portion of the fin 101 and the resulting threshold voltage.
And step five, after the step is finished, the step of removing the cap layer 103 is further included.
In step five, the threshold voltage adjustment implantation 104 employs angled ion implantation.
Typically, a step of forming a well region in the fin body is further included after step two is completed and before step three is performed. After the cap layer 103 is removed, forming a first gate dielectric layer on the surface of the top portion of the fin body 101 to form a polysilicon dummy gate; forming side walls on the side surfaces of the polycrystalline silicon pseudo-gate, forming embedded epitaxial layers in the fin bodies on the two sides of the polycrystalline silicon pseudo-gate, forming zero-layer interlayer films, and performing a chemical mechanical polishing process until the zero-layer interlayer films are level to the top surface of the polycrystalline silicon pseudo-gate; and then carrying out a metal gate replacement process. For the input-output FinFET, the gate dielectric layer can directly adopt the first gate dielectric layer, the first gate dielectric layer in the forming area of the input-output FinFET is not removed in the metal gate replacement process, only the first gate dielectric layer in the forming area of the core FinFET is removed, then the second gate dielectric layer comprising the high-dielectric-constant material is formed in the forming area of the core FinFET, and then the metal gate is formed.
In the prior art, the capping layer 103 is formed before the threshold voltage adjustment implantation 104 and covers the surface of the top portion of the fin 101, and the capping layer 103 is used for protecting the fin 101 in the threshold voltage adjustment implantation 104 and preventing the fin 101 from being damaged by the threshold voltage adjustment implantation 104; the embodiment of the invention breaks through the conventional knowledge of the cap layer 103 in the prior art, utilizes the characteristic that the cap layer 103 can block the ion implantation so as to cause the energy loss of the implantation, further adjusts the structural parameters of the cap layer 103, and further causes the cap layer 103 with different structural parameters to have different impedance effects on the threshold voltage adjusting implantation 104 and further causes the concentration of impurities implanted into the top part of the fin body 101 to be different, thereby realizing the adjustment of the threshold voltage; therefore, in the embodiment of the present invention, the structural parameters of the cap layer 103 covering the top portion of the fin 101 are set according to the requirement of the threshold voltage, so that the threshold voltage can be adjusted without changing the threshold voltage adjustment implant 104, thereby increasing the process means for adjusting the threshold voltage, facilitating the precise adjustment of the threshold voltage, and reducing the cost.
FIG. 3A is a graph showing a simulation curve of the doping concentration profile of a fin formed by two different capping layers in an exemplary method of the present invention; in fig. 3A, a dotted line AA corresponds to the top surface of the fin body, a dotted line BB corresponds to the bottom surface of the top portion of the fin body 101, i.e., the top surface of the isolation dielectric layer 102, and a part between the dotted lines AA and BB corresponds to the top portion of the fin body 101; the atomic size of the cap layer 103 corresponding to the curve 201 is smaller, so that the implanted ions easily penetrate into the top portion of the fin 101; the atomic size of the cap layer 103 corresponding to the curve 202 is smaller, so that the implanted ions penetrate into the fin 101 less. The simulation curve of fig. 3A corresponds to the simulation curve of PMOS, and the implanted impurity of the threshold voltage adjustment implant 104 is phosphorus, and it can be seen that in the top portion of the fin 101, the value of the curve 202 is lower than the value of the curve 201, making the FinFET corresponding to the curve 201 the first FinFET, and the FinFET corresponding to the curve 202 the second FinFET. It should be appreciated by those skilled in the art that the smaller the doping concentration of the channel region, the smaller the threshold voltage of the device will be, so it can be obtained that the threshold voltage of the second FinFET will be less than the threshold voltage of the first FinFET.
As shown in fig. 3B, is a simulation curve of drain current and gate voltage of the FinFET corresponding to the two cap layers in fig. 3A, i.e., an Id-Vg simulation curve. Curve 203 is the Id-Vg simulation curve for the first FinFET and curve 204 is the Id-Vg simulation curve for the second FinFET, it can be seen that the threshold voltage of the second FinFET is indeed less than the threshold voltage of the first FinFET.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (15)
1. A threshold voltage adjustment method of a FinFET is characterized by comprising the following steps:
providing a semiconductor substrate, and carrying out graphical etching on the semiconductor substrate to form a fin body;
filling an isolation dielectric layer in the interval area of the fin body;
etching the isolation medium layer to expose the top part of the fin body;
forming a cap layer to cover the top part of the fin body, wherein the structural parameters of the cap layer are set according to the required value of the threshold voltage;
and fifthly, carrying out threshold voltage adjusting injection, wherein impurities of the threshold voltage adjusting injection penetrate through the cap layer and enter the top part of the fin body to be used for adjusting the threshold voltage of the FinFET, and the size of the threshold voltage is determined by the parameters of the threshold voltage adjusting injection and the structural parameters of the cap layer.
2. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: FinFETs integrated on the same semiconductor substrate comprise an N-type FinFET and a P-type FinFET.
3. The method of threshold voltage adjustment of a FinFET of claim 2, wherein: in step five, the type of the threshold voltage adjusting implanted impurity of the N-type FinFET is P-type, and the type of the threshold voltage adjusting implanted impurity of the P-type FinFET is N-type;
in step five, the threshold voltage adjustment implant of the N-type FinFET and the threshold voltage adjustment implant of the P-type FinFET are performed separately.
4. The method of threshold voltage adjustment of a FinFET of claim 3, wherein: the N-type FinFETs are divided into a plurality of types according to different threshold voltages;
in the fourth step, the cap layers of the N-type finfets of the same class and having the same threshold voltage have the same structural parameters, and the cap layers of the N-type finfets of the different classes and having the same threshold voltage have different structural parameters;
in the fifth step, all the N-type FinFETs are simultaneously realized by adopting the threshold voltage adjustment injection with the same parameters, and the difference of the threshold voltages of the N-type FinFETs is adjusted by the difference of the structural parameters of the cap layer.
5. The method of threshold voltage adjustment of a FinFET of claim 3, wherein: the P-type FinFETs are divided into a plurality of types according to different threshold voltages;
in the fourth step, the cap layers of the P-type finfets of the same class and with the same threshold voltage have the same structural parameters, and the cap layers of the P-type finfets of the different classes and with the same threshold voltage have different structural parameters;
in the fifth step, all the P-type finfets are simultaneously implemented by adopting the threshold voltage adjustment injection with the same parameters, and the difference of the threshold voltages of the various P-type finfets is adjusted by the difference of the structural parameters of the cap layer.
6. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in the first step, the semiconductor substrate comprises a silicon substrate.
7. The method of threshold voltage adjustment of a FinFET of claim 6, wherein: the isolation medium layer is made of an oxide layer.
8. The method of threshold voltage adjustment of a FinFET of claim 7, wherein: the isolation medium layer is formed by adopting an FCVD process.
9. The method of threshold voltage adjustment of a FinFET of claim 6, wherein: in step four, the structural parameters of the cap layer are adjusted by growing different material layers.
10. The method of threshold voltage adjustment of a FinFET of claim 9, wherein: the material of the cap layer comprises a soft material and a hard material, and the threshold voltage is adjusted by utilizing the characteristic that the ion blocking capability of the hard material for adjusting and injecting the threshold voltage is greater than the ion blocking capability of the soft material for adjusting and injecting the threshold voltage; the larger the number of impurities which are injected into the fin body after passing through the soft material and the larger the obtained threshold voltage is, the larger the thickness is, the larger the threshold voltage is.
11. The method of threshold voltage adjustment of a FinFET of claim 10, wherein: the soft material comprises an oxide layer formed by adopting an FCVD process, and the hard material comprises a silicon nitride layer.
12. The method of threshold voltage adjustment of a FinFET of claim 9 or 10, wherein: in the fourth step, the structural parameters of the cap layer are further adjusted by adjusting the thickness of the material layer; when the material of the material layer is the same, the thinner the material layer is, the greater the number of the impurities implanted into the top portion of the fin body after passing through the material layer and the greater the obtained threshold voltage is.
13. The method of threshold voltage adjustment of a FinFET of claim 9, wherein: the material layer of the cap layer comprises a plurality of material layers with different atomic sizes; the smaller the atomic size of the material layer is, the larger the number of the impurities implanted into the top portion of the fin body after passing through the material layer and the larger the obtained threshold voltage is.
14. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: and fifthly, after the step is finished, the step of removing the cap layer is further included.
15. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in the fifth step, the threshold voltage adjustment implantation adopts angled ion implantation.
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| US9524967B1 (en) * | 2016-01-12 | 2016-12-20 | United Microelectronics Corp. | Semiconductor device and method of forming the same |
| CN107437506A (en) * | 2016-05-27 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor structure |
| CN108122758A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109087887A (en) * | 2017-06-14 | 2018-12-25 | 中芯国际集成电路制造(北京)有限公司 | Semiconductor structure and forming method thereof |
| US20210119033A1 (en) * | 2019-10-18 | 2021-04-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor Device Structure Having a Plurality of Threshold Voltages and Method of Forming the Same |
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