CN104078427B - SRAM (Static Random Access Memory) and preparation method thereof - Google Patents
SRAM (Static Random Access Memory) and preparation method thereof Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- General Physics & Mathematics (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Health & Medical Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention relates to a SRAM (static random access memory) and a preparation method thereof. The preparation method comprises the following steps: providing a semiconductor substrate; carrying out halo/LDD (Lightly Doped Drain) ion injection to a PD(Pull down) on the semiconductor substrate; carrying out halo/LDD (Lightly Doped Drain) ion injection to a PU(Pull Up) on the semiconductor substrate; carrying out the halo/LDD ion injection to a PMOS (P-channel Metal Oxide Semiconductor) area of a core area on the semiconductor substrate; carrying out the halo/LDD ion injection to an NMOS (N-channel Metal Oxide Semiconductor) area of the core area on the semiconductor substrate; carrying out the halo/LDD ion injection to the PMOS area of an input/output area on the semiconductor substrate; and carrying out the halo/LDD ion injection to the NMOS area of the input/output area on the semiconductor substrate. A conventional ion injection sequence in the prior art is changed by adopting the method. After a grid electrode structure is formed, the SRAM repairs grid corrosion damage, and then, a PD (Pull Down) halo/LDD ion injection step is immediately executed. The PD receives the least photoresist ashing and wet method stripping technologies, PD threshold voltage mismatching reaches the minimum, and the yield of the SRAM can be effectively improved.
Description
Technical field
A kind of the present invention relates to semiconductor applications, in particular it relates to SRAM memory and preparation method thereof.
Background technology
SRAM (SRAM), as a member in volatile storage, has high speed, low-power consumption and standard
The advantages of technique is mutually compatible, is widely used in PC, personal communication, consumption electronic product (broadcast by smart card, digital camera, multimedia
Put device) etc. field.Particularly, high-speed synchronous SRAM are used for the application of the cache buffer memory devices such as work station, cache
For the data recycling or the storage instructing offer high speed.
In SRAM device design and production process, due to the uncertain, reason such as random error, gradient error, some set
But there is error, referred to as the mismatch process of semiconductor device after manufacture in the identical semiconductor device of timing（Mismatch
process）.Mismatch process becomes the restriction in generic analog signal processing procedure, especially in multiplexing analog systemss
（multiplexed analog systems）, digital analog converter（digital-to-analog converters）, ginseng
Examine source（reference sources）In.In digital circuit, the coupling of device is also critically important, for example, in stored digital
Read/write circuit, and the voltage range of SRAM cell.Enter one due to device size in MOS device
Step reduction and the reduction of available signal amplitude, described mismatch process（Mismatch process）Impact become particularly heavy
Will.
In technical elements, mismatch process（Mismatch process）With dimensions of semiconductor devices reduction increasingly
Many, about σ（Δ（P））=1/ area1/2, wherein σ represents standard deviation, Δ（P）Represent the difference of device property P.
Generally threshold voltage mismatch（Vt mismatch）Raising for SRAM yield is non-the normally off key, threshold voltage
Mismatch（Vt mismatch）It is normally defined σ (Δ (Vt))=1/ (W × L)1/2, usual supply voltage reduces relatively low to reach
Power consumption, the size of device is also less and less, the static noise surplus (statistic noise margin, SNM) of SRAM
Also become less, threshold voltage mismatch（Vt mismatch）SRAM is also become more and more important.
The LDD with certain angle would generally be executed in device fabrication process（Lightly dopeddrain）Ion is noted
Enter（halo/LDD）Step, the step of described halo/LDD needs to use photoresist, photoresist ashing and peel off in wet method
During can consume a part of oxide, it will cause the deviation of production technology, for example, make gate edge become coarse, source and drain
What in area, residual oxide became is coarse.More ashing and wet stripping techniques, can lead to more serious line edge roughness
（Line edge roughness LER）, same source-drain area residual oxide layer also becomes more coarse, and is executing LDD
Afterwards, described degree of roughness becomes even worse, and process deviation is bigger, the threshold voltage mismatch of device（Vt mismatch）Also become more
Plus serious, the static noise surplus (statistic noise margin, SNM) of SRAM also becomes less, yield to SRAM
Have a negative impact.In terms of improving SARM yield of devices, pull-down transistor（Pull Down, PD）Threshold voltage mismatch（Vt
mismatch）Become principal element.
At present, SRAM pull-down transistor（Pull Down, PD）LDD formed grid structure technique after, equally in PU
（Pull Up, PU）After LDD injection, thus result in the reduction of device performance, the performance of semiconductor device therefore to be provided,
The preparation technology of current device must be improved.
Content of the invention
Introduce a series of concept of reduced forms in Summary, this will specific embodiment partly in enter
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme required for protection
Key feature and essential features, more do not mean that the protection domain attempting to determine technical scheme required for protection.
The present invention is in order to overcome the problem of presently, there are, there is provided a kind of preparation method of SRAM memory, methods described bag
Include：
Semiconductor substrate is provided；
Halo/LDD ion implanting is carried out to the pull-down transistor in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to pulling up transistor in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the PMOS area of the core space in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the NMOS area of the core space in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the PMOS area of the I/O area in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the NMOS area of the I/O area in described Semiconductor substrate.
Preferably, methods described is further comprising the steps of before carrying out halo/LDD ion implanting to pull-down transistor：
Form grid structure on the semiconductor substrate, and the damage of described grid structure etching technics is repaired；
Skew side wall is formed on the side wall of described grid structure.
Preferably, methods described also includes the step forming source-drain area.
Preferably, methods described is additionally included in the step forming contact plug on described source-drain area, to form electrical connection.
Preferably, the PMOS transistor to described core space and nmos pass transistor carry out the suitable of halo/LDD ion implanting
Sequence is exchanged.
Preferably, the PMOS transistor to described I/O area and nmos pass transistor carry out halo/LDD ion implanting
Order exchange.
Preferably, the ion implanting that described halo/LDD ion implanting tilts for angle.
Preferably, the implant angle of described halo/LDD ion implanting is 5 °～45 °.
Preferably, described pull up transistor as PMOS transistor, described pull-down transistor is nmos pass transistor.
Present invention also offers the SRAM memory that a kind of said method prepares.
The method of the invention changes conventional ion injection order of the prior art, and SRAM device is forming grid structure
Afterwards, and gate etching process is damaged and repair, the step of execution PDhalo/LDD ion implanting is so that holding immediately after
During row PD halo/LDD, PD device experienced ashing and the wet stripping techniques of minimum photoresist, the technique of such gate lateral wall
The process deviation of deviation and PD device source-drain area residue oxide layer is all reduced to minimum, in halo/LDD ion implanting,
Introduce less Random Dopant Fluctuation（RDF）, PD threshold voltage mismatch reaches minimum, static noise surplus (statistic
Noise margin, SNM) maximum can also be reached, the yield of SRAM can be effectively improved.
Secondly, in methods described, the Halo/LDD ion implanting of described imput output circuit is placed on finally, due to input
The size of output area is larger, and its anti-mismatch capability is stronger.
Brief description
The drawings below of the present invention is used for understanding the present invention in this as the part of the present invention.Shown in the drawings of this
Bright embodiment and its description, for explaining assembly of the invention and principle.In the accompanying drawings,
Fig. 1 is the present invention to prepare the process chart of described SRAM memory in specific embodiment.
Specific embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And, it is obvious to the skilled person that the present invention can one or more of these details and be able to
Implement.In other examples, in order to avoid obscuring with the present invention, some technical characteristics well known in the art are not entered
Row description.
In order to thoroughly understand the present invention, detailed description will be proposed in following description, of the present invention to illustrate
SRAM memory and preparation method thereof.Obviously, the execution of the present invention is not limited to what the technical staff of semiconductor applications was familiar with
Specific details.Presently preferred embodiments of the present invention is described in detail as follows, but in addition to these describe in detail, the present invention can also have
There is other embodiment.
Should give it is noted that term used herein above is merely to describe specific embodiment, and be not intended to restricted root
Exemplary embodiment according to the present invention.As used herein, unless the context clearly indicates otherwise, otherwise singulative
It is intended to include plural form.Additionally, it should be understood that, when in this manual using term "comprising" and/or " inclusion "
When, it indicates there is described feature, entirety, step, operation, element and/or assembly, but does not preclude the presence or addition of one or many
Other features individual, entirety, step, operation, element, assembly and/or combinations thereof.
Now, it is more fully described the exemplary embodiment according to the present invention with reference to the accompanying drawings.However, these exemplary realities
Apply example to implement with many different forms, and should not be construed to be limited solely to the embodiments set forth herein.Should
Be understood by, these embodiments are provided so that disclosure of the invention is thoroughly and complete, and by these exemplary enforcements
The design of example is fully conveyed to those of ordinary skill in the art.In the accompanying drawings, for the sake of clarity, exaggerate the thickness in layer and region
Degree, and make to be presented with like reference characters identical element, thus description of them will be omitted.
Below the described SRAM memory and preparation method of embodiments of the invention is described further, provides first
Semiconductor substrate,
Specifically, described Semiconductor substrate can be at least one in the following material being previously mentioned：Silicon, silicon-on-insulator
（SOI）, silicon is laminated on insulator（SSOI）, SiGe is laminated on insulator（S-SiGeOI）And germanium on insulator SiClx
（SiGeOI）Deng.Could be formed with doped region and/or isolation structure in described substrate, described isolation structure be shallow trench every
From（STI）Structure or selective oxidation silicon（LOCOS）Isolation structure.
Include all permissible in core space and I/O area, wherein core space and I/O area in described Semiconductor substrate
Comprise various active devices, wherein following various operations, in the case of being not specific to, refer both to all areas for Semiconductor substrate
Domain.
As further, preferably, described substrate can comprise various active devices, and in the present invention specifically implements
Form the storage array comprising multiple memory element over the substrate, each memory element wherein said comprises at least in mode
One pull-down transistor（Pull down PMOS）, one pull up transistor（Pull up NMOS）And a transmission crystal
Pipe.Preferably, described pull-down transistor is PMOS transistor, described pull up transistor as nmos pass transistor.
The forming step forming described SRAM device is to form grid structure over the substrate first, the present invention's
In embodiment, described substrate can be Si substrate, and it is additionally may included in the SiO on Si2Boundary layer, by rapid thermal oxidation work
Skill（RTO）Or atom layer deposition process（ALD）To form SiO2Boundary layer, then forms gate material layers over the substrate,
In the present invention one is specifically preferably silicon or polysilicon layer in embodiment, preferably, shape on the semiconductor substrate
Become grid stack layer, includings the high k dielectric layer stacking gradually, TiN cover layer, polysilicon layer, and be located at described TiN cover layer with
Barrier layer between polysilicon layer.
Specifically, form gate dielectric over the substrate, described gate dielectric can be formed from hafnium,
It is used for example in HfO2Middle introduce the element such as Si, Al, N, La, Ta and optimize the ratio of each element the hafnium to obtain etc..Described
The method forming gate dielectric can be physical gas-phase deposition or atom layer deposition process.In embodiments of the invention
In, in described SiO2HfO2 gate dielectric is formed on boundary layer, its thickness is 15 to 60 angstroms.Afterwards, on gate dielectric
Form the TiN cover layer of gate stack structures, then deposit diffusion barriers in TiN layer, can be TaN layer or AlN layer.It
Deposition includes the gate material layers of polycrystalline silicon material on the diffusion barrier afterwards.
Etch described grid stack layer to form grid structure over the substrate.
Specifically, it is possible to use the SiO that photoetching process is formed to above step2Boundary layer, high k dielectric layer, TiN cover
Layer, polysilicon layer carry out patterned process, obtain described grid structure, the grid being formed has the structure of storehouse.Then, right
The etching technics of described grid structure damages and is repaired, inevitably to described grid during forming grid structure
The lattice structure of structure side wall damages, and affects device performance, for this reason, in the present invention specifically passes through in embodiment
High annealing, the method for rapid thermal oxidation are repaired to the surface of described grid structure, but restorative procedure is not limited to institute
Lift example, those skilled in the art can be selected according to degree of injury and reparation situation.
Then, carry out forming offset side wall（offset spacer）Step.The material of offset side wall can be nitridation
The insulant such as silicon, silicon oxide or silicon oxynitride.Offset side wall can improve the channel length of the transistor of formation, reduces short
Channelling effect and the hot carrier's effect being caused due to short-channel effect.
Next with grid structure as mask, to the described pull-down transistor in described SRAM device（Pull down, PD）
Carry out the LDD with certain angle（Lightly doped drain）Ion implanting（halo/LDD）；Specifically, with gate junction
Structure and skew side wall are mask, adopt ion on the basis of perpendicular to the vertical plane of semiconductor substrate surface, wide-angle tilt is noted
Enter mode and carry out halo/LDD ion implanting, to form unactivated first kind ion halo area, wide-angle tilt injection is permissible
Effectively prevent junction capacity and junction leakage that ion implanting causes, this unactivated first kind ion halo area can provide LDD to prolong
Stretch the diffusion zone of area's ion implanting, form ultra-shallow junctions.
In the present invention one specifically selects the method for halo LDD ion implanting and suitable selection in embodiment
The angle of injection, energy and dosage range, can reduce threshold drift with the junction capacity of optimised devices generation and junction leakage, therefore,
The impact to SCE, DIBL effect, junction capacity and junction leakage, threshold drift for the ion LDD/halo injection, preferably, described ion
The energy of injection is 2KeV～60KeV, preferably 5KeV～50KeV, and dosage is 1E12/cm2～5E13/cm2, preferably 1E13/
cm2～3E13/cm2, implant angle be 5 °～45 °, preferably 10 °～35 °.
As further preferably, the ionic type of described LDD injection is electrical according to the semiconductor device that will be formed
Determine, the foreign ion mixing in LDD injection technology is one of phosphorus, arsenic, antimony, bismuth or combination；Or injection impurity from
Son is boron.According to the concentration of required foreign ion, ion implantation technology can be completed with one or multi-step.
After executing described PD halo/LDD ion implanting, with grid structure as mask, pull up transistor to described（Pull
Up, PU）Carry out halo/LDD ion implanting.From ion on the basis of perpendicular to the vertical plane of semiconductor substrate surface, big angle
Degree tilts injection mode and carries out halo/LDD ion implanting, to form unactivated first kind ion halo area, wide-angle tilt
Injection can effectively prevent junction capacity and the junction leakage that ion implanting causes, and this unactivated first kind ion halo area can carry
For the diffusion zone of LDD extension area ion implanting, form ultra-shallow junctions.
In the one of present invention ion and the suitable selection injection specifically selecting halo/LDD injection in embodiment
Angle, energy and dosage range, the junction capacity that can be produced with optimised devices and junction leakage, reduce threshold drift, therefore, ion
The impact to SCE, DIBL effect, junction capacity and junction leakage, threshold drift for the halo/LDD injection, preferably, described ion implanting
Energy be 10KeV～40KeV, preferably 25KeV～30KeV, dosage be 1E13/cm2～5E13/cm2, preferably 3E13/
cm2～4E13/cm2, implant angle be 25 °～45 °, preferably 30 °～35 °.
The method of the invention changes conventional ion injection order of the prior art, and SRAM device is forming grid structure
Afterwards, it is immediately performed the step of PD halo/LDD ion implanting so that when executing PD halo/LDD, PD device experienced
The ashing of few photoresist and wet stripping techniques, the process deviation of such gate lateral wall and PD device source-drain area residue oxide layer
Process deviation be all reduced to minimum, in halo/LDD ion implanting, introduce less Random Dopant Fluctuation（RDF）, PD
Threshold voltage mismatch reaches minimum, and static noise surplus (statistic noise margin, SNM) can also reach maximum
Value, can effectively improve the yield of SRAM.
The method of the invention has prominent effect in terms of improving yield of devices.Will before LDD in prior art
After oxide layer on described source-drain area is removed, mismatch performance will not be improved, exacerbate the mismatch of device on the contrary, equally from chemistry
The method of rinse bath DNS cleaning is not also significantly improved to device mismatch performance.From the method for the invention, change
After halo/LDD ion implanting order, described device mismatch performance is improve 13%, even more high, therefore, side of the present invention
Method has prominent effect.
Preferably, in order to avoid the overlap in follow-up halo area and inclination are injected to LDD ultra-shallow junctions, gate dielectric layer and grid
After structural damage is it is preferred that form grid structure on a semiconductor substrate, then shape on the skew side wall of grid structure
Become clearance wall, then carry out subsequently every halo/LDD injection technology again.
Clearance wall is formed on the offset side wall that substrate and above-mentioned steps are formed（Spacer）, it is possible to use silicon nitride,
The material of carborundum, silicon oxynitride or a combination thereof.First silicon oxide layer, the first silicon nitride layer and can be deposited on substrate
Silicon dioxide layer, then adopts engraving method to form clearance wall, described clearance wall can have the thickness of 2-10nm.Then, use
Ion implantation technology or diffusion technique heavy doping source electrode and drain electrode（S/D）It is formed in the substrate of grid gap wall either side.Also
Annealing steps can be included, form the steps such as pouch-shaped injection region, NiSi deposition.
Then, in described device, the PMOS transistor of core space carries out halo/LDD ion implanting；To described core space
PMOS transistor carry out rake angle assisting ion halo/ with small angle inclination mode PMOS transistor in described core space
LDD injects, to form halo ion implanted region in PMOS transistor in described core space.For N-type semiconductor device, use
Group-III element carries out ion implanting, such as boron, boron difluoride and indium, ion implantation energy be 20-60keV, dosage be 5 ×
1012-6×1013Atom/cm3.For P-type semiconductor device, carry out example injection, such as phosphorus and arsenic, ion using V group element
Implantation Energy is 20-60keV, and dosage is 5 × 1012-6×1013Atom/cm3.For example can be with a vertical 20-70 degree
Angle carries out two sub-symmetry halo/LDD ion implantings to described device, forms halo ion implanting in the channel region both sides of substrate
Area.Halo/LDD ion implanted regions by the width of the opening being formed, the height of opening, the energy of ion implanting, injection angle
Degree and ion penetration side wall and dielectric layer ability determine.When the angle with vertical direction increases, halo ion implanted region will be from ditch
The both sides of raceway groove are shifted to, simultaneously the depth shallower of halo ion implanted region in the middle of road.So in specifically embodiment, according to control
Device short-channel effect processed needs, and designs energy and the angle of halo ion implanting.If carrying out two sub-symmetry halo ion notes
In entering, little with the angle of vertical direction, two in raceway groove halo ion implanted region is close to raceway groove centre in fact it could happen that weighing
Folded.The width of single halo ion implanted regions is generally less than 1.5 times of the width of opening.
Then, nmos pass transistor in described core space is carried out with ion LDD halo injection, described condition may be referred to
The LDD halo injection condition of PMOS transistor in above-mentioned core space, but also do not limit to and this condition.
As further preferred, device is annealed, to activate the impurity of halo ion implanted region.For example can adopt
With rapid thermal annealing, other annealing process can be adopted in other examples.If source-drain area and source and drain extension ginseng
Miscellaneous also do not activate, it is possible to use this step along band annealing, to reach activation purpose.According to embodiments of the invention, generally adopt
With spike annealing process, device is annealed, such as anneal between the temperature more than about 1000 DEG C is carried out 0.5 to 2 seconds.Institute
State annealing steps and can carry out it is also possible to laggard in all of halo ion implanting after every time having executed halo ion implanting
OK, not strict restriction.
In the present invention according to device mismatch performance need, in described core space PMOS transistor and core space NMOS
The halo/LDD ion implanting order of transistor can be exchanged, and reduces the adverse effect that mismatch is brought further, improves device
Energy.
Halo/LDD ion implanting is carried out to the I/O area of described semiconductor device, by described device in methods described
The halo/LDD ion implanting of I/O area is placed on finally, due to I/O area size is larger, can affect its mismatch
It is preferably minimized, as another embodiment of the present invention, according to device mismatch performance need, can also be to NMOS and PMOS
The order of the LDD ion implanting of I/O area be interchangeable.
The both sides of described transistor gate carry out source and drain injection, the present invention one specifically in embodiment using pre- non-
Crystallization doping (Pre-amorphization Implantation, PAI) and common ion injection (Co-implant), reduce note
Enter depth, suppression tunnel-effect (Channeling), reduce end-of-range (EOR) defect；Improve implantation dosage, reduce knot electricity
Resistance；Using high current, low-yield and angled ion injection, the diffusion of effective control doped chemical, improve source and drain extension
(SDE) steepness, using higher dosage halo structure, also can effectively suppress short-channel effect (SCE), the doping of rational halo area
Distribution can significantly improve small size device performance.The increase of halo implant angle, energy and dosage can improve the threshold value of device
Voltage and on-off ratio, reduce leakage current and threshold drift, and effectively suppression short-channel effect (SCE), the drain electrode of subthreshold behavior lures
Send out potential barrier and reduce effect (DIBL) effect.
In an embodiment of the present invention in order to improve the performance of device, can also comprise further to form the step of metal gates
Suddenly.
Specifically, remove the polysilicon layer in described grid structure, form groove.The method of described removal can be photoetching
And etching.In etching process, gas used includes HBr, and it is as main etch gas；Also include supplementing gas as etching
The O of body2Or Ar, it can improve the quality of etching.After this step, the final thickness of the TaN or AlN layer in PMOS exists
Between 10-30 angstrom.
Metal gates are formed on described barrier layer；
Specifically, the step carrying out formation PMOS metal gates.Described metal gates pass through to deposit multiple film stack shapes
Become.Described thin film includes workfunction layers, barrier layer and metallic aluminum material layer.Described barrier layer include TaN, TiN, TaC,
TaSiN, WN, TiAl, TiAlN or combinations of the above.Described deposition barrier layer process non-limiting examples include chemical vapor deposition
Area method (CVD), such as low temperature chemical vapor deposition (LTCVD), low-pressure chemical vapor deposition (LPCVD), fast thermal chemical vapor deposition
(LTCVD), plasma activated chemical vapour deposition (PECVD).
In one embodiment of the invention using ald（ALD）, the side of sputter and physical vapour deposition (PVD) (PVD)
Method, the thickness on the barrier layer being formed is between 10-100 angstrom.Described workfunction layers include one or more layers metal level.Institute
Stating metal level can be TiN, TaN, TiN and TaN, combinations of the above.The method that described metal level can use ALD, PVD or CVD
Formed.Preferably, the thickness of described workfunction layers is between 10-200 angstrom.
Described metallic aluminum material layer can be deposited with the method for CVD or PVD.After this conductive layer is formed,
Annealed under 300-500 degree celsius temperature.The time that it reacts in containing nitrogen environment is 10-60 minute.Finally carry out conduction
The planarization of layer, forms PMOS metal gates with the conductive layer removing beyond groove.
Etch described interlayer dielectric layer, form contact hole；Described contact hole is filled using conductive metal material, forms contact
Plug, to form electrical connection；
Specifically, described interlayer dielectric layer forms mask, be then etched, respectively in described NMOS and PMOS grid
Extremely upper formation contact hole, then fills conductive material in described contact hole, is finally planarized, formed on described grid
Contact plug, for electrically connecting.
Fig. 1 is the preparation method flow chart of the described SRAM memory of embodiments of the invention, including：
Step 201 provides Semiconductor substrate；
Step 202 carries out halo/LDD ion implanting to the pull-down transistor in described Semiconductor substrate；
Step 203 carries out halo/LDD ion implanting to pulling up transistor in described Semiconductor substrate；
Step 204 carries out halo/LDD ion implanting to the PMOS area of the core space in described Semiconductor substrate；
Step 205 carries out halo/LDD ion implanting to the NMOS area of the core space in described Semiconductor substrate；
Step 206 carries out halo/LDD ion implanting to the PMOS area of the I/O area in described Semiconductor substrate；
Step 207 carries out halo/LDD ion implanting to the NMOS area of the I/O area in described Semiconductor substrate.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and descriptive purpose, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member, it is understood that the invention is not limited in above-described embodiment, can also make more kinds of according to the teachings of the present invention
Variants and modifications, within these variants and modifications all fall within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (9)
1. a kind of preparation method of SRAM memory, methods described includes：
Semiconductor substrate is provided；
Execute following ion implanting step according to sequencing successively：Pull-down transistor in described Semiconductor substrate is carried out
Halo/LDD ion implanting；
Halo/LDD ion implanting is carried out to pulling up transistor in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the PMOS area of the core space in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the NMOS area of the core space in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the PMOS area of the I/O area in described Semiconductor substrate；
Halo/LDD ion implanting is carried out to the NMOS area of the I/O area in described Semiconductor substrate.
2. method according to claim 1 it is characterised in that methods described pull-down transistor is carried out halo/LDD from
Further comprising the steps of before son injection：
Form grid structure on the semiconductor substrate, and the damage of described grid structure etching technics is repaired；
Skew side wall is formed on the side wall of described grid structure.
3. method according to claim 1 is it is characterised in that methods described also includes the step forming source-drain area.
4. method according to claim 3 forms contact it is characterised in that methods described is additionally included on described source-drain area
The step of plug, to form electrical connection.
5. method according to claim 1 is it is characterised in that the PMOS transistor to described core space and nmos pass transistor
The order carrying out halo/LDD ion implanting is exchanged.
6. method according to claim 1 is it is characterised in that the PMOS transistor to described I/O area and NMOS are brilliant
The order that body pipe carries out halo/LDD ion implanting is exchanged.
7. method according to claim 1 is it is characterised in that described pull up transistor as PMOS transistor.
8. method according to claim 1 is it is characterised in that described pull-down transistor is nmos pass transistor.
9. the SRAM memory that the method as described in one of claim 1-8 prepares.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5872030A (en) * | 1997-10-27 | 1999-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving beta ratio in SRAM and device manufactured thereby |
| CN1244731A (en) * | 1998-08-11 | 2000-02-16 | 株式会社日立制作所 | Semiconductor integrated circuit and its producing method |
| TW459389B (en) * | 1997-11-22 | 2001-10-11 | United Microelectronics Corp | Manufacture method of SRAM |
| CN101055872A (en) * | 2006-04-10 | 2007-10-17 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its making method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5872030A (en) * | 1997-10-27 | 1999-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of improving beta ratio in SRAM and device manufactured thereby |
| TW459389B (en) * | 1997-11-22 | 2001-10-11 | United Microelectronics Corp | Manufacture method of SRAM |
| CN1244731A (en) * | 1998-08-11 | 2000-02-16 | 株式会社日立制作所 | Semiconductor integrated circuit and its producing method |
| CN101055872A (en) * | 2006-04-10 | 2007-10-17 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its making method |
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