：ϊ 3 8 1 933TWF.DOC/005 Α7 Β7 經濟部中央標準局員工消費合作社印裝 五、發明説明（f ) 本發明是有關於一種靜態隨機存取記憶體的製造方 法，且特別是有擺於一種使細胞具有低預備能量使用（L0W standby power usage)的靜態隨機存取記憶體製造方法。 爲了增加積體電路的效能並減少其製作成本，因此逐漸 降低積體電路的設計尺寸而增進元件的密度。近來的積體 電路記憶胞中，較廣爲人知的例如有DRAMs、SRAMs、 ROMs與EEPROMS等。積體電路記憶體中記憶胞密度的增 加，且伴隨著元件中單一儲存位元成本的降低。而藉著形 成較小的結構，或是元件或結構間較小的分隔距離更增加 元件的密度。通常，較小的設計規則需配合以佈局、設計 與結構上的修飾而形成縮減的元件尺寸，且縮小的元件必 須能維持一定的效能。例如，藉縮小設計尺寸而增加縮小 操作電壓的可能性，如縮小閘極氧化物層的厚度或增進微 影製程的容忍度。另一方面，因逐漸縮減的設計規則造成 較低的操作電壓，基本上限制了在高電壓操作下，小尺寸 元件中熱載子(Hot carrier)的效應。 另一因改變設計規則而影響的操作參數爲靜態隨機存 取記憶體（Static Random Access Memories, SRAM)中之能量 消耗。在SRAMs處於其預備（standby)的狀態時，通常需要 低能量消耗，例如，可攜帶式計算元件需要長時間的低能 量消耗以延長電池的使用時間。其他計算應用系統在某些 操作狀態下亦需要低能量的消耗，例如桌上型電腦在一段 時間未使用而進入”睡眠”的狀態時，即爲低能量的操作狀 態。而如上述的電腦，或至少是電腦的週邊，如數據機 3 本紙張尺度適用中國國家標隼（CNS ) A4規格（210X297公釐} ^^^1 11 n^— In ^^^1 nn i nn i— n^i、一SJ (讀先閲讀背面之注意Ϋ項再填寫本頁) A 今SsTWF.D。 DOC/005 A7 B7 經濟部中央標準局負工消費合作社印製 五、發明説明（>) (modem)，亦需要如上述電腦的操作狀態，而使電腦可以快 速地由其睡眠狀態進入正常操作的狀態。由於其它形式的 記憶體消耗太多能量（如DRAM)或不具合適的功能（如 EEPROMs, flash)，而爲維持一低能量消耗，因此使用SRAM 應用在電腦操作狀態的儲存係重要的。然當SRAM的密度 因縮減的設計規則而增加時，維持可接受的低能量消耗則 變得較爲困難。對於縮減的設計規則，SRAM中的元件變 得較小，而較小的元件使得每一記憶胞的電荷遺漏有增加 的趨勢。在高密度的SRAM設計中，由於設計規則的因素， 使得SRAM中記憶胞數增加而造成大量的記憶胞電荷遺 漏’致使上述遺漏的問題更形嚴重。而爲使高密度SRAMs 在低能量消耗的使用上能更加有用，因之減少SRAMs記憶 胞的電荷遺漏成爲一重要的課題。 典型的SRAM設計包括2個或4個以一鎖存配置（latch configuration)耦接在一起的MOS電晶體，而鎖存配置具有 2個與記憶胞資料儲存對應的電荷儲存狀態電荷儲存結 點° SRAM尙包括2個下拉電晶體(pull down transistor)與2 個負載元件(load device)，可以是複晶矽負載電阻或薄膜電 晶體(Thin Film Transistor)。每一電荷儲存結點爲一對應的 下拉電晶體與一對應的負載元件之一連接點，且每一電荷 儲存結點耦接至傳統鎖存配置下拉電晶體的閘極上。傳統 SRAM記憶胞資料的讀取以一非破壞性的方式選擇性耦接 每一電荷儲存結點與2條補償位元線之一者。選擇性耦接 藉由一對通道電晶體(pass transistor)而完成，單一通道電 曰曰 ^^1 · I. I it ^^1 ^ 1 - I I ^^1 H ^^1 ^IJ U3 ，\$ (請先閲讀背面之注意事項再填寫本頁) 本紙張尺度適用中關家梯李（CNS) A規^ (21GX297公疫 經濟部中央標準局員工消费合作社印聚 ^593¾9 1933TWF.DOC/005 A7 _______B7 _ 五、發明説明（4) 體與電荷儲存結點之一及對應的補償位元線連接。在資料 讀取操作時，將字元線的信號提供給通道電晶體而打開通 道電晶體。電荷流經打開的通道電晶體’或從電荷儲存結 點，而由字元線之一流出及流入其它字元線’字元線上電 壓的變化由一微分放大器（Differential amplifier)偵測而 得。對於SRAM記憶胞鎖存，在資料讀取操作中欲維持一 穩定的狀態，則必須以較電荷流入或流出對應位元線爲快 的速度流入或流出SRAM中至少一電荷儲存結點。而控制 部份是以形成一通道電晶體的通道’較長或較短於SRAM 中至少一下拉電晶體的通道而維持，其中，通道電晶體連 接至單一電荷儲存結點，而下拉電晶體具有一汲極且與單 一電荷儲存結點連接。對至少一 SRAM下拉電晶體與其對 應的通道電晶體而言’允許較多的電流流經下拉電晶體1 因此，電荷儲存結點電荷流入或流出的速度較對應位元線 電荷流入流出的速度爲快。 在SRAM未進行讀取與存寫操作而處於預備的狀態 時，電荷傾向於從電荷儲存結點遺漏的方式存在，而在最 後資料將從SRAM的記憶胞流失或致使部份記憶胞中的資 料模糊。因之’藉由設計SRAMs ’使電荷儲存結點因提供 給予電荷維持位準而解決上述的問題’較佳的是以一相當 於從電荷儲存結點電荷遺漏相當慢的平均速率進行。SRAM 記憶胞提供2個負載元件’其與一電荷儲存結，點連接並具 有高參考電壓《電流持續性或間歇地經由負載元件，而從 高參考電壓流向個別的電荷儲存結點’以取代從電荷儲存 5 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐） (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局員工消費合作社印裝 ，·Ά 193 3TWF.DOC/0 0 5 Α7 Β7 五、發明説明（/) 結點遺漏的電荷。不論是在操作或靜止的狀態，SRAM資 料儲存下負載元件的操作需要長時間消耗能1，因此，目 前的課題均嘗試降低高密度SRAMs中負載元件的能量消 '耗。例如Nishimura在美國專利號5,514,880中提出的， K Field Effect Thin-Film Transistor for an SRAM with Reduced Standby Curent”，即敘述了在使用一 SRAM 的負 載兀件中，以不同設計經由薄膜電晶體控制電荷的遺漏。 爲了降低能量消耗與提高SRAMs集積度的持續需求， 需要更進一步降低個別SRAMs記憶胞的能量損耗以完成 SRAM電路。 爲達上述之目的’本發明提供一種SRAM的製造方法， 其中SRAM記憶胞具有一高參考電壓接點，一低參考電壓 接點與一電荷儲存結點，並在電荷儲存結點與低參考電壓 接點間提供一下拉電晶體，而下拉電晶體之一源極與一汲 極分別和低參考電壓與電荷儲存結點連接，其中下拉電晶 體的汲極不具有含砷離子之一雜質。接著，在電荷儲存結 點與一位元線間提供一通道電晶體’最後在電荷儲存結點 與高參考電壓接點間提供一負載元件。 本發明另提供一種SRAM的製造方法，其至少具有複 數個SRAM記憶胞，且包括有複數個下拉電晶體與複數個 通道電晶體，SRAM製造方法至少包括下列步驟：首先在 一閘極氧化物層上形成一閘極’並自動對準閘極進行一第 一磷離子植入，再沿該閘極側邊形成一絕緣間隙壁，而自 動對準絕緣間隙壁進行一第二磷離子植入，藉此提供一 6 本紙張尺度適用中國目家_ ( CNS )八4减（21GX 297公釐） " ---------iM------訂-------W (請先閲讀背面之注意事項再填寫本1) L 933TWF.DOC/005 A7 B7 經濟部中央標率局貝工消費合作社印裝 五、發明説明（ir) LDD結構以形成一下拉電晶體之一源極與一汲極，而完成 下拉電晶體。其中下拉電晶體之一源極與一汲極分別和低 參考電壓與電荷儲存結點連接。接著，對下拉電晶體提供 一植入罩幕’暴露出下拉電晶體之該源極部份，且覆蓋住 至少下拉電晶體的汲極區部份，並對下拉電晶體之源極區 進行一砷離子植入。最後，在電荷儲存結點與一位元線間 提供一通道電晶體，並在電荷儲存結點與高參考電壓接觸 間提供一負載元件。 本發明再提供一種SRAM的製造方法，其至少具有複 數個SRAM記憶胞，且包括有複數個下拉電晶體與複數個 通道電晶體，SRAM的製造方法至少包括下列步驟：首先 提供一具有一源極與一汲極之一下拉電晶體，且下拉電晶 體之汲極基本上包括有磷離子之一雜質，而下拉電晶體之 源極具有一較下拉電晶體爲高的摻雜濃度。最後在電荷儲 存結點與一位元線間提供一通道電晶體，並在電荷儲存結 點與高參考電壓接觸間提供一負載元件。 爲讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂’下文特舉一較ft實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖係顯示根據本發明較佳實施例具有一 6個電晶體 SRAM記憶胞之電路圖。 第2圖係顯示根據本發明較佳實施例一保護SRAM週 邊電路的靜電放電（Electrostatic discharge, ESD)保護電 7 (請先聞讀背面之注意事項再填寫本頁) ，τ 3 本紙張尺度適用中國國家標準（CNS Μ4说格（2丨OX 297公釐） 1933TWF.DOC/005 A7 B7 經濟部中央標隼局負工消費合作社印装 五、發明説明（l) 路。 第3圖至第5圖係顯不根據本發明較佳實施例一 SRAM 不同部份之製造流程剖面圖。 第6圖係顯示根據本發明較佳實施例在一 SRAM記憶 胞2下拉電晶體間以植入法形成一共源極之剖面圖。 其中’各圖標號與構件名稱之關係如下： 實施例 本發明較佳實施例係提供一種SRAM記憶胞的製造方 法’其可降低能量的消耗並可增進資料穩定度與操作速率 的可靠度。根據本發明形成一 SRAM較佳實施例，形成一 SRAM的下拉電晶體’而下拉電晶體的汲極區毋須藉砷離 子或較重的N型雜質植入而形成。眾所皆知的是離子植入 基底的步驟會引發基底晶體晶格相當的損害，這是爲何在 習知積體電路製程中進行離子植入步驟後尙須進行一回火 (anneal)步驟的原因之一。一般相信回火步驟可以修復因離 子植入造成的晶格破壞，而回復晶體高度結晶的狀態。而 本發明人證實，在一 SRAM下拉電晶體中，進行砷離子之 離子植入形成源極區而對基底造成的破壞，無法完全地藉 回火基底的步驟而移除，反應出因砷離子植人而造成的破 壞相當地嚴重，而無法以回火步驟完全修復。亦有可能是 因容納大的砷原子，對傳統下拉電晶體的砷離子植入引起 缺陷而使晶格產生一應力，而其與非晶系源/汲極區相關的 遺漏爲不同的。 8 本紙張尺度適用中國國家標準（CNS ) A4規格（210 X 297公釐） m ^^^^1 ^^^^1 ^ufl« 1 >IA— «^6^ ^^^^1 ^^^^1 I nn ^^^^1 U3. Ί (讀先閱讀背面之注意事項再填寫本頁) 經濟部中央楯準局員工消費合作社印笨 4693¾9 1933TWF.DOC/005 A7 B7 五、發明説明（7) 無論如何，由於下拉電晶體的汲極係直接與SRAM記 憶胞個別的電荷儲存結點連接，而與砷離子植入下拉電晶 體源極相關的電荷遺漏將造成SRAM記憶胞不良的能量消 耗增加。而一般相信與使用砷離子植入，定義SRAM下拉 電晶體汲極相關的電荷遺漏，在使用大且較重的N型離 子，如銻離子Sb植入定義SRAM記憶胞下拉電晶體汲極 時，電荷遺漏的現象亦爲顯著的。本發明人發現是使用磷 離子植入而定義SRAM下拉電晶體的汲極時，可降低由電 荷儲存結點電荷遺漏的情況。因此，在部份的實施例中， 在下拉電晶體的汲極中特別限制磷離子的植入劑量小於的 l*10M/cm2，較佳的是在定義閘極時，形成一下拉電晶體的 淡濃度摻雜汲極(LDD)結構，對準閘極的邊緣進行一第一離 子對準，再於閘極側邊形成絕緣側牆間隙壁.，再對準側牆 間隙壁的邊緣進行一第二離子植入步驟。 使用磷離子作爲SRAM記憶胞下拉電晶體的汲極，會 降低下拉電晶體的驅動能力（driving capacity)。如上所述， 在調整下拉電晶體的操作特性以降低由電荷儲存結點的遺 漏時，使下拉電晶體或通道電晶體具有足夠的驅動能力確 保SRAM記憶胞的穩定度係重要的，上述的調節應用在通 道電晶體與下拉電晶體的特徵中。本發明之實施例係提供 一種增進下拉電晶體驅動能力的源極，而可部份調節因下 拉電晶體汲極結構降低之驅動能力，且藉提供一較高濃度 砷離子的摻雜而完成下拉電晶體的源極結構。在本發明較 佳實施例中，下拉電晶體的源極爲一砷離子之第三離孑植 9 本紙張尺度適用中國國家標準（CNS ) A4規格{ 210><297公釐） m m ^^1 ^^1 ^^1 —tr .^ϋ J3,-s (請先聞讀背面之注WtK項再填寫本頁) 經濟部中央標準扃負工消費合作社印裝 l 933TWF.IfpG：il)05 A 7 4 b ^ ~__B7__ 五、發明説明（孓） 入步驟，如上所述，本發明係對SRAM記憶胞提供了非對 稱性的下拉電晶體。 下拉電晶體應具有一高的驅動能力，在許多方面與 SRAM週邊電路的高驅動能力相似，特別是在SRAM的ESD 保護電路上。在形成本發明較佳實施例下拉電晶體源極的 同時，使用相同的植入步驟形成週邊電路ESD電路至少部 份的源/汲極區，而下拉電晶體可形成與週邊電路ESD保護 電晶體源/汲極區相似，且具有高驅動能力的源極。本發明 將以圖示詳述如下。 第1圖係說明一 SRAM記憶胞(具有6個電晶體)包括有 2個PMOS負載電晶體10、12與2個NMOS下拉電晶體14、 16連接而形成跨接反向器（cross-coupled inverter)。每一 PMOS負載電晶體10、12的閘極與一對應的NMOS下拉電 晶體14、16閘極連接。PM0S負載電晶體10、12的汲極則 與相對應的NM0S電晶體14、16汲極連接，而形成具有傳 統結構的反向器負載電晶體的源極與一高參考電壓相 接，通常爲V«，而下拉電晶體的源極與一低參考電壓連 接，通常爲Vss，其可以爲接地電壓。PM0S電晶體10與 NM0S電晶體14形成一反向器，而PM0S電晶體10與 NM0S電晶體14的閘極與其它反向器的電晶體12、16連 接。同樣地，PM0S電晶體12與NM0S電晶體16的閘極 使其它反向器與電晶體10、14的汲極連接。因此，顯現在 一第一反向器電晶體10、14(結點N1)汲極的電壓施加在一 第二反向器電晶體12、16的閘極上，而電荷使第二反向器 ^^^1· ^^^^1 ^^—^1 OJ (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家梯準（CNS ) A4規格（210 X 297公釐} A7 B7 Λ ·、:;Ί'3 i533TWF.DOC/005 '發明説明（7) 維持在一 “開”或“關，，的狀態。而邏輯上相反的電壓則顯 現在第二反向器電晶體Ϊ2、16(結點N2)的閘極與第一反向 锻電晶體1〇、14的閘極上，而維持第一反向器在補償“開” 或“關”的狀態。因此，上述SRAM記憶胞的鎖存具有2 撞檫定的狀態：第一狀態爲在電荷儲存結點N1上有一事先 定義的電壓，在電荷儲存結點N2上有一低電壓，第二狀態 爲在電荷儲存結點N1上有一低電壓，在電荷儲存結點N2 上有一事先定義的電壓。二進位的資料鎖存藉兩種狀態的 轉換而記錄，因之必須在電荷儲存結點與相關反向器的連 接閘極上儲存足夠的電荷，而明確地使反向器之一“打 而其它的反向器“關閉”，藉此保持記憶的狀態。當 維持SRAM記憶胞在其原始狀態時，SRAM記憶胞的穩定 度可藉由在電荷儲存結點電壓的微小變化而量化。 SRAM記憶胞的狀態，傳統上藉選擇性連接記憶胞的電 荷儲存結點N1、N2與一對補償的位元線(5L，亙)而讀取。 〜對通道電晶體18、20與電荷儲存結點Nl、N2及對應的 位元線(BL,亙)連接，在讀取操作進行前，位元線、BL 相同且爲高參考電壓與低參考電壓的中間値，--般爲 ，接著，在字元線WL上的信號使通道電晶體 爲“打開”的狀態。例如，在N1上施以一預先設定的電壓 Vcc，而N2施以一低電壓Vss。當通道電晶體〗8、20打開， 電荷將從結點N1經由通道電晶體18流向位元線BL，而在 結點N1的電荷開始流向位元線BL，並藉流經負載電晶體 1〇至結點N1而再補充。同時，電荷從位元線經過通道電 11 I- -- - 1^1 -I y 1^1 In ^^1 、\兵 (請先閱讀背面之注意事項再填寫本頁) 經濟部中央標隼局負工消費合作杜印製 本紙張尺度適用中國國家樣準（CNS ) A4说格（210 X 297公釐） 19S3TWF.DOC/005 A7 經濟部中央標隼局貝工消費合作杜印裝 ___....__B7 五、發明説明（/〇 ) 晶體20而流動至結點N2，並從結點N2再流經下拉電晶體 16。在較流經通道電晶體18更多的電流流經電晶體1〇時， 電荷開始由結點N1流出，在減小至一個程度後，可以開始 打開“關閉’’的下拉電晶體16。在較流經通道電晶體2〇更 多的電流流經電晶體I6時，電荷開始累積在結點N2，在 累積至一個程度後，可以開始打開“關閉”的下拉電晶體 10 ° 一般而言，在6個電晶體SRAM記憶胞，使用薄膜電 晶體(TFTs)作爲2個負載元件1〇、12。而上述之TFT SRAM 記憶胞配置與負載電晶體1〇、12的源極、汲極與通道區均 以複晶矽沈積在一絕緣材料上而形成，其中絕緣材料覆蓋 SRAM電路基底表面上的通道電晶體與下拉電晶體。而由 於TFT結構與SRAM佈局非相關本發明，因此在此不再多 加敘述，而增進記憶胞集積密度佈局與由TFT負載元件低 遺漏電荷的方法與構造，可參考Nishitmira等人在美國專利 第 5,514,880 號所發表的 “Field Effect Thin-Film Transistor for an SRAM with Reduced Standby Current” ，在 Nishimura 的專利中，係利用砷離子植入下拉電晶體的源/汲極區。 本發明係以一般的離子植入步驟，形成SRAM週邊電 路的一部分，同時形成下拉FETs的源極區。第2圖爲根據 本發明一 SRAM之一週邊電路。金屬焊墊22作爲SRAM的 輸入或輸出端與其它電路連接之用，例如，焊墊22可作爲 SRAM處理信號或從SRAM讀取資料之用。而一種或多種 不同的供應或參考電壓亦可以如第2圖所示，經由外接焊 {請先閱讀背面之注意事項再填寫本頁) 策 訂 本紙張尺度適用中國國家標準（CNS ) Α4規格U10X297公釐） A7 B7 1933TWF DQC/005 五、發明説明（// ) 批衣-- (請先閲讀背面之注意事項再填寫本I) 墊而提供給SRAM。而從焊墊的一延伸部份，如部份的剖 面圖所示，與一 ESD保護元件的一電晶體源極或汲極做接 觸，即如圖中SRAM的週邊電路24所示。上述的ESD保 護元件24爲一具有源/汲極區26、30與一複晶矽浮置閘極 28的浮置閘極電晶體。而源/汲極26、30具有一摻雜的輪 廓，其適合於一電晶體操作與驅動較大的電流之用。如上 之源/汲極區具有根據本發明形成的一 SRAM下拉電晶體之 特性。而受重視的是，週邊電路的其它元件最好是具有一 高電流、驅動能力。儘管如此，輸入/輸出（I/O)電路的驅動能 允不若符合ESD保護元件的源/汲極區特性般地符合所需 下拉電晶體源極。如上，較佳的是下拉電晶體的源極具有 與ESD保護電晶體相似的電流驅動特性。簡述如下，一 ESD 保護電路24之單一 NMOS電晶體，係與第2圖所示不同， 但一般可提供與其相同的功能，如第3圖所示。上述討論 的週邊元件電路通常滿足I/O的功能，包括SRAM的ESD 保護，這是較佳SRAM元件主要記憶胞陣列建立電晶體與 放大器之比較，而此處之電晶體爲記憶胞電晶體。 經濟部中央標率局員工消費合作社印製 第3圖顯示對應於下拉電晶體之一的2記憶胞電晶體 14 ' 18與第1圖所示之6T記憶胞通道電晶體之一。第3 圖所示爲週邊電路中ESD保護電路之一典型的NMOS電晶 體24，然第3圖所示之各種元件並非在一 SRAM實施例中 典型對準或配置方式。第3圖係顯示一 SRAM在閘極定義 與一第一源/汲極植入形成後，不同部份之一初期製程。 SRAM與場氧化元件隔離區32形成於一矽基底30上，其 本紙張尺度適用中國國家標準（CNS ) A4現格（210X297公釐） 1 933 TWF.DOC/005 Α7 Β7 五、發明説明（/y) 中場氧化元件隔離區32可以矽的局部氧化(LOCOS)技術形 成或是在基底蝕刻溝渠，並以化學氣相沈積法沈積氧化物 塡滿溝渠而形成之淺溝渠隔離元件作爲隔離結構，而淺溝 渠隔離結構尙須經一化學機械硏磨法而完成。在基底上形 成場隔離元件32後，在基底上形成一厚度約爲30-200A之 熱氧化物層，在萍份的實施例中，較佳是在週邊電路的元 件上成長一較厚的閘極氧化物層，特別是形成在需要高電 壓操作的週邊電路。 接著，在元件的基底上沈積一摻有雜質的複晶矽層，經 定義後形成適合不同種類電晶體的閘極42、52與62,而雖 然閘極結構的尺寸與結構相似，然實際上不同的電晶體具 有不同的電流驅動與操作需求，且具有其個別的特性而需 調整，以獲得SRAM所需的效能與穩定度。再請參照第3 圖，利用閘極42、52與62作爲一植入罩幕，以一淡濃度 與低能量的磷離子，進行淡摻雜區40、50與60的自動對 準植入步驟，以形成元件的源/汲極區。而根據本發明形成 LDD源/汲極區之離子摻雜濃度約爲l-3*10n/cm2，植入能 量約爲35KeV左右。下拉電晶體14包括形成在基底30上 的源/汲極區40，與形成在基底30閘極氧化物層上的閘極 42。通道電晶體18包括形成在基底30上的源/汲極區50， 與形成在閘極氧化物層上的閘極52。ESD保護電路電晶體 24包括一源/汲極區60與閘極.62。下拉電晶體 '通違電晶 體與ESD保護電路電晶體的閘極至少部份爲由摻有雜質的 複晶矽層形成。下拉電晶體、通道電晶體與ESD保護電路 本紙張尺度適用中國國家標率（CMS ) A4現格（210X297公釐） I- n H 1 I I n - I I I 丁 、T (請先閎讀背面之注意事項再填寫本頁) 經濟部中央標车局員工消费合作杜印裝 459389 五、發明説明（β) 電晶體42、52與62的閘極最低層可以爲單一摻有雜質的 複晶矽層形成，或是可以不同的導體層，包括矽鎢化物 (Tungsten silicide)或砂钽化物（Titanium silicide)形成下拉電 晶體、通道電晶體與ESD保護電路電晶體的閘極。 第4圖係顯示在下拉電晶體、通道電晶體與週邊電晶體 的閘極側邊形成絕緣間隙壁結構，絕緣間隙壁結構可由氧 化矽形成，對更小的設計規則而言，間隙壁結構材料可以 是氮化矽》在本實施例中，先沈積一厚度約爲1500-2500A 的CVD氧化物層，接著回鈾刻氧化物層，暴露出源/汲極 區，分別沿著閘極42、52與62而形成氧化物間隙壁結構 44、54與64。而回蝕刻氧化物層的步驟可利用一反應性離 子蝕刻或一氟化物蝕刻法進行，且氧化物間隙壁的厚度係 由氧化物層的沈積厚度所決定。 經濟部中央標隼局員工消費合作社印裝 H. - 1^1 : - m · -1 ^^1 ^^1 —I— I τ* 0¾-6 (請先閲讀背面之注意事項再填寫本貰) 在沿著閘極而形成絕緣間隙壁44、54與64後，在元件 上進行一第二磷離子植入步驟，而形成源/汲極區的重摻雜 區。而根據本發明形成第二離子摻雜濃度約爲1*1013-l*10M/cm2，植入能量約爲40KeV左右。進行植入的結果 爲，自動對準間隙壁而形成重濃度摻雜區，而提供下拉電 晶體14、通道電晶體18與ESD保護電路電晶體24源/汲 極區46、56與66的LDD結構。除了如圖所示的元件外， 另包括有SRAM週邊電路的I/O電路。此些週邊電路尙包 括有反向器與其它形式具有高電流驅動能力的緩衝電路。 而I/O可包括有，例如由PMOS與NMOS電晶體耦接組成 的CMOS反向器，或是僅以NMOS電晶體或與PMOS電晶 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐} 經濟部中央標準局貞工消費合作社印裝 :1^9 38 9 1933TWF.DOC/005 五、發明説明（，*/ ) 體結合的電路。一般而言，I/O電路的NM0S電晶體暴露 出二磷離子植入區後，接著，再進行更進一步的植入步驟’ 以完成I/O電路或其它週邊電路。如第4圖所示’對下拉 電晶體、通道電晶體8與ESD保護電路上提供一罩幕，再 對週邊電路NMOS電晶體之源/汲極區進行植入。而再進行 砷離子的植入步驟，其植入濃度約爲2*l〇15/cm2’植入能量 約爲55KeV左右。之後，再剝除罩幕層’並再提供一新 的罩幕層而完成定義ESD電路的步驟。 請參照第5圖，在SRAM上提供一 ESD罩幕8〇 ’而 如圖所示，ESD罩幕層覆蓋住全部的通道電晶體與下拉電 晶體的汲極區，因此下拉電晶體的汲極區不會接受到ESD 植入。而除了 ESD保護電路外的週邊電路，亦以ESD罩 幕覆蓋住，因此亦不會遭受ESD的植入。接著，對ESD 保護電路電晶體24的源/汲極區進行一 ESD植入，而下 拉電晶體的汲極47未接受植入。ESD植入的第一部分， 植入濃度約爲l*l〇15/cm2，植入能量約爲55KeV左右。最 後，對ESD保護電路電晶體的源/汲極區提供一硼離子植 入，形成一袋狀摻雜區68，對與下拉電晶體的源極提供 •一硼離子植入，亦形成一袋狀摻雜區49，其鄰接下拉電 晶體的通道。袋狀植入區係以一傾斜角度，約爲30。而植 入硼離子，較佳是以旋轉基底而進行，而植入濃度約爲 2-5*10i3/cm2，植入能量約爲60tCeV左右，袋狀摻雜區將 限制擊穿效應（punch through effect)，接著再剝除ESD罩 幕80。在所有的植入步驟完成後，再進行回火，例如在 本纸張尺度適用中國國家標準{ CNS )八4規格（210 X ：297公釐） (請先聞讀背面之注意事項再填寫本頁) 袈.: Ϊ 3 8 1 933TWF.DOC / 005 Α7 Β7 Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs 5. Description of the Invention (f) The present invention relates to a method for manufacturing a static random access memory, and in particular it has a pendulum The invention relates to a method for manufacturing static random access memory which enables cells to have low standby power usage. In order to increase the efficiency of integrated circuits and reduce their manufacturing costs, the design size of integrated circuits is gradually reduced to increase the density of components. Among recent integrated circuit memory cells, there are widely known, for example, DRAMs, SRAMs, ROMs, and EEPROMS. The density of memory cells in integrated circuit memory increases, and is accompanied by a reduction in the cost of a single storage bit in the device. By forming smaller structures or smaller separation distances between components or structures, the density of components is increased. Generally, smaller design rules need to be combined with layout, design, and structural modifications to form a reduced component size, and the reduced component must be able to maintain a certain performance. For example, reducing the design size increases the possibility of reducing the operating voltage, such as reducing the thickness of the gate oxide layer or improving the tolerance of the lithography process. On the other hand, the lower operating voltage due to the shrinking design rules basically limits the effect of hot carriers in small-sized components under high-voltage operation. Another operating parameter that is affected by changing design rules is the energy consumption in Static Random Access Memories (SRAM). When SRAMs are in their standby state, low energy consumption is usually required. For example, portable computing elements require long periods of low energy consumption to extend battery life. Other computing application systems also require low energy consumption in certain operating states. For example, a desktop computer enters a "sleep" state when it has not been used for a period of time, which is a low-energy operating state. And the computer as mentioned above, or at least the periphery of the computer, such as the modem. 3 This paper size applies to the Chinese National Standard (CNS) A4 specification (210X297 mm) ^^^ 1 11 n ^ — In ^^^ 1 nn i nn i— n ^ i, a SJ (read the note on the back first, then fill out this page) A Today SsTWF.D. DOC / 005 A7 B7 Printed by the Central Consumers Bureau of the Ministry of Economic Affairs and Consumer Cooperatives >) (modem), which also needs the computer's operating state as described above, so that the computer can quickly enter its normal operating state from its sleep state. Because other forms of memory consume too much energy (such as DRAM) or are not suitable Functions (such as EEPROMs, flash), and to maintain a low power consumption, it is important to use SRAM for computer operating state storage. However, when the density of SRAM is increased due to reduced design rules, maintain an acceptable low energy Consumption becomes more difficult. For reduced design rules, the components in the SRAM become smaller, and the smaller components tend to increase the charge leakage of each memory cell. In high-density SRAM designs, due to Factors of design rules This increases the number of memory cells in the SRAM and causes a large number of memory cell charges to be missed ', which makes the above-mentioned problem even more serious. To make high-density SRAMs more useful in the use of low energy consumption, thereby reducing the memory cells of the SRAMs. Charge leakage has become an important issue. A typical SRAM design includes two or four MOS transistors coupled together in a latch configuration, and the latch configuration has two corresponding to the memory cell data storage. Charge storage state charge storage node ° SRAM 尙 includes 2 pull down transistors and 2 load devices, which can be polycrystalline silicon load resistors or thin film transistors. Each The charge storage node is a connection point between a corresponding pull-down transistor and a corresponding load element, and each charge storage node is coupled to the gate of a conventional latch configuration pull-down transistor. Reading of traditional SRAM memory cell data Take a non-destructive way to selectively couple each charge storage node with one of the two compensation bit lines. The selective coupling is via a pair of channel transistors ( pass transistor), and a single pass is called ^^ 1 · I. I it ^^ 1 ^ 1-II ^^ 1 H ^^ 1 ^ IJ U3, \ $ (Please read the precautions on the back before filling in this (Page) This paper size is applicable to Zhongguanjiati Li (CNS) Regulation A (21GX297 Printed by the Consumers' Cooperatives of the Central Standards Bureau of the Ministry of Public Health and Economics of the People's Republic of China ^ 593¾9 1933TWF.DOC / 005 A7 _______B7 _ V. Description of the invention (4) One of the charge storage nodes is connected to the corresponding compensation bit line. During the data reading operation, the signal of the word line is provided to the channel transistor to turn on the channel transistor. The charge flows through the opened channel transistor 'or from the charge storage node, and the change in voltage flowing from one of the word lines to the other word line' is detected by a differential amplifier. For the SRAM memory cell latch, in order to maintain a stable state during the data reading operation, it must flow into or out of at least one charge storage node in the SRAM at a faster speed than the charge flows into or out of the corresponding bit line. The control part is maintained by forming a channel of a channel transistor 'longer or shorter than the channel of at least one pull-down transistor in the SRAM, wherein the channel transistor is connected to a single charge storage node, and the pull-down transistor has A drain is connected to a single charge storage node. For at least one SRAM pull-down transistor and its corresponding channel transistor, 'allow more current to flow through the pull-down transistor1. Therefore, the charge storage node charge flows in or out at a faster rate than the corresponding bit line charge flows in or out. fast. When the SRAM is in a prepared state without reading, storing, and writing, the charge tends to exist from the charge storage node. In the end, data will be lost from the SRAM memory cells or cause some of the data in the memory cells. blurry. Therefore, by designing the SRAMs, the charge storage nodes can solve the above-mentioned problems by providing a charge maintenance level. It is preferable to perform at an average rate that is relatively slow compared to the charge leakage from the charge storage nodes. The SRAM memory cell provides 2 load elements 'which are connected to a charge storage node, and have a high reference voltage, "Current flows continuously or intermittently through the load element, and flows from a high reference voltage to individual charge storage nodes' instead of from Charge storage 5 This paper is sized for China National Standard (CNS) A4 (210X297 mm) (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Central Standards Bureau of the Ministry of Economic Affairs, Ά 193 3TWF.DOC / 0 0 5 Α7 Β7 V. Description of the invention (/) Missing charge at the node. Regardless of whether it is in an operating or stationary state, the operation of load elements under SRAM data storage requires a long time to consume energy1. Therefore, current issues have tried to reduce the energy consumption of load elements in high-density SRAMs. For example, Nishimura proposed in U.S. Patent No. 5,514,880, "K Field Effect Thin-Film Transistor for an SRAM with Reduced Standby Curent", which describes the use of a SRAM load element to control the charge through thin-film transistors in different designs. Omissions. In order to reduce the energy consumption and increase the continuous demand of SRAMs integration, it is necessary to further reduce the energy loss of individual SRAMs memory cells to complete the SRAM circuit. In order to achieve the above-mentioned purpose, the present invention provides a method for manufacturing SRAM, wherein the SRAM memory cells It has a high reference voltage contact, a low reference voltage contact and a charge storage node, and a pull-down transistor is provided between the charge storage node and the low reference voltage contact, and one source of the pull-down transistor and one The drain is connected to the charge storage node with a low reference voltage, wherein the drain of the pull-down transistor does not have an impurity containing arsenic ions. Then, a channel transistor is provided between the charge storage node and a bit line. A load element is provided between the charge storage node and the high reference voltage contact. The invention also provides a SRAM The manufacturing method includes at least a plurality of SRAM memory cells, and includes a plurality of pull-down transistors and a plurality of channel transistors. The SRAM manufacturing method includes at least the following steps: first, a gate is formed on a gate oxide layer. And automatically align the gate for a first phosphorus ion implantation, and then form an insulation gap along the side of the gate, and automatically align the insulation gap for a second phosphorus ion implantation, thereby providing a 6 books Paper size is applicable to China Mujia _ (CNS) 8 4 minus (21GX 297 mm) " --------- iM ------ Order ------- W (Please read first Note on the back, please fill in this again. 1) L 933TWF.DOC / 005 A7 B7 Printed by the Shell Standard Consumer Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. 5. Description of the invention (ir) The LDD structure is used to form a source and a pull transistor. The drain electrode completes the pull-down transistor. One of the source of the pull-down transistor is connected to a drain with a low reference voltage and the charge storage node. Then, an implant mask is provided to the pull-down transistor to expose the pull-down transistor. The source portion of the crystal and covering at least the drain region of the transistor An arsenic ion implantation is performed on the source region of the pull-down transistor. Finally, a channel transistor is provided between the charge storage node and a bit line, and a charge transistor is provided between the charge storage node and the high reference voltage contact. Load element. The present invention further provides a method for manufacturing an SRAM, which has at least a plurality of SRAM memory cells and includes a plurality of pull-down transistors and a plurality of channel transistors. The method for manufacturing a SRAM includes at least the following steps: One of the source and the sink is a pull-down transistor, and the drain of the pull-down transistor basically includes an impurity of phosphorus ion, and the source of the pull-down transistor has a higher doping concentration than the pull-down transistor. Finally, a channel transistor is provided between the charge storage node and a bit line, and a load element is provided between the charge storage node and a high reference voltage contact. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a detailed description is given below with reference to the accompanying drawings, as follows: Brief description of the drawings: FIG. 1 It is a circuit diagram showing a six transistor SRAM memory cell according to a preferred embodiment of the present invention. Figure 2 shows an electrostatic discharge (ESD) protection circuit for protecting SRAM peripheral circuits according to a preferred embodiment of the present invention. 7 (Please read the precautions on the back before filling this page). Τ 3 This paper size is applicable Chinese National Standard (CNS M4 scale (2 丨 OX 297 mm) 1933TWF.DOC / 005 A7 B7 Printing by the Consumers ’Cooperative of the Central Bureau of Standards of the Ministry of Economic Affairs 5. Description of the invention (1) Road. Figures 3 to 5 The figure is a cross-sectional view showing the manufacturing process of different parts of a SRAM according to a preferred embodiment of the present invention. FIG. 6 shows a preferred embodiment of the present invention to form a total of the SRAM memory cell 2 by pulling down the transistors to form a total. A cross-sectional view of the source electrode, wherein the relationship between each icon number and the component name is as follows: Example The preferred embodiment of the present invention provides a method for manufacturing an SRAM memory cell, which can reduce energy consumption and improve data stability and operation. Rate reliability. According to the present invention, a SRAM is formed, and a pull-down transistor of the SRAM is formed. The drain region of the pull-down transistor does not need to be formed by implanting arsenic ions or heavier N-type impurities. It is well known that the step of ion implantation of the substrate will cause considerable damage to the crystal lattice of the substrate. This is why it is necessary to perform an annealing step after performing the ion implantation step in the conventional integrated circuit manufacturing process. One of the reasons. It is generally believed that the tempering step can repair the lattice damage caused by ion implantation and restore the highly crystalline state of the crystal. The inventors have confirmed that arsenic ion ion implantation is performed in a SRAM pull-down transistor The damage to the substrate caused by the formation of the source region cannot be completely removed by the step of tempering the substrate, reflecting that the damage caused by the implantation of arsenic ions is quite serious and cannot be completely repaired by the tempering step. There are also It may be due to containing large arsenic atoms that cause defects in the arsenic ion implantation of the conventional pull-down transistor, which causes a stress on the lattice, and its omissions related to the amorphous source / drain region are different. 8 papers The scale is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) m ^^^^ 1 ^^^^ 1 ^ ufl «1 > IA—« ^ 6 ^ ^^^^ 1 ^^^^ 1 I nn ^^^^ 1 U3. Ί (Read the precautions on the back before filling (Write this page) The Consumer Cooperative of the Central Economic and Technical Bureau of the Ministry of Economic Affairs, India Benben 4693¾9 1933TWF.DOC / 005 A7 B7 V. Description of Invention (7) In any case, because the drain of the pull-down transistor is directly stored with the individual charges of the SRAM memory cell The nodes are connected, and the leakage of the charge associated with the source of the arsenic ion implantation pull-down transistor will increase the energy consumption of the SRAM memory cell. It is generally believed that the charge associated with the use of arsenic ion implantation to define the drain of the SRAM pull-down transistor Missing, when using large and heavy N-type ions, such as antimony ion Sb implantation to define the SRAM memory cell pull-down transistor drain, the phenomenon of charge leakage is also significant. The inventors have found that when the drain of a SRAM pull-down transistor is defined using phosphorus ion implantation, the leakage of the charge from the charge storage node can be reduced. Therefore, in some embodiments, the implantation dose of phosphorus ions in the drain of the pull-down transistor is particularly limited to less than 1 * 10M / cm2. It is preferable to form a pull-transistor when defining the gate. The lightly doped drain (LDD) structure is aligned with the edge of the gate for a first ion alignment, and then an insulating sidewall spacer is formed on the side of the gate. The second ion implantation step. The use of phosphorus ions as the drain of the SRAM memory cell pull-down transistor will reduce the driving capacity of the pull-down transistor. As described above, when adjusting the operating characteristics of the pull-down transistor to reduce the omission from the charge storage node, it is important to make the pull-down transistor or the channel transistor have sufficient driving capability to ensure the stability of the SRAM memory cell. It is used in the characteristics of channel transistor and pull-down transistor. An embodiment of the present invention provides a source for improving the driving capability of a pull-down transistor, which can partially adjust the driving capability lowered by the structure of the drain of the pull-down transistor, and completes the pull-down by providing a higher concentration of arsenic ion doping. Source structure of transistor. In the preferred embodiment of the present invention, the source of the pull-down transistor is the third ion implantation of an arsenic ion. 9 The paper size is applicable to the Chinese National Standard (CNS) A4 specification {210 > < 297 mm) mm ^^ 1 ^^ 1 ^^ 1 —tr. ^ Ϋ J3, -s (please read the note WtK on the back before filling out this page) Printed by the Central Standard Ministry of Economic Affairs and Consumer Cooperatives l933TWF.IfpG: il) 05 A 7 4 b ^ ~ __B7__ V. Description of the invention (i) Steps, as mentioned above, the present invention provides an asymmetric pull-down transistor for the SRAM memory cell. The pull-down transistor should have a high driving capability, which is similar to the high driving capability of SRAM peripheral circuits in many aspects, especially on ESD protection circuits of SRAM. While forming the source of the pull-down transistor in the preferred embodiment of the present invention, at least part of the source / drain region of the peripheral circuit ESD circuit is formed using the same implantation step, and the pull-down transistor can form an ESD protection transistor with the peripheral circuit. Source / drain regions are similar and have high drive capability. The present invention will be described in detail with the drawings. Figure 1 illustrates a SRAM memory cell (with 6 transistors) including two PMOS load transistors 10, 12 and two NMOS pull-down transistors 14, 16 to form a cross-coupled inverter. ). The gate of each PMOS load transistor 10, 12 is connected to a corresponding NMOS pull-down transistor 14, 16 gate. The drains of the PM0S load transistors 10 and 12 are connected to the corresponding NM0S transistors 14 and 16 drains, and the source of the inverter load transistor with a conventional structure is connected to a high reference voltage, usually V «, and the source of the pull-down transistor is connected to a low reference voltage, usually Vss, which can be a ground voltage. The PMOS transistor 10 and the NMOS transistor 14 form an inverter, and the gates of the PMOS transistor 10 and the NMOS transistor 14 are connected to the transistors 12 and 16 of other inverters. Similarly, the gates of the PMOS transistor 12 and the NMOS transistor 16 connect other inverters to the drains of the transistors 10 and 14. Therefore, the voltage appearing at the drain of a first inverter transistor 10, 14 (node N1) is applied to the gate of a second inverter transistor 12, 16 and the charge causes the second inverter ^ ^^ 1 · ^^^^ 1 ^^ — ^ 1 OJ (Please read the notes on the back before filling this page) This paper size is applicable to China National Standards (CNS) A4 (210 X 297 mm) A7 B7 Λ ·,:; Ί'3 i533TWF.DOC / 005 'Explanation of the invention (7) Maintained in an "on" or "off," state, and a logically opposite voltage appears in the second inverter transistor Ϊ2 , The gate of 16 (node N2) and the gate of the first reverse forging transistor 10, 14 maintain the first inverter in the state of compensation "on" or "off". Therefore, the above SRAM memory The cell latch has 2 states: the first state is a pre-defined voltage at the charge storage node N1, the low voltage is at the charge storage node N2, and the second state is at the charge storage node N1. There is a low voltage on it, and a pre-defined voltage on the charge storage node N2. The binary data latch is recorded by the transition of the two states, so it must be Sufficient charge must be stored on the connection gate of the charge storage node and the relevant inverter, so that one of the inverters is "hit" and the other inverter is "turned off" to maintain the state of memory. When maintaining When the SRAM memory cell is in its original state, the stability of the SRAM memory cell can be quantified by a small change in the voltage of the charge storage node. The state of the SRAM memory cell is traditionally connected to the charge storage node N1 of the memory cell traditionally And N2 are read with a pair of compensated bit lines (5L, 亘). ~ The channel transistors 18, 20 are connected to the charge storage nodes Nl, N2 and the corresponding bit lines (BL, 亘), and are being read Before the fetch operation is performed, the bit line and BL are the same and are in the middle of the high reference voltage and the low reference voltage, which is generally, then, the signal on the word line WL causes the channel transistor to be “on”. For example, a predetermined voltage Vcc is applied to N1, and a low voltage Vss is applied to N2. When the channel transistor 8 and 20 are turned on, the charge will flow from the node N1 to the bit line BL via the channel transistor 18, And the charge at the node N1 starts to flow to the bit line BL, and then flows through Load the transistor 10 to node N1 and replenish it. At the same time, the charge passes from the bit line through the channel electricity 11 I---1 ^ 1 -I y 1 ^ 1 In ^^ 1, \ Bing (Please read the back first Please pay attention to this page, please fill in this page) The Ministry of Economic Affairs, Central Bureau of Standards, Off-line Work, Consumer Cooperation, Printed Paper Size Applicable to China National Standard (CNS) A4 (210 X 297 mm) 19S3TWF.DOC / 005 A7 Ministry of Economic Affairs The Central Bureau of Standards, Shellfisher, Consumer Cooperative, Du printed equipment ___....__ B7 V. Description of the invention (/ 〇) The crystal 20 flows to the node N2, and then flows from the node N2 to the pull-down transistor 16. When more current flows through the transistor 10 than through the channel transistor 18, the charge starts to flow from the node N1, and after reducing to a certain degree, the "closed" pull-down transistor 16 can be turned on. When more current flows through the transistor I6 than the channel transistor 20, the charge starts to accumulate at the node N2. After it has accumulated to a certain degree, the "closed" pull-down transistor can start to open 10 ° Generally speaking, In the six transistor SRAM memory cells, thin film transistors (TFTs) are used as the two load elements 10 and 12. The above-mentioned TFT SRAM memory cells are configured with the source, drain, and channel of the load transistors 10 and 12. The regions are all formed by depositing polycrystalline silicon on an insulating material, wherein the insulating material covers the channel transistor and the pull-down transistor on the surface of the SRAM circuit substrate. Since the TFT structure and the SRAM layout are not related to the present invention, they are not described here Add more narration, and the method and structure for improving the density of memory cell accumulation density and low leakage charge from TFT load elements can refer to the "Field Effect Thin-Film" published by Nishitmira et al. In US Patent No. 5,514,880. "Transistor for an SRAM with Reduced Standby Current", in Nishimura's patent, uses arsenic ions to implant the source / drain region of a pull-down transistor. The invention uses a general ion implantation step to form a part of the SRAM peripheral circuit. At the same time, the source region of the pull-down FETs is formed. Figure 2 is a peripheral circuit of a SRAM according to the present invention. The metal pad 22 is used as the input or output terminal of the SRAM to connect with other circuits. For example, the pad 22 can be processed as SRAM. Signal or read data from SRAM. And one or more different supply or reference voltage can also be connected by external welding as shown in Figure 2 (Please read the precautions on the back before filling this page) Applicable to China National Standard (CNS) A4 specification U10X297 mm) A7 B7 1933TWF DQC / 005 V. Description of the invention (//) Approval-(Please read the precautions on the back before filling in this I) Pad provided to SRAM. And from an extended part of the pad, as shown in a partial cross-sectional view, to make contact with a transistor source or drain of an ESD protection element, as shown in the peripheral circuit 24 of the SRAM. The ESD protection element 24 is a floating gate transistor having source / drain regions 26, 30 and a polycrystalline silicon floating gate 28. The source / drain 26, 30 has a doped profile, It is suitable for the operation of a transistor and driving a larger current. The source / drain region as described above has the characteristics of a SRAM pull-down transistor formed according to the present invention. It is important to note that other components of the peripheral circuit are best It has a high current and driving ability. Nevertheless, the drive capability of the input / output (I / O) circuit does not allow the source / drain region characteristics of the ESD protection element to match the required pull-down transistor source. As described above, it is preferable that the source of the pull-down transistor has a current driving characteristic similar to that of the ESD protection transistor. A brief description is as follows. A single NMOS transistor of an ESD protection circuit 24 is different from that shown in FIG. 2, but generally provides the same function as that shown in FIG. 3. The peripheral component circuits discussed above usually meet the I / O functions, including ESD protection of SRAM. This is a comparison between the transistor and amplifier of the main memory cell array of a better SRAM element, and the transistor here is a memory cell transistor. Printed by the Employees' Cooperative of the Central Standards Bureau of the Ministry of Economic Affairs. Figure 3 shows one of the 2 memory cell transistors 14'18 corresponding to one of the pull-down transistors and one of the 6T memory cell channel transistors shown in Figure 1. Figure 3 shows a typical NMOS transistor 24, which is one of the ESD protection circuits in the peripheral circuit. However, the various components shown in Figure 3 are not the typical alignment or configuration in an SRAM embodiment. Figure 3 shows an initial process of a SRAM after the gate definition and the formation of a first source / drain implant. The SRAM and field oxide element isolation area 32 is formed on a silicon substrate 30. The paper size is applicable to the Chinese National Standard (CNS) A4 (210X297 mm) 1 933 TWF.DOC / 005 Α7 Β7 5. Description of the invention (/ y) The mid-field oxidation element isolation region 32 can be formed by a local oxidation of silicon (LOCOS) technique or a trench is etched on the substrate, and a shallow trench isolation element formed by depositing oxide over the trench by chemical vapor deposition is used as an isolation structure. The shallow trench isolation structure must be completed by a chemical mechanical honing method. After the field isolation element 32 is formed on the substrate, a thermal oxide layer having a thickness of about 30-200 A is formed on the substrate. In the embodiment of the invention, it is preferable to grow a thicker gate on the components of the peripheral circuit. Electrode layers are formed especially in peripheral circuits that require high voltage operation. Next, a polycrystalline silicon layer doped with impurities is deposited on the substrate of the element, and gates 42, 52, and 62 suitable for different types of transistors are formed after being defined. Although the gate structure is similar in size and structure, it is actually Different transistors have different current drive and operation requirements, and have their own characteristics that need to be adjusted to obtain the performance and stability required by SRAM. Referring to FIG. 3 again, using the gate electrodes 42, 52, and 62 as an implant mask, the light-doped regions 40, 50, and 60 are automatically aligned and implanted with a light concentration and low energy phosphorus ions. To form the source / drain region of the element. The ion doping concentration of the LDD source / drain region formed according to the present invention is about 1-3 * 10n / cm2, and the implantation energy is about 35KeV. The pull-down transistor 14 includes a source / drain region 40 formed on the substrate 30, and a gate 42 formed on the gate oxide layer of the substrate 30. The channel transistor 18 includes a source / drain region 50 formed on a substrate 30 and a gate electrode 52 formed on a gate oxide layer. The ESD protection circuit transistor 24 includes a source / drain region 60 and a gate electrode 62. The pull-down transistor 'at least part of the gate of the transistor and the transistor of the ESD protection circuit is formed by a compound silicon layer doped with impurities. Pull-down transistor, channel transistor and ESD protection circuit This paper is applicable to China National Standard (CMS) A4 standard (210X297 mm) I- n H 1 II n-III D, T (Please read the notes on the back first Please fill in this page again) Consumption cooperation between employees of the Central Bureau of Standards and Vehicles of the Ministry of Economic Affairs, Du Duanqi 459389 V. Description of the invention (β) The lowest gates of transistors 42, 52 and 62 can be formed of a single compound silicon layer doped with impurities Or, different conductor layers, including Tungsten silicide or Titanium silicide, can be used to form the gate of the pull-down transistor, the channel transistor, and the ESD protection circuit transistor. Figure 4 shows the formation of an insulating spacer structure on the gate side of the pull-down transistor, the channel transistor, and the surrounding transistor. The insulating spacer structure can be formed of silicon oxide. For smaller design rules, the spacer structure material In this embodiment, a CVD oxide layer with a thickness of about 1500-2500A is deposited first, and then the oxide layer is etched back to expose the source / drain regions, which are respectively along the gates 42, 52 and 62 form oxide spacer structures 44, 54 and 64. The step of etching back the oxide layer can be performed by a reactive ion etching or a fluoride etching method, and the thickness of the oxide spacer is determined by the thickness of the oxide layer. Printed by the Consumer Cooperatives of the Central Bureau of Standards of the Ministry of Economic Affairs H.-1 ^ 1:-m · -1 ^^ 1 ^^ 1 —I— I τ * 0¾-6 (Please read the notes on the back before filling in this card After forming the insulating spacers 44, 54 and 64 along the gate, a second phosphorus ion implantation step is performed on the device to form a heavily doped region of the source / drain region. According to the present invention, the second ion doping concentration is about 1 * 1013-l * 10M / cm2, and the implantation energy is about 40KeV. As a result of the implantation, the gap wall is automatically aligned to form a heavily doped region, and a pull-down transistor 14, a channel transistor 18, and an ESD protection circuit transistor 24 source / drain regions 46, 56, and 66 LDD are provided. structure. In addition to the components shown in the figure, I / O circuits including SRAM peripheral circuits are also included. These peripheral circuits include inverters and other forms of buffer circuits with high current drive capability. The I / O can include, for example, a CMOS inverter composed of a PMOS and an NMOS transistor, or only a NMOS transistor or a PMOS transistor. The paper size applies the Chinese National Standard (CNS) A4 specification (210X297). Mm} Printed by Zhengong Consumer Cooperative, Central Bureau of Standards, Ministry of Economic Affairs: 1 ^ 9 38 9 1933TWF.DOC / 005 V. Description of the invention (, * /) integrated circuit. In general, the NM0S circuit of I / O circuit After the crystal is exposed to the diphosphorus ion implantation area, then further implantation steps are performed to complete the I / O circuit or other peripheral circuits. As shown in Fig. 4, the pull-down transistor, channel transistor 8 and A cover is provided on the ESD protection circuit, and then the source / drain region of the NMOS transistor in the peripheral circuit is implanted. After the arsenic ion implantation step is performed, the implantation concentration is about 2 * 1015 / cm2 ' The implantation energy is about 55KeV. After that, the mask layer is peeled off and a new mask layer is provided to complete the steps of defining the ESD circuit. Please refer to FIG. 5 to provide an ESD mask on the SRAM. 8 'And as shown in the figure, the ESD cover layer covers all channel transistors and pull-down transistors. The drain region, so the drain region of the pull-down transistor will not receive ESD implantation. The peripheral circuits other than the ESD protection circuit are also covered by the ESD cover, so they will not be subject to ESD implantation. Then, An ESD implant was performed on the source / drain region of the ESD protection circuit transistor 24, and the drain 47 of the pull-down transistor was not implanted. In the first part of the ESD implantation, the implantation concentration was about 1 * 10/15. cm2, the implantation energy is about 55KeV. Finally, a source / drain region of the ESD protection circuit transistor is provided with a boron ion implantation to form a pocket-shaped doped region 68 for the source of the pull-down transistor. A boron ion implantation also forms a pocket-shaped doped region 49, which is adjacent to the channel of the pull-down transistor. The pocket implantation region is at an inclined angle of about 30. For boron ion implantation, it is preferred to rotate Substrate, the implantation concentration is about 2-5 * 10i3 / cm2, the implantation energy is about 60tCeV, the bag-shaped doped region will limit the punch through effect, and then the ESD mask is stripped off 80 Tempering after all implantation steps are completed, such as applicable at this paper scale Chinese National Standard {CNS) 8 4 specifications (210 X: 297 mm) (Please read the precautions on the back before filling this page) 袈.
、1T A7 A7 1 933TWF.DOC/005 _____B7 五、發明说明（/f) —爐管回火溫度約爲800°C下進行20-30分鐘左右，或以 一快速熱回火製程’溫度約在l〇〇〇-ll〇〇t下進行1〇_6〇 秒鐘。 第6圖係顯示第5圖部份SRAM記憶胞陣列不同切面 之剖面圖。在實際的植入中，SRAM記憶胞的下拉電晶體 14、16係形成一共源極植入。如上，esd罩幕80同樣地亦 覆蓋在下拉電晶體14、16的汲極區47上，而暴露出共源 極，以提供週邊電路源極區48，較深的P型袋狀摻雜區中 砷離子植入源極區48。 更進一步的步驟包括，在第5圖的元件與負載元件上形 成一絕緣層’而繼續完成如第1圖所示之SRAM記憶體之 傳統技術可參照Nishimura的專利，在此不再多加敘述。 雖然本發明已以一較佳實施例揭露如上，然其並非用以 限定本發明’任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 —^---------裝— (請先閲讀背面之注意事項再填寫本頁) 經濟部中央標準局負工消費合作社印製 本紙張尺度適用中國國家標準{CNS) A4規格（2ί〇χ297公釐） Ϋ 經濟部中央標準局貝工消費合作社印製 i f年ί月i#日修正/•:^止·/·補光 (9 3'3TWFi .DOC/0 0 2 ί%ί·fl_ Β7.正θ銷 五、發明説明（/¾)符號說明 N1、 N2 ： 電荷儲存節點 10、 12 ： 負載電晶體 14、 16 ： 下拉電晶體 18、 20 ： 通道電晶體 22 ： 金屬焊墊 24 ： ESD 保護電路 26、 30 ： 源/汲極區、基底 32 ： 場氧化元件隔離區 40、 50 ' 60 :淡摻雜區 42 ' 52、 62 :閘極 44、 54、 64 :間隙壁結構 46 ' 56、 66 : LDD結構 47 ： 汲極 49、 68 ： 袋狀摻雜區 80 ： ESD 罩幕 48 ： 源極 區 (請先閱讀背面之注意事項再填寫本頁) -s 本紙張尺度適用中國國家標準（CNS ) A4規格（210X297公釐）、 1T A7 A7 1 933TWF.DOC / 005 _____B7 V. Description of the Invention (/ f)-The furnace tube tempering temperature is about 800 ° C for about 20-30 minutes, or in a rapid thermal tempering process, the temperature is about It is performed at 100-1000 seconds for 100-600 seconds. Fig. 6 is a sectional view showing different cut planes of a part of the SRAM memory cell array of Fig. 5. In actual implantation, the pull-down transistors 14 and 16 of the SRAM memory cell form a common source implant. As described above, the esd mask 80 also covers the drain regions 47 of the pull-down transistors 14 and 16 and exposes the common source to provide the peripheral circuit source region 48 and the deeper P-shaped doped region.中 Arsenic ions are implanted in the source region 48. A further step includes forming an insulating layer 'on the component and the load component of FIG. 5 and continuing to complete the conventional technology of the SRAM memory shown in FIG. 1 with reference to Nishimura's patent, which will not be described further here. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. 'Any person skilled in the art can make various modifications and decorations without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application. — ^ --------- 装 — (Please read the notes on the back before filling out this page) The paper standard printed by the Central Standards Bureau of the Ministry of Economic Affairs and Consumer Cooperatives is printed in accordance with the Chinese National Standard {CNS) A4 specifications ( 2ί〇χ297mm) 贝 Printed ifyear ί 月 i # 日 改 / •: ^ 止 · / · 补 光 (9 3'3TWFi .DOC / 0 0 2 ί% ί · Fl_ Β7. Positive θ pin 5. Description of the invention (/ ¾) Symbol description N1, N2: charge storage node 10, 12: load transistor 14, 16: pull-down transistor 18, 20: channel transistor 22: metal pad 24: ESD protection circuit 26, 30: source / drain region, substrate 32: field oxide element isolation region 40, 50 '60: lightly doped region 42' 52, 62: gate 44, 54, 64: spacer structure 46 '56, 66: LDD structure 47: Drain 49, 68: Bag-shaped doped region 80: ESD mask 48: Source region (please read the precautions on the back before filling this page) -s This paper size applies China National Standard (CNS) A4 specification (210X297 mm)