JPH11238810A - Forming method of gate oxide films with different thickness - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable adjusting thickness of gate oxide films in such a manner that performance of a circuit is maximized, by forming a damage layer by simple ion implantation. SOLUTION: An element isolation film 12 is formed on a semiconductor substrate 10 having a normal operating region and a high voltage operating region, and a photoresist film pattern 16 is so formed that the high voltage operating region 14 is exposed on the semiconductor substrate 10. Silicon 17 which is electrically inert atom to the semiconductor substrate formed of silicon is ion-implanted by using the photoresist film pattern 16 as a mask. The photoresist film pattern 16 is eliminated, and each gate oxide film is formed on each region. In this case, a gate oxide film of the high voltage operating region is made relatively thicker than that of the normal voltage operating region by forming a damage layer by ion implantation of silicon.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a gate oxide film having different thicknesses on a single semiconductor substrate.
The present invention relates to a method for manufacturing a semiconductor device forming an ide layer.

[0002]

2. Description of the Related Art As semiconductor elements are highly integrated and power consumption is increased, a chip is taken as a measure against this.
(Chip) Research on lowering the internal operating voltage (Vdd) has been actively pursued.

[0003] By lowering the chip internal operating voltage (Vdd), it is possible to prevent a decrease in the reliability of transistors and other elements due to a high voltage and a high electric field. The development of low voltage operation semiconductor devices is being accelerated.

[0004] DRAM (Dynamic Random)
Also, in the case of Access Memory, the internal operating voltage has been reduced to 2.0V level after the external power source has been reduced from 5.0V to 3.3V for the last 5 years.

[0005] In particular, in the case of a 1 Gbit (bit) DRAM, many companies expect 1.8 V operation.

[0006] However, although the operating voltage of the device has a great advantage as described above, the operating voltage can be reduced by using a MOS transistor.
(i.e., current driving capability). As a result, a reduction in the operation speed of the semiconductor element, which is regarded as the most important, is inevitably caused.

One method for solving this problem is to scale down a gate insulating film and a transistor.
down).

Although the scaling down of the gate insulating film has attracted attention as a method for realizing low voltage operation without lowering the operation speed, this method also has a problem in reliability. Especially,
The problem becomes very serious if the operating voltage is not reduced in the operation of a specific part of the device.

As an example where the operating voltage is not reduced,
First, when the external power is higher than the internal operating voltage, the external power should be applied to reduce the voltage to generate the internal operating voltage. The portion to which the external power is applied has a higher voltage than the inside.

Also, a high-voltage external signal is applied to the input / output terminal of the chip, and the internal signal must be boosted to a high voltage and output. Therefore, a high voltage is also applied to this portion.

Second, as in the case of a DRAM, a cell array is used.
(cell array) word line (word l)
Ine) The part related to the operation is read / write (read / w
In operation, in order to transmit the internal voltage as much as the internal voltage, a threshold voltage (threshold vol.
(Tage), a higher voltage is required. That is, the floating NODE during circuit operation
In order to apply a full operating voltage to the (floating node), a voltage higher than the operating voltage should be applied to the gate.

Third, non-volatile memory (Non Vola)
EEPROM that is a tile memory (NVM)
(Electrically Erasable Pr
ogrammable read only memo
ry), as in case (ry)
Even when data is written using (tunneling), a circuit operating at a high voltage is required.

For the reasons described above, if a region to which a high voltage is applied is required inside the chip, the thickness of the gate insulating film is limited to the portion to which the high voltage is applied in order to guarantee the reliability of the chip. A condition is required to ensure the reliability of the system. As a result, there is a problem that it is not possible to scale down the gate insulating film to maximize the performance of the circuit.

In order to solve the above-described problems, a method of forming gate insulating films having different thicknesses in one substrate is disclosed in Jeoping Lin, Tayuan H.
rien, "METHOD FOR FABRICAT
ING GATE OXIDE LAYERS OF
DIFFERENT THICKNESS "(US Pat.
P No. 5,502,009), 1996.

However, the method is complicated, for example, using a silicon nitride film as a mask to form different gate oxide films, and it is difficult to maintain the cleanness of the gate insulating film. There is a problem that is difficult to secure.

[0016]

SUMMARY OF THE INVENTION The present invention has been proposed in order to solve the above-mentioned various problems. It is an object of the present invention to form at least two or more gate oxide films having different thicknesses on a semiconductor substrate. It is an object of the present invention to provide a method of forming gate oxide films having different thicknesses through which the performance of a circuit can be maximized.

Another object of the present invention is to ion implant simple electrical inactive atoms.
Accordingly, it is an object of the present invention to provide a method of forming gate oxide films having different thicknesses, whereby the thickness of the gate oxide film can be adjusted.

[0018]

According to the present invention for achieving the above object, a method for forming gate oxide films having different thicknesses is provided on a semiconductor substrate having a first region and a second region. Forming an element isolation film by defining an active region and an inactive region; forming a photoresist film pattern so that the second region is exposed on the semiconductor substrate; and using the photoresist film pattern as a mask Implanting electrically inactive atoms into the second region,
Removing the photoresist film pattern and forming a gate oxide film in each of the first and second regions, wherein the gate oxide film in the second region is relatively thicker than the gate oxide film in the first region. It is formed.

In a preferred embodiment of the method, the first region is a normal voltage operation region and the second region is a high voltage operation region.

In a preferred embodiment of the method, the atoms are the same as the constituent atoms of the semiconductor substrate.

In a preferred embodiment of the method, the atoms are tetravalent.

In a preferred embodiment of the method, the atoms are silicon (Si).

In a preferred embodiment of the method, atoms are implanted at a dose of at least 1E13.

In a preferred embodiment of the method, the thickness of the gate oxide film in the second region varies depending on the type and dose of atoms, energy, and conditions for forming the gate oxide film.

According to the present invention to achieve the above object, a method for forming gate oxide films having different thicknesses is provided in a method for manufacturing a semiconductor device having gate oxide films having different thicknesses on one semiconductor substrate. Ion-implanting electrically inactive atoms into a part of a region of a semiconductor substrate where a gate oxide film is to be formed to form a damaged layer on the semiconductor substrate in the region; Forming,
Forming a gate oxide film on the semiconductor substrate in the gate oxide film forming region including the damaged layer, wherein the gate oxide film in the region having the damaged layer is relatively thicker than the gate oxide film in the region not having the damaged layer The formed region having a damaged layer also has a gate oxide film having a different thickness depending on the damaged layer forming conditions.

In a preferred embodiment of the method, the atoms are the same as the constituent atoms of the semiconductor substrate.

[0027] In a preferred embodiment of the method, the atoms are tetravalent atoms.

In a preferred embodiment of the method, the atoms are silicon (Si).

In a preferred embodiment of the method, atoms are implanted at a dose of at least 1E13.

In a preferred embodiment of the method, the conditions for forming the damaged layer include the type and dose of atoms, energy,
Further, conditions for forming a gate oxide film are included.

(Function) The method of forming gate oxide films having different thicknesses according to the present invention maximizes the performance of a circuit by forming gate oxide films having different thicknesses on a semiconductor substrate.

[0032]

Referring to FIGS. 2 and 3, a novel method for forming gate oxide films 20a and 20b having different thicknesses according to an embodiment of the present invention will be described.
normalvolume operation re
Gion) 13 and a high voltage operation region (high voltage)
An element isolation film 12 is formed on a semiconductor substrate 10 having a geo operation region 14. Then, a photoresist film pattern (photos) is formed so that the high voltage operation region 14 is exposed on the semiconductor substrate 10.
After forming an is layer pattern 16, silicon 17, which is an electrically inactive atom, is ion-implanted into the silicon semiconductor substrate 10 using the photoresist film pattern 16 as a mask. The photoresist film pattern 16 is removed, and gate oxide films 20a and 20b are formed in each region. At this time, the gate oxide film 20b in the high voltage operation region 14 is formed to be relatively thicker than the gate oxide film 20a in the normal voltage operation region 13 because a damage layer 18 is formed by ion implantation of silicon. According to such a semiconductor device manufacturing method, at least two or more gate oxide films 20a and 20b having different thicknesses are formed on one semiconductor substrate 10.
Can be formed, whereby the performance of the circuit can be maximized. In addition, the damage layer 1 by simple ion implantation
The formation of the gate oxide film 8 can adjust the thickness of the gate oxide film.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS.

FIGS. 1 to 5 are vertical sectional views sequentially showing a method of forming gate oxide films 20a and 20b having different thicknesses according to an embodiment of the present invention.

Referring to FIG. 1, a method of forming gate oxide films 20a and 20b having different thicknesses according to an embodiment of the present invention first defines an active region and a non-active region on a semiconductor substrate 10 by defining an element isolation film 12a. To form The element isolation film 12 is formed of a general LOCOS (LOCal Oxidation).
of Silicon) or STI (ShallowT)
(Rench Isolation) method.

The active region includes a normal voltage operation region 13;
High voltage operation area 14 such as DRAM cell array area
Having.

In FIG. 2, a photoresist film pattern 16 is formed so that the high-voltage operation region 14 is exposed.
Predetermined atoms 17 are ion-implanted using the photoresist film pattern 16 as a mask.

Then, a damaged layer 18 is formed on the surface of the semiconductor substrate 10 in the high voltage operation region 14.

The atoms 17 are electrically inactive, for example, the same tetravalent silicon as the constituent atoms of the semiconductor substrate 10.
(silicon) 17.

Therefore, the atoms 17 do not change the conductivity of the semiconductor substrate 10.

The atoms 17 are ion-implanted at a dose of 1E12 dose or more.

Referring to FIG. 3, after removing the photoresist film pattern 16, a sufficient cleaning process is performed using an HF base solution or the like so that contamination generated when the subsequent gate oxide films 20 a and 20 b are formed. To prevent

Subsequently, the gate oxide films 20a and 20b are provided in the normal voltage operation region 13 and the high voltage operation region 14, respectively.
To form

As a result, the gate oxide film 20b in the high voltage operation region 14 is formed relatively thicker than the gate oxide film 20a in the normal voltage operation region 13.

This is because, as is well known, in the case where there is ion implantation damage in a wafer, a development is used in which an oxide film is formed thicker.

Gate oxide film 20b in high voltage operation region 14
Can be variously changed depending on the type and dose of the atoms 17, the energy, and the conditions for forming the gate oxide film 20b.

Further, additional photolithography (photo
The thickness of the two types of gate oxide films 20a and 20b may be reduced by atomic ion implantation under other conditions (olithography) process and other conditions.
If necessary, a gate oxide film having other various thicknesses can be formed.

In FIG. 4, each gate oxide film 20a,
The conductive layers 21 and 22 for forming gate electrodes are formed on the semiconductor substrate 10 including Ob.

Finally, the gate electrode forming conductive layers 21 and 2
2 to form a gate electrode layer 23a, 23b
Is formed, a normal voltage operating element 24 and a high voltage operating element 25 having gate oxide films 20a and 20b having different thicknesses are formed as shown in FIG.

Thereafter, the element forming process is completed by using a normal MOS transistor manufacturing method.

[0051]

According to the present invention, at least two or more gate oxide films having different thicknesses can be formed on a single semiconductor substrate, thereby maximizing the performance of a circuit, and achieving a simple electric non-contact. There is an effect that the thickness of the gate oxide film can be adjusted by forming a damaged layer by ion implantation of active atoms.

[Brief description of the drawings]

FIG. 1 is a vertical sectional view illustrating a method of forming gate oxide films having different thicknesses according to an embodiment of the present invention.

FIG. 2 is a vertical cross-sectional view illustrating a method of forming gate oxide films having different thicknesses according to an embodiment of the present invention.

FIG. 3 is a vertical sectional view illustrating a method of forming gate oxide films having different thicknesses according to an embodiment of the present invention.

FIG. 4 is a vertical sectional view illustrating a method of forming gate oxide films having different thicknesses according to an embodiment of the present invention.

FIG. 5 is a vertical sectional view illustrating a method of forming gate oxide films having different thicknesses according to an embodiment of the present invention.

[Explanation of symbols]

 10: Semiconductor substrate 12: Device isolation film 13: Normal voltage operation region 14: High voltage operation region 16: Photoresist film pattern 17: Silicon 18: Damage layer 20a: Thin gate oxide film 20b: Thick gate oxide film 23: Gate electrode layer

Claims (13)

[Claims] Forming a device isolation layer on a semiconductor substrate having a first region and a second region so as to define an active region and an inactive region; and exposing the second region on the semiconductor substrate. Forming a photoresist film pattern as described above; ion-implanting electrically inactive atoms into the second region using the photoresist film pattern as a mask; Removing, and forming a gate oxide film on each of the first region and the second region, wherein the gate oxide film of the second region is formed thicker than the gate oxide film of the first region. For forming gate oxide films having different thicknesses. 2. The method as claimed in claim 1, wherein the first region is a normal voltage operation region, and the second region is a high voltage operation region. Method. 3. The method as claimed in claim 1, wherein the atoms are the same as the atoms constituting the semiconductor substrate. 4. The method of claim 1, wherein the atoms are tetravalent atoms. 5. The method according to claim 4, wherein the atoms are silicon. 6. The method of claim 1, wherein the atoms are implanted at a dose of 10 ¹³ cm ⁻² or more. 7. The gate oxide film according to claim 1, wherein the thickness of the gate oxide film in the second region varies depending on the type and dose of the atoms, energy, and conditions for forming the gate oxide film. A method for forming a gate oxide film having a thickness. 8. A method of manufacturing a semiconductor device having gate oxide films having different thicknesses on one semiconductor substrate, wherein a part of a region of the semiconductor substrate where the gate oxide film is formed is electrically inactive. Forming a damaged layer on the semiconductor substrate in the region by ion-implanting the atoms of the region, forming at least one damaged layer on the semiconductor substrate in the gate oxide film forming region including the damaged layer. Forming a gate oxide film in the region having the damaged layer relatively thicker than the gate oxide film in the region not having the damaged layer, and forming the gate oxide film in the region having the damaged layer. A method for forming gate oxide films having different thicknesses, wherein gate oxide films having different thicknesses are provided depending on layer formation conditions. 9. The method according to claim 8, wherein the atoms are the same as the constituent atoms of the semiconductor substrate. 10. The method of claim 8, wherein the atoms are tetravalent atoms. 11. The method as claimed in claim 10, wherein the atoms are silicon (Si). 12. The method of claim 8, wherein the atoms are implanted at a dose of 10 ¹³ cm ⁻² or more. 13. The method of claim 8, wherein the conditions for forming the damaged layer include the type and dose of the atoms, the energy, and the conditions for forming the gate oxide film. Method.