JP3193581B2 - 1-transistor 1-capacitor dynamic random access memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a highly integrated, low power consumption,
The present invention relates to a one-transistor, one-capacitor type dynamic random access memory for high-speed operation.

[0002]

2. Description of the Related Art High integration of dynamic random access memories (hereinafter referred to as DRAMs) has been remarkable, and in recent years, DRAMs having 64 Mbits integrated on one chip have been put into practical use. Such high integration has been largely due to remarkable progress in microfabrication technology, and in addition to the high performance of transistors based on scaling rules. DR as above
In AM, a gate oxide film serving as a gate insulating film of each transistor in a memory cell region, a peripheral circuit region, and an input / output circuit region is formed to have substantially the same thickness.

[0003]

In a DRAM where one bit is composed of one storage capacitor and one switching transistor, the leakage current of the switching transistor must be strictly suppressed. This is becoming more severe because the refresh time is doubled for each generation so that the busy rate is constant, and the refresh time tends to be longer for low power consumption. That's why. In order to suppress the leakage current of the switching transistor, it is necessary to improve the cut-off characteristics. For this purpose, measures have been taken to form a thinner gate oxide film. Further, in order to increase the driving power of the peripheral circuit transistor, a measure for forming a thinner gate oxide film has been taken.

On the other hand, in order to prevent a voltage drop during writing to a capacitor due to the threshold voltage of the transistor itself,
A method of increasing the voltage of a word line to a threshold voltage or higher has conventionally been adopted. However, in this method, there is a limit in reducing the thickness of the gate oxide film from the maximum electric field applied to the gate oxide film in terms of reliability. Recently, the region where the trade-off is established is disappearing, and it has become difficult to realize a high-density high-speed DRAM.

[0005]

SUMMARY OF THE INVENTION The present invention is directed to a one-transistor, one-capacitor type DRAM which has been made to solve the above-mentioned problems, and has a memory cell array in which a plurality of memory cells having cell transistors and capacitors are arranged. A one-transistor, one-capacitor dynamic random access memory including a peripheral circuit having a peripheral transistor for driving a memory cell, wherein a gate insulating film of the cell transistor is formed thicker than a gate insulating film of the peripheral transistor; The thickness Tox of the gate insulating film of the cell transistor is such that the margin coefficient is α, the threshold voltage of the cell transistor is Vt, the high-level voltage applied to the capacitor is Vcc, and the gate insulating film of the cell transistor has high reliability. If the maximum allowable electric field is Eoxmax, Tox (ΑVt + Vcc) / Eoxm
ax.

The above-mentioned one-transistor, one-capacitor type DR
In AM, since the gate insulating film of the cell transistor is formed thicker than the gate insulating film of the peripheral transistor, cut-off characteristics of the cell transistor and high-level write compensation are satisfied. At the same time, the gate insulating film of each transistor in the peripheral circuit region is formed thin, so that the driving power of each transistor is increased.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to FIG. In the figure, 1 transistor / 1 capacitor type DR
1 shows an example of the configuration of an AM.

As shown in FIG. 1, a DRAM 1 is a one-transistor / one-capacitor type, and a circuit for driving the memory cell array and a signal from the memory cell array are processed around a memory cell array block 11 serving as a memory cell area. A peripheral circuit block 12 serving as a peripheral circuit area including circuits to be implemented is arranged. Further, an I / O circuit block 13 serving as an input / output circuit area for exchanging signals with the outside is arranged in a state connected to the peripheral circuit block 12. The gate oxide film thickness (not shown) serving as the gate insulating film of the MOS transistor used in each of the blocks 11 and 12 is T _OXCELL and T _OXPERI , respectively.
Then, the relationship is set as shown in Expression (1).

[0009]

[ _Equation 1] T _OXCELL > T _OXPERI ... (1)

Next, a manufacturing method for realizing the DRAM 1 that satisfies the above-described relationship of the thickness of the gate oxide film will be described with reference to FIGS. 2A and 2B and FIGS. It will be explained by.

First, as shown in FIG.
A P-type semiconductor substrate (for example, a silicon substrate) 101 of about 0 Ωcm is prepared, and a field oxide film 102 is formed in a predetermined region on the front surface side of the semiconductor substrate 101 by, for example, a LOCOS method. Although not shown in the figure, CM
When configuring an OS transistor, a well region is formed in advance. Further, in order to prevent a soft error, a structure in which a double well is formed in the memory cell region may be adopted. Subsequently, in order to finish each threshold voltage of the N-channel transistor and the P-channel transistor to the set value, Vt control implantation is performed on the region where each N-channel transistor is to be formed and the region where the P-channel transistor is to be formed. Further, an oxide film 151 is formed in the active region to a thickness of, for example, about 4 nm by a thermal oxidation method.

Subsequently, as shown in FIG. 2B, a resist film is formed and patterned to form a resist pattern 152 covering the memory cell region 131. Using this resist pattern 152 as an etching mask, the oxide film 151 (portion indicated by a two-dot chain line) on the active region 132 other than the memory cell region is removed by etching with a dilute hydrofluoric acid aqueous solution.

Next, the resist pattern 152 is removed by a known resist removal technique. Thereafter, as shown in FIG. 2C, gate oxide films 103 and 104 are simultaneously formed by a thermal oxidation method. At this time, the thickness of the gate oxide film 104 other than the memory cell region 131 is set to 6 nm. In this case, since the oxide film 151 (see (2)) has been formed in the memory cell region 131 in advance, the thickness of the gate oxide film 103 is about 8 nm, which is thicker than the gate oxide film 104. In thermal oxidation of silicon, the reaction rate control and the diffusion rate control compete with each other, so that the total film thickness due to the two oxidations is not a simple arithmetic addition.

Subsequently, as shown in FIG.
A polycrystalline silicon film is deposited on the above structure by a method. And by lithography and etching
The polycrystalline silicon film is patterned to form a gate electrode 10
5 and the gate electrode 106 are formed. Thereafter, source / drain diffusion layers 107 and source / drain diffusion layers 108 are formed by ion implantation.

Next, a memory cell capacitor is formed on the above structure. As shown in FIG. 3A, first, for example, silicon oxide is deposited by a CVD method to form an interlayer insulating film 109, and then a predetermined position of the interlayer insulating film 109 [source / drain region] is formed by lithography and etching. 107a (107)], a contact hole 110 is opened. Then, after forming a polycrystalline silicon film by the CVD method, the polycrystalline silicon film is patterned by lithography and etching to form a lower electrode 111 of the capacitor. Further, a silicon nitride film and a polycrystalline silicon film are sequentially formed by a CVD method. Thereafter, the polycrystalline silicon film and the silicon nitride film are patterned by lithography and etching to form a capacitor dielectric thin film 112 with the silicon nitride film and an upper electrode 113 of the capacitor with the polycrystalline silicon film.

Next, an interlayer insulating film 114 for separating the capacitor and the bit line is formed by a CVD method, and the above-mentioned interlayer insulating film 1 is formed by lithography and etching.
14 at a predetermined position [source / drain region 107b (10
7) Open contact hole 115 above. Further, after forming, for example, a tungsten polycide film as a conductive material, patterning is performed by lithography and etching to form a bit line 116.

Subsequently, a metal wiring layer is further formed on the above structure. As shown in FIG. 3B, silicon oxide is deposited by a CVD method to form an interlayer insulating film 117, and a contact hole 118 is formed in a predetermined position (source / drain region 108) of the interlayer insulating film 117 by lithography and etching. Open on top). Thereafter, a conductive material such as tungsten polycide is buried as the plug 119. Then, an aluminum alloy is deposited by sputtering to form a metal layer. Then, the wiring layer 120 is formed by patterning the metal layer by lithography and etching. Finally, after the passivation film 121 is formed, a bonding pad portion (not shown) is opened to complete the wafer process.

Next, another method of manufacturing a gate oxide film will be described with reference to the manufacturing process diagram of FIG. In FIG. 4A, a field oxide film 102 is formed at a predetermined position on a semiconductor substrate 101. Thereafter, a structure after forming a gate oxide film 152 and patterning the gate electrode 106 of the transistor in the peripheral circuit region 132 is shown.

Subsequently, at least the gate oxide film 152 below the gate electrode 106 is left, and the memory cell region 1 is left.
The gate oxide film 152 on 31 is removed. Next, as shown in FIG. 4B, a new gate oxide film 103 is formed by a thermal oxidation method. At this time, the gate electrode 106
Since the gate oxide film 152 does not grow on the lower surface side of the substrate, its film thickness does not change. In this thermal oxidation, the active region of the peripheral circuit region 132 is also oxidized, and when the gate electrode 106 is made of polycrystalline silicon, its surface is also oxidized. Then, the gate electrode 105 in the memory cell region 131 is patterned on the gate oxide film 103. In this manner, two types of gate oxide films 152 and 103 having different film thicknesses can be formed.

Next, the DR having the configuration described with reference to FIG.
The operation of AM1 will be described. Transistor in memory cell area of DRAM 1 (hereinafter referred to as memory cell transistor)
The important specifications required of the device include cut-off leak and high-level write compensation in a data retention state. Among them, the specification of the cut-off leak is derived by calculation of the allowable leak current. In order to prevent data destruction, the charge loss of the cell must be less than a certain ratio until the next refresh. Here, the capacitor capacity of the memory cell is Cs, and the high-level write voltage is Vs
Assuming that cc, the cell plate voltage is 1/2 Vcc, the allowable charge disappearance rate is η, and the refresh interval is T _REF , the allowable leak current I _LMAX ′ can be expressed by equation (2).

[0021]

## EQU2 ## I _LMAX '= [(1 / 2Vcc · Cs) / T _REF ] η (2)

Assuming a 256 Mbit class, a specific numerical value will be substituted. Cs = 25fF, Vcc = 1.5
V, η = 20%, 8 in consideration of low power mode
A double is set and T _REF = 1024 ms. Since the allowable leak I _LMAX ′ includes a leak component such as a capacitor and a junction leak, the allowable leak I of the transistor itself is included.
_LMAX is 0.37 assuming margin and 1/10 of the whole
fA. This value must be satisfied at the maximum operating temperature, for example 80 ° C. Here, punch-through should be particularly noted as the leak mode of the transistor. Another limitation that comes from high-level write compensation, which is another specification, is the withstand voltage of the gate oxide film of the transistor. For high-level write compensation, a method of bootstrapping a word line connected to a gate higher than Vcc and applying a high voltage has been widely used. The condition for high-level write compensation is (3)
It looks like an expression.

[0023]

## _EQU3 ## V _WL > Vcc + α · Vt (3)

Here, V _WL is the voltage at the time of writing to the word line, α is a margin coefficient in consideration of the word line delay, etc., depending on the circuit design. For example, a predetermined value in the range of about 1.1 to 1.5 Set to. Vt has a back bias of -V
This is the threshold voltage when cc + Vbb. This is because the source of the transistor is at Vcc during high level writing. Vbb is a substrate bias. If the maximum electric field applied to the gate oxide film is Eoxmax and the gate oxide film thickness is Tox, the above equation (3) is approximated as equation (4).

[0025]

Vt <(Eoxmax · Tox−Vcc) / α (4)

When equation (4) is further transformed, equation (5) is obtained.

[0027]

Tox> (αVt + Vcc) / Eoxmax (5)

The threshold voltage must be set high in order to suppress the leakage current of the transistor as described above. On the other hand, the threshold voltage must be set low for high-level write compensation. Must. In particular, since the thickness of the gate oxide film is becoming thinner, the limit from the maximum voltage applied to the gate oxide film is severe.

FIG. 5 is a graph showing the above relationship, in which the vertical axis shows the threshold voltage of the transistor and the horizontal axis shows the gate oxide film thickness. The intrinsic allowable maximum electric field applied to the gate oxide film is 10 MV / cm or more, but the allowable maximum electric field Eoxmax for practical long-term reliability due to imperfections of the gate oxide film is 3 MV / cm or more and 5 MV. / Cm or less. In the figure, Eoxmax
= 4.5 MV / cm. The solid line in the figure indicates the lower limit of the threshold voltage due to the limitation of the leak current. As the gate oxide film is made thinner, cutoff characteristics are improved, and the specification of leakage current can be achieved with a lower threshold voltage. On the other hand, the upper limit of the threshold voltage resulting from the high-level write compensation indicated by the dotted line in the figure is proportional to the gate oxide film thickness. The range where both trade-offs hold is
This is a region indicated by oblique lines in the figure. In this example, the thickness of the gate oxide film is reduced to about 6.5 nm, below which high-level write compensation cannot be performed. Therefore, the gate oxide film thickness of the memory cell transistor is set to about 8 nm, and the gate oxide film thickness of the transistor of the peripheral circuit block is set to about 6 nm, which is smaller than that.

As described above, by setting the gate oxide film thickness of the memory cell transistor to be larger than the gate oxide film thickness of the peripheral circuit block, the cutoff of the memory cell transistor and the high level write compensation can be satisfied, The driving force of each transistor in the circuit portion can be increased. Therefore, a DRAM device that can operate at high density and high speed can be realized.

Next, an embodiment of the second invention will be described with reference to the block diagram of FIG. As shown in the figure, the periphery of a memory cell array block (memory cell area) 21 of a 1-transistor / 1-capacitor type DRAM 2 includes a circuit for driving the memory cell array, a circuit for processing signals from the memory cell array, and the like. Circuit block (peripheral circuit area)
22 are arranged. Further, an I / O circuit block (input / output circuit area) 23 for exchanging signals with the outside is arranged so as to be connected to the peripheral circuits. Further, a voltage conversion circuit 24 for stepping down an external power supply is provided between the power supply and the I / O circuit block 23.

The voltage conversion circuit 24 operates an internal circuit composed of fine transistors at a low voltage to prevent a reduction in power consumption and a reduction in reliability due to hot carriers and the like. Interface with input and output voltages. Therefore, for example, when the external power supply voltage is 3.3 V, the voltage is reduced to 2.5 V to supply power to the internal circuit. By incorporating this voltage conversion circuit 24, a single power supply to the memory chip is required. Further, as a transistor of an internal peripheral circuit, a gate oxide film as thin as possible is used so that high-speed operation can be performed even at a low voltage. On the other hand, in the transistor of the I / O circuit, a gate oxide film thicker than the gate oxide film of the transistor in the peripheral circuit block is used so that sufficient reliability can be obtained even at a high external voltage. Therefore, when the gate oxide film thicknesses of the MOS transistors used in the memory cell region and the peripheral circuit region are T _OXCELL and T _OXPERI , respectively, the relationship is as shown in the above equation (1).

A method of manufacturing a DRAM by changing the thickness of a gate oxide film of a transistor so as to satisfy the above equation (1) is a process similar to that described with reference to FIGS. Therefore, the description is omitted here.

Next, the operation of the DRAM 2 will be described. In the same manner as in the embodiment of the first aspect of the invention, the allowable leak current of the specification of the cut-off leak required for the memory cell transistor of the DRAM 2 is expressed by the above-described equation (2). The allowable leakage current I of the transistor itself assuming a 256 Mbit class
_LMAX is, for example, I _LMAX = 0.37 fA. The above values must be satisfied at the maximum operating temperature, for example 80 ° C.

Another limitation resulting from high-level write compensation, which is another specification, is the withstand voltage of the gate oxide film of the transistor. For high-level write compensation, a method of bootstrapping a word line connected to a gate higher than Vcc and applying a high voltage has been widely used. The condition of the high-level write compensation is as shown in the above-described equation (3), and when it is modified, it becomes as in the above-mentioned equation (5).

There is a trade-off between the lower limit of the threshold voltage resulting from the limitation of the leak current of the memory cell transistor and the upper limit of the threshold voltage resulting from the high-level write compensation. Therefore, the lower limit of the reduction in the thickness of the gate oxide film is about 6.5 nm under the same conditions as described in the first embodiment of the present invention, below which high-level write compensation cannot be performed. Therefore, for example, the gate oxide film thickness of the memory cell transistor is set to about 8 nm, and the gate oxide film thickness of the transistor of the peripheral circuit block is set to about 6 nm, which is thinner.

As described above, the memory cell array block 2
By setting the gate oxide film thickness of one transistor to be larger than the gate oxide film thickness of the transistors of the peripheral circuit block 22, the cutoff of the memory cell transistor and the high level write compensation are satisfied. At the same time, the driving power of the transistors of the peripheral circuit block 22 is increased.

In the above description, the parameter setting at the 256 Mb DRAM level is used, but the present invention can be applied to other generations of DRAM devices. The form of the memory cell may be other than the stacked type described in the manufacturing method.

[0039]

As described above, according to the present invention,
Since the gate insulating film of the transistor in the memory cell region of the DRAM device is formed thicker than the gate insulating film of the transistor in the peripheral circuit region, cut-off leakage of the memory cell transistor and high-level write compensation can be satisfied, and the peripheral circuit can be satisfied. The driving force of the transistor in the region can be increased. Therefore, a DRAM device that can operate at high density and at high speed can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a DRAM according to an embodiment of the first invention.

FIG. 2 is a diagram (part 1) illustrating a process of manufacturing the DRAM of the first invention;

FIG. 3 is a diagram (part 2) illustrating a process of manufacturing the DRAM of the first invention;

FIG. 4 is another manufacturing process diagram of the gate oxide film.

FIG. 5 is a diagram showing a relationship between a threshold voltage and a gate oxide film thickness.

FIG. 6 is a configuration diagram of a DRAM according to an embodiment of the second invention.

[Explanation of symbols]

 1, 2 DRAM 11, 21 Memory cell array block 12, 22 Peripheral circuit block 13, 23 I / O circuit block 24 Voltage conversion circuit 103, 104, 152 Gate oxide film 131 Memory cell area

Continuation of the front page (56) References JP-A-55-83251 (JP, A) JP-A-2-237153 (JP, A) JP-A-4-165670 (JP, A) JP-A-54-58386 (JP) JP-A-2-21653 (JP, A) JP-A-5-6665 (JP, A) JP-A-5-259289 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB Name) H01L 27/108 H01L 21/8234 H01L 21/8242 H01L 27/088 H01L 29/78

Claims (2)

(57) [Claims] A memory cell array in which a plurality of memory cells each having a cell transistor and a capacitor are arranged;
A one-transistor, one-capacitor dynamic random access memory including a peripheral circuit having a peripheral transistor for driving the memory cell, wherein a gate insulating film of the cell transistor is formed thicker than a gate insulating film of the peripheral transistor; The thickness Tox of the gate insulating film of the cell transistor is such that the margin coefficient is α, the threshold voltage of the cell transistor is Vt, and the high level voltage applied to the capacitor is Vc.
c, If the maximum electric field that the gate insulating film of the cell transistor can tolerate in reliability is Eoxmax, Tox> (αVt +
Vcc) / Eoxmax A one-transistor, one-capacitor dynamic random access memory satisfying the relationship: Vcc) / Eoxmax. 2. The one-transistor, one-capacitor dynamic random access memory according to claim 1, further comprising a voltage conversion circuit for lowering an external power supply voltage.