JPH08204142A - Dynamic randon access memory - Google Patents

Abstract

PURPOSE: To realize a high density rapid DRAM by satisfying the high level write-in compensation and the cut off characteristics of transistor in the memory cell region of the DRAM as well as improving the drive force of a transistor in the peripheral circuit region. CONSTITUTION: Within a DRAM 1, the gate insulating film of a transistor of a memory cell array block 11 comprising a memory cell is formed thicker than the gate insulating film of respective transistors of the peripheral circuit block 12 (peripheral circuit region) and an I/O circuit block 13 (I/O circuit region). Besides, the gate insulating film of respective transistors in the memory cell region and the I/O circuit region are formed thicker than the gate insulating film of respective transistors excluding these gate insulating films.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to high integration, low power consumption,
CMIS (Complimentary Metal In) for high-speed operation
sulator Semiconductor) type dynamic random access memory device.

[0002]

2. Description of the Related Art The dynamic random access memory device (hereinafter referred to as DRAM) is highly integrated, and in recent years, a DRAM having 64 megabits integrated on one chip has been put into practical use. Such high integration is largely due to remarkable progress in fine processing technology, and in addition to high performance of transistors based on scaling rules. DR as above
In AM, the gate oxide film serving as the gate insulating film of each transistor in the memory cell region, the peripheral circuit region and the input / output circuit region is formed to have substantially the same thickness.

[0003]

In a DRAM in which one bit is composed of one storage capacitor and one switching transistor, the leakage current of the switching transistor must be strictly suppressed. This is becoming more severe due to the fact that the refresh time is doubled for each generation to keep the busy rate constant and that the refresh time tends to be longer due to lower power consumption. This is because. In order to suppress the leak current of the switching transistor, it is necessary to improve the cutoff characteristic, and therefore, a measure for forming a thinner gate oxide film is taken. Further, in order to increase the driving force of the peripheral circuit transistor, a measure for forming the gate oxide film thinner is taken. On the other hand, in order to prevent the voltage drop at the time of writing to the capacitor due to the threshold voltage of the transistor itself, the method of raising the voltage of the word line above the threshold voltage has been conventionally adopted. The maximum electric field applied to the upper gate oxide film also limits the thinning of the gate oxide film. Recently, the area where the trade-off is established is disappearing,
It has become difficult to realize a high-density and high-speed DRAM.

[0004]

SUMMARY OF THE INVENTION The present invention is a DRAM made to solve the above-mentioned problems.
The AM is formed by forming the gate insulating film of the transistor in the memory cell region to be thicker than the gate insulating film of the transistor other than the memory cell region. The D of the second invention
In the RAM, the gate insulating film of each transistor in the memory cell region and the input / output circuit region (hereinafter referred to as I / O circuit region) is thicker than the gate insulating film of each transistor other than the memory cell region and the I / O circuit region. It was formed.

[0005]

In the DRAM of the first invention, since the gate insulating film of the transistor in the memory cell region is formed thicker than the gate insulating film of the transistor other than the memory cell region, the cutoff characteristic of the transistor in the memory cell region is formed. And high level write compensation is satisfied. At the same time, since the gate insulating film of each transistor in the peripheral circuit region and the I / O circuit region is thinly formed, the driving force of each transistor is increased.

In the DRAM of the second invention, the gate insulating film of the transistor in the memory cell region and the I / O circuit region is formed thicker than the gate insulating film of the transistor other than the memory cell region and the I / O circuit region. Therefore, the cut-off characteristic of the transistor in the memory cell region and the high-level write compensation are satisfied. At the same time, since the gate insulating film of the transistor in the peripheral circuit portion is formed thin, the driving force of this transistor is increased. .

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the first invention will be described with reference to the block diagram of FIG. In the figure, 1 transistor / 1 capacitor type DR
An example of the structure of AM is shown.

As shown in the figure, the DRAM 1 is of a one-transistor / one-capacitor type, and a circuit for driving the memory cell array and a signal from the memory cell array are processed in the periphery of the memory cell array block 11 serving as a memory cell area. A peripheral circuit block 12 serving as a peripheral circuit region including a circuit to be operated is arranged. Further, an I / O circuit block 13 serving as an input / output circuit area for exchanging signals with the outside is arranged while being connected to the peripheral circuit block 12. The gate oxide film thickness (not shown) that becomes the gate insulating film of the MOS transistor used in each of the blocks 11 to 13 is T _OXCELL , T _OXPERI , and
If T _{OXI / O} , the relationship is set as shown in equation (1).

[0009]

[ _Equation 1] T _OXCELL > T _OXPERI = T _{OXI / O} (1)

Next, regarding the manufacturing method for realizing the DRAM 1 satisfying the above-mentioned relation of the thickness of the gate oxide film, the manufacturing process chart of FIG. 2 (No. 1) and the manufacturing process chart of FIG. 3 (No. 2). Explained by.

First, as shown in (1) of FIG.
A P-type semiconductor substrate (for example, a silicon substrate) 101 of about 0 Ωcm is prepared, and a field oxide film 102 is formed in a predetermined region on the front surface side of the semiconductor substrate 101 by, for example, the LOCOS method. Although not shown in the figure, CM
When configuring an OS transistor, a well region is formed in advance. Further, in order to prevent soft error, a double well may be formed in the memory cell region. Then, in order to finish each threshold voltage of the N-channel transistor and the P-channel transistor to the set value, Vt control implantation is performed on each N-channel transistor formation-scheduled region and each P-channel transistor formation-scheduled region. Further, an oxide film 151 is formed in the active region with a thickness of, for example, about 4 nm by a thermal oxidation method.

Subsequently, as shown in FIG. 2B, a resist film is formed and patterned, and a resist pattern 152 is formed so as to cover the memory cell region 131. Using this resist pattern 152 as an etching mask, the oxide film 151 (the portion indicated by the chain double-dashed line) on the active region 132 other than the memory cell region is removed by etching with a dilute hydrofluoric acid solution.

Next, the resist pattern 152 is removed by a known resist removing technique. After that, as shown in FIG. 2C, the gate oxide films 103 and 104 are simultaneously formed by a thermal oxidation method. At this time, the gate oxide film 104 other than the memory cell region 131 is set to 6 nm. In that case, since the oxide film 151 [see (2)] has been formed in advance in the memory cell region 131, the thickness of the gate oxide film 103 is about 8 nm, which is thicker than the gate oxide film 104. In thermal oxidation of silicon, the reaction rate control and the diffusion rate control compete with each other. Therefore, the total film thickness obtained by two oxidations is not a simple arithmetic addition.

Subsequently, as shown in (4) of FIG.
By the method, a polycrystalline silicon film is deposited on the above structure. And by lithography and etching,
The gate electrode 10 is formed by patterning the polycrystalline silicon film.
5 and the gate electrode 106 are formed. After that, a source / drain diffusion layer 107 and a source / drain diffusion layer 108 are formed by an ion implantation method.

Next, a memory cell capacitor is formed on the above structure. As shown in (1) of FIG. 3, first, for example, silicon oxide is deposited by a CVD method to form an interlayer insulating film 109, and then by lithography and etching, a predetermined position [source / drain region] of the interlayer insulating film 109 is formed. 107a (107) top], the contact hole 110 is opened. Then, after forming a polycrystalline silicon film by the CVD method, the polycrystalline silicon film is patterned by lithography and etching to form the lower electrode 111 of the capacitor. Further, a silicon nitride film and a polycrystalline silicon film are sequentially formed by the CVD method. Then, the polycrystalline silicon film and the silicon nitride film are patterned by lithography and etching to form the dielectric thin film 112 of the capacitor with the silicon nitride film and the upper electrode 113 of the capacitor with the polycrystalline silicon film.

Then, an interlayer insulating film 114 for separating the capacitor and the bit line is formed by the CVD method, and the interlayer insulating film 1 is formed by lithography and etching.
14 predetermined positions [source / drain regions 107b (10
7) Top] to form a contact hole 115. Furthermore, after forming, for example, a tungsten polycide film as a conductive material, patterning is performed by lithography and etching to form the bit line 116.

Subsequently, a metal wiring layer is further formed on the above structure. As shown in (6) of FIG. 3, silicon oxide is deposited by the CVD method to form an interlayer insulating film 117, and contact holes 118 are formed at predetermined positions (source / drain regions 108) in the interlayer insulating film 117 by lithography and etching. Open on top). After that, a conductive material such as tungsten polycide is embedded as the plug 119. Then, an aluminum alloy is deposited by sputtering to form a metal layer. Then, the metal layer is patterned by lithography and etching to form the wiring layer 120. Finally, after forming the passivation film 121, a pad portion for bonding (not shown) is opened and the wafer process is completed.

Next, another method for manufacturing the gate oxide film will be described with reference to the manufacturing process chart of FIG. In FIG. 4A, the field oxide film 102 is formed at a predetermined position on the semiconductor substrate 101. After that, the gate oxide film 152 is formed, and the gate electrode 106 of the transistor other than the memory cell region 131 is formed.
The structure after patterning is shown.

Subsequently, leaving at least the gate oxide film 152 below the gate electrode 106, the memory cell region 1 is formed.
The gate oxide film 152 on 31 is removed. Next, as shown in (2) of FIG. 4, a new gate oxide film 103 is formed by a thermal oxidation method. At this time, the gate electrode 106
Since the gate oxide film 152 on the lower surface side of the film does not grow, its film thickness does not change. Further, in this thermal oxidation, the active regions other than the memory cell region 131 are also oxidized,
When the gate electrode 106 is made of polycrystalline silicon, its surface is also oxidized. Then, the gate electrode 105 in the memory cell region 131 is patterned on the gate oxide film 103. In this way, two types of gate oxide films 152 and 103 having different film thicknesses can be formed.

Next, the DR having the configuration described with reference to FIG.
The operation of AM1 will be described. Memory cell area of DRAM1
Transistor (hereinafter referred to as memory cell transistor)
The important specifications required for
Cut-off leakage and high level write compensation
It Of these, the specifications for cutoff leak are
It is derived by the calculation of the peak current. To prevent data corruption
In order to prevent the charge loss of the cell before the next refresh,
Must be below a certain percentage. Where the memory cell
Capacitor capacity is Cs, high level write voltage is V
cc, cell plate voltage 1/2 Vcc, allowable charge dissipation rate
η, refresh interval is T _REFThen the allowable leakage voltage
Flow I_LMAX′ Can be expressed as in equation (2).

[0021]

[ _Equation 2] I _LMAX '= [(1/2 Vcc · Cs) / T _REF ] η (2)

Substituting a concrete numerical value on the assumption of 256 Mbit class. Cs = 25fF, Vcc = 1.5
V, η = 20%, normal 8 considering low power mode
Double the value to set T _REF = 1024 ms. This allowable leak I _LMAX 'includes leak components such as capacitors and junction leaks, so the allowable leak I of the transistor itself
_LMAX is 0.37 if a margin is set to 1/10 of the whole
It becomes fA. This value must be met at the maximum operating temperature, for example 80 ° C. Here, as the leak mode of the transistor, punch-through must be particularly noted. Another limitation that comes from high-level write compensation, which is another specification, is the breakdown voltage of the gate oxide film of the transistor. For high-level write compensation, a method of bootstrapping the word line connected to the gate to a voltage higher than Vcc to apply a high voltage has been widely used. The conditions for high-level write compensation are (3)
It looks like an expression.

[0023]

[Equation 3] V _WL > Vcc + α ・ Vt '(3)

Here, V _WL is a voltage at the time of writing the word line, α is a margin coefficient in consideration of word line delay and the like, which depends on the circuit design, but is, for example, a predetermined value in the range of about 1.1 to 1.5. Set to. Also, Vt 'has a back bias of -V.
This is the threshold voltage when cc + Vbb. This is because the source of the transistor is Vcc at the time of writing at high level. Vbb is the substrate bias. When the maximum electric field applied to the gate oxide film is Eoxmax and the gate oxide film pressure is Tox, the above equation (3) is approximated by equation (4).

[0025]

## EQU00004 ## Vt '<(Eoxmax.Tox-Vcc) /. Alpha .... (4)

When the equation (4) is further modified, the equation (5) is obtained.

[0027]

## EQU00005 ## Tox> (. Alpha.Vt '+ Vcc) / Eoxmax (5)

In order to suppress the leakage current of the transistor severely as described above, the threshold voltage must be set high. On the other hand, the threshold voltage must be set low for high level write compensation. I have to. In particular, since the gate oxide film thickness is getting thinner, there are severe restrictions on the maximum voltage that can be applied to the gate oxide film.

FIG. 5 is a graph showing the above relationship, where the vertical axis represents the threshold voltage of the transistor and the horizontal axis represents the gate oxide film thickness. The intrinsic maximum allowable electric field applied to the gate oxide film is 10 MV / cm or more, but the practical maximum allowable electric field Eoxmax in terms of long-term reliability due to imperfections of the gate oxide film is 3 MV / cm or more and 5 MV or more. / Cm or less. In the figure, Eoxmax
= 4.5 MV / cm. The solid line in the figure shows the lower limit of the threshold voltage due to the limitation of the leak current. As the gate oxide film is made thinner, the cutoff characteristic is improved and the leak current specification can be achieved at a lower threshold voltage. On the other hand, the upper limit of the threshold voltage resulting from the high level write compensation indicated by the dotted line in the figure is proportional to the gate oxide film thickness. The range where the trade-off between the two is
The area becomes the shaded area in the figure. In this example, the gate oxide film thickness is reduced to about 6.5 nm, and if it is less than that, high-level write compensation cannot be performed. Therefore, the gate oxide film thickness of the memory cell transistor is set to about 8 nm, and the gate oxide film thickness of the transistors of the peripheral circuit block and the I / O circuit block is set to about 6 nm, which is thinner than that.

As described above, by setting the gate oxide film thickness of the memory cell transistor to be thicker than the gate oxide film thickness of each transistor of the peripheral circuit block and the I / O circuit block, the cutoff of the memory cell transistor and the high level It is possible to satisfy the write compensation and increase the driving force of each transistor in the peripheral circuit section and the I / O circuit section. Therefore, it is possible to realize a DRAM device which can operate at high density and at high speed.

Next, an embodiment of the second invention will be described with reference to the block diagram of FIG. As shown in the figure, in the periphery of the memory cell array block (memory cell region) 21 of the one-transistor / one-capacitor type DRAM 2, a periphery including a circuit for driving the memory cell array, a circuit for processing signals from the memory cell array, and the like. Circuit block (peripheral circuit area)
22 are arranged. Further, an I / O circuit block (input / output circuit area) 23 for exchanging signals with the outside is arranged in a state of being connected to the peripheral circuits. Further, a voltage conversion circuit 24 for increasing the voltage of the external power supply is provided between the power supply and the I / O circuit block 23.

The voltage conversion circuit 24 operates an internal circuit composed of minute transistors at a low voltage to prevent low power consumption and decrease in reliability due to hot carriers, etc. Interface with the input and output voltage of. Therefore, for example, when the external power supply voltage is 3.3V, it is stepped down to 2.5V and power is supplied to the internal circuit. By incorporating this voltage conversion circuit 24, a single power supply to the memory chip is required. Further, the transistors of the internal peripheral circuits use the thinnest possible gate oxide film so that they can operate at high speed even at a low voltage. On the other hand, in the transistor of the I / O circuit, a gate oxide film thicker than the gate oxide film of the transistor in the peripheral circuit block is used so that sufficient reliability can be obtained even at a high external voltage. Therefore, the gate oxide film thicknesses of the MOS transistors used in the memory cell area, the peripheral circuit area, and the I / O circuit area are T _OXCELL and T
_{If OXPERI} and T _{OXI / O} , then the relationship is as shown in equation (6).

[0033]

[ _Equation 6] T _OXCELL = T _{OXI / O} > T _OXPERI (6)

Transistor is used to satisfy the above equation (6).
How to manufacture DRAM by changing the thickness of gate oxide film
The method is the same as that described with reference to FIGS.
Seth. Therefore, the description is omitted here.
The gate oxide film in the memory cell area and the I / O circuit area
If it is formed simultaneously with the gate oxide film of_OXCELL= T
_{OXI / O}Is satisfied.

Next, the operation of the DRAM 2 will be described. As with the first embodiment of the first invention, regarding the specification of the cut-off leak required for the memory cell transistor of the DRAM 2, the allowable leak current is expressed by the above-mentioned formula (2). The allowable leakage current I of the transistor itself assuming the 256 Mbit class
_LMAX becomes I _LMAX = 0.37fA as an example. This value must be met at the maximum operating temperature, for example 80 ° C.

Another limitation imposed by the high level write compensation, which is another specification, is the breakdown voltage of the gate oxide film of the transistor. For high level write compensation, a method of bootstrapping the word line connected to the gate to a voltage higher than Vcc to apply a high voltage has been widely used. The conditions for high-level write compensation are as shown in equation (3) above, and if they are modified, they become equation (5) above.

There is a trade-off relationship between the lower limit of the threshold voltage due to the limitation of the leak current of the memory cell transistor and the upper limit of the threshold voltage due to the high level write compensation. Therefore, the lower limit of thinning the gate oxide film thickness is about 6.5 nm under the same conditions as described in the first embodiment of the present invention, and high level write compensation cannot be performed below that. Therefore, for example, the gate oxide film thickness of the memory cell transistor is set to about 8 nm, and the gate oxide film thickness of the transistor of the peripheral circuit block is set to about 6 nm, which is thinner than that. Further, since the gate oxide film of the transistor of the I / O circuit block is applied with an external power supply voltage higher than that of the inside, it is set to about 8 nm which is the same as that of the memory cell transistor.

In this way, the memory cell array block 2
By setting the gate oxide film thickness of the transistor of No. 1 and the gate oxide film of the transistor of the I / O circuit block 23 to be thicker than the gate oxide film thickness of the transistor of the peripheral circuit block 22, the cutoff of the memory cell transistor and the high level Satisfies the writing compensation of. At the same time, the driving force of the transistors of the peripheral circuit block 22 is increased. In addition, a voltage conversion circuit 24 that steps down the external power supply
The reliability is also improved because the gate oxide film thickness of the transistor of the I / O circuit block 23 to which a high power supply voltage is applied without increasing the gate oxide film thickness is increased. Furthermore, since the transistors of the memory cell array block 21 and the transistors of the I / O circuit block 23 have the same gate oxide film, the increase in the number of steps can be minimized. Therefore, a DRAM device with high density and high speed operation can be realized.

In the above description, the 256 Mb DRAM level parameter setting is used, but the present invention can be applied to other generation DRAM devices. The memory cell may be of any type other than the stacked type described in the manufacturing method.

[0040]

As described above, according to the first invention, the gate insulating film of the transistor in the memory cell region of the DRAM device is formed thicker than the gate insulating film of the transistor in the region other than the memory cell region. It is possible to satisfy the cut-off leakage of the cell transistor and the high level write compensation, and to enhance the driving force of the transistor in the peripheral circuit region and the input / output circuit region. Therefore, D with high density and high speed operation
A RAM device can be realized.

According to the second invention, the gate insulating film of each transistor in the memory cell region and the input / output circuit region of the DRAM device is formed thicker than the gate insulating film of the transistor other than the memory cell region and the input / output circuit region. Therefore, it is possible to satisfy the cut-off leakage of the memory cell transistor and the high-level write compensation, and increase the driving force of the transistor in the peripheral circuit region. Therefore, it is possible to realize a DRAM device having a high density and capable of operating at high speed.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a DRAM according to an embodiment of the first invention.

FIG. 2 is a manufacturing process diagram (1) of the DRAM of the first invention.

FIG. 3 is a manufacturing process diagram (2) of the DRAM of the first invention.

FIG. 4 is another manufacturing process diagram of the gate oxide film.

FIG. 5 is a relationship diagram between a threshold voltage and a gate oxide film thickness.

FIG. 6 is a configuration diagram of a DRAM according to an embodiment of the second invention.

[Explanation of symbols]

 1, 2 DRAMs 11, 21 Memory cell array block 12, 22 Peripheral circuit block 13, 23 I / O circuit block 24 Voltage conversion circuit 103, 104, 152 Gate oxide film 131 Memory cell area

Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical display location H01L 27/088 29/78 7735-4M H01L 27/10 671 Z 29/78 301 G

Claims (5)

[Claims] 1. A dynamic random access memory device of one-transistor / one-capacitor type, wherein a gate insulating film of a transistor in a memory cell region is formed thicker than a gate insulating film of a transistor other than the memory cell region. Dynamic random access memory device. 2. The dynamic random access memory device according to claim 1, wherein the thickness Tox of the gate insulating film of the transistor in the memory cell region has a margin coefficient α related to the operation delay time,
The threshold voltage of the transistor is Vt ′, the high level voltage is Vcc, and the maximum electric field that the gate insulating film of the transistor can tolerate in terms of reliability is Eoxmax, and Tox> (αVt ′ +
A dynamic random access memory device characterized by satisfying a relationship of (Vcc) / Eoxmax. 3. A dynamic random access memory device of one-transistor / one-capacitor type, wherein the gate insulating film of each transistor in the memory cell region and the input / output circuit region is replaced by the gate of the transistor other than the memory cell region and the input / output circuit region. A dynamic random access memory device characterized by being formed thicker than an insulating film. 4. The dynamic random access memory device according to claim 3, wherein the gate insulating film thickness Tox of each transistor in the memory cell region and the input / output circuit region has a margin coefficient α related to an operation delay time, The threshold voltage is Vt ′, the high level voltage is Vcc, and the maximum electric field that the gate insulating film of the transistor can tolerate in terms of reliability is Eoxmax, which satisfies the relationship of Tox> (αVt ′ + Vcc) / Eoxmax. And a dynamic random access memory device. 5. The dynamic random access memory device according to claim 3 or 4, wherein a voltage conversion circuit for stepping down an external power supply voltage is incorporated.