CN108122758A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108122758A CN108122758A CN201611081261.6A CN201611081261A CN108122758A CN 108122758 A CN108122758 A CN 108122758A CN 201611081261 A CN201611081261 A CN 201611081261A CN 108122758 A CN108122758 A CN 108122758A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 77
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- 150000002500 ions Chemical class 0.000 claims abstract description 107
- 238000012545 processing Methods 0.000 claims abstract description 11
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- 238000005530 etching Methods 0.000 claims description 20
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 239000010703 silicon Substances 0.000 claims description 14
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 12
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 claims description 9
- 230000008569 process Effects 0.000 claims description 9
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 238000002156 mixing Methods 0.000 claims description 2
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- 238000007254 oxidation reaction Methods 0.000 claims 1
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- 238000010348 incorporation Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 238000002955 isolation Methods 0.000 description 16
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- 239000004020 conductor Substances 0.000 description 2
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- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention provides a kind of semiconductor structure and forming method thereof, and wherein method includes：Substrate is provided, the substrate includes first area and second area；Barrier layer is formed on the substrate of the first area and second area, the barrier layer thickness of the first area and the barrier layer thickness of the second area differ；It is formed after barrier layer, processing is doped to the substrate, the first doped region is formed in the substrate of first area, the second doped region is formed in the substrate of second area, first doped region is different from the doping concentration of the second doped region.During the barrier layer is formed, the thickness on the barrier layer can be adjusted according to the concentration of required incorporation Doped ions in substrate, so as to reduce the difficulty of ion doping, improvement forms semiconductor structure performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technology
With the rapid development of semiconductor fabrication, semiconductor devices is towards higher component density and higher collection
The direction of Cheng Du is developed.Transistor is just being widely used at present as most basic semiconductor devices, therefore with semiconductor device
The raising of the component density and integrated level of part, problem also generate therewith.
Ion doping is the basic technology to form semiconductor structure.However, different semiconductor devices are to ion doping technique
The ion concentration of middle doping have different requirement in addition with semiconductor device different piece to being adulterated in doping process
Ion concentration also has different requirements.Particularly by ion doping adjust transistor threshold voltage technique in, to from
The adjusting of sub- doping concentration is particularly important.
Threshold voltage is the critical nature of transistor., it is necessary to be adjusted to threshold voltage in the processing procedure for forming transistor
Section so that transistor has particular threshold voltage, can realize different functions.It is to adjust transistor that raceway groove, which is doped,
The major way of threshold voltage.
The raceway groove protrusion substrate surface of FinFET (fin formula field effect transistor) forms fin, and grid covers the top surface of fin
And side wall, so that inversion layer is formed on each side of raceway groove, it can be in the connecting and disconnecting of the both sides control circuit of circuit, Neng Gou great
Width improves circuit control, reduces leakage current.The mainly method by being doped to fin is adjusted to FinFET threshold voltages
It carries out.The threshold voltage of FinFET is had a major impact with the ion concentration of wall doping at the top of fin
However, existing ion doping technique is larger to the adjusting difficulty of Doped ions concentration, so that transistor threshold
The adjusting difficulty of voltage is larger, forms semiconductor structure poor-performing.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of semiconductor structure and forming method thereof, Doped ions concentration can be reduced
Adjusting difficulty, improvement form semiconductor structure performance.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, including：Substrate is provided, it is described
Substrate includes first area and second area；Form barrier layer on the substrate of the first area and second area, described
The barrier layer thickness in one region and the barrier layer thickness of the second area differ；It is formed after barrier layer, to the substrate
Processing is doped, the first doped region is formed in the substrate of first area, the second doping is formed in the substrate of second area
Area, first doped region are different from the doping concentration of the second doped region.
Optionally, the step of forming barrier layer includes：Initial resistance is formed on the substrate first area and second area
Barrier；Mask layer is formed on the second area initial resistance layer；It is mask to the initial resistance layer using the mask layer
It performs etching；After being performed etching to the initial resistance layer, the mask layer is removed.
Optionally, the step of doping treatment includes：Ion implanting is carried out to the substrate, is injected in the substrate
The Doped ions.
Optionally, the step of doping treatment includes：It is formed on the substrate exposed on the barrier layer and barrier layer
Doped layer has Doped ions in the doped layer；The doped layer is made annealing treatment, diffuses into the Doped ions
Enter the substrate；After the annealing, the doped layer is removed.
Optionally, the material on the barrier layer is silica, silicon nitride, silicon oxynitride, silicon, germanium, SiGe or silicon-carbon.
Optionally, the substrate includes substrate and the fin in the substrate, and the fin includes firstth area
Domain and second area, the first area are located at the top of the second area.
Optionally, the step of doping treatment includes：Ion implanting is carried out to the fin, is injected in the fin
The Doped ions.
Optionally, the step of doping treatment includes：The doped layer for covering the fin side wall and top is formed, it is described
There are Doped ions in doped layer；It is formed after the doped layer, the doped layer is made annealing treatment, expands Doped ions
It dissipates into the fin；After the annealing, the doped layer is removed.
Optionally, the material of the doped layer is the SiGe containing Doped ions, silicon nitride or carbon silicon.
Optionally, the step of forming the doped layer includes：The stressor layers for covering the fin side wall and top are formed, and
During the stressor layers are formed, the stressor layers are doped, form the doped layer.
Optionally, for the stressor layers for forming PMOS transistor, the lattice constant of the stressor layers is less than the fin
Lattice constant；Alternatively, the stressor layers, for forming NMOS transistor, the lattice constant of the stressor layers is more than the fin
Lattice constant.
Optionally, for the stressor layers for forming PMOS transistor, the material of the stressor layers is carbon silicon；It is alternatively, described
For stressor layers for forming NMOS transistor, the material of the stressor layers is SiGe.
Optionally, the thickness of the doped layer is 20nm~50nm.
Optionally, the step of forming the barrier layer includes：It is formed and covers the initial of the fin side wall and top surface
Barrier layer；Graph layer is formed in the initial resistance layer surface, the graph layer exposes at the top of the fin or sidewall surfaces
Initial resistance layer；The initial resistance layer is performed etching using the graph layer as mask；The initial resistance layer is carried out
After etching, the graph layer is removed.
Optionally, the thickness of the initial resistance layer is 0.5nm~5nm.
Optionally, the fin of the first area has a tip, and the barrier layer thickness of the first area is less than described the
The barrier layer thickness in two regions.
Optionally, the step of forming the barrier layer includes：Initial resistance is formed in the fin side wall and top surface
Layer；The initial resistance layer is performed etching, removes the initial resistance layer of the part or all of thickness of fin top surface.
Optionally, the technique performed etching to the initial resistance layer includes：Anisotropic dry etch process.
Optionally, after the doping treatment, further include：Remove the barrier layer.
Correspondingly, the present invention also provides a kind of semiconductor structure, including：Substrate, the substrate include first area and the
Two regions；Barrier layer on the substrate first area and second area, the barrier layer thickness of the first area and institute
The barrier layer thickness for stating second area differs；The first doped region in the substrate of first area, positioned at second area
The second doped region in substrate, first doped region are different from the doping concentration of the second doped region.
Compared with prior art, technical scheme has the following advantages：
In the forming method for the semiconductor structure that technical solution of the present invention provides, it is doped before processing, in the lining
Barrier layer is formed on bottom.Since the barrier layer thickness and the barrier layer thickness of the second area of the first area differ,
It, can be according to the doping concentration needed for first doped region and the second doped region to institute during the barrier layer is formed
The thickness for stating barrier layer is adjusted, so that the doping concentration of substrate meets the first area and second area institute shape simultaneously
Into the needs of semiconductor devices.Specifically, when the doping concentration of first doped layer is higher, it can be by reducing described
Barrier layer thickness on one area substrate so as to reduce barrier effect of the barrier layer to Doped ions, and then makes described first to mix
The doping concentration in miscellaneous area is higher；It, can be by serving as a contrast the second area when the doping concentration of second doped region is higher
Barrier layer on bottom has smaller thickness, so as to reduce barrier effect of the second area barrier layer to Doped ions, and then makes
Second doped region has higher doping concentration.
Further, the substrate includes fin, and the second area fin has tip, is formed after gate structure, institute
It is stronger to the control action at the tip to state gate structure, therefore, the tip makes the ditch at the top of the fin of formed transistor
Road is easier to open than the raceway groove of side wall.By the way that the barrier layer thickness at the top of the fin is made to be less than the fin sidewall surfaces
Barrier layer thickness so as to which the Doped ions concentration at the top of fin is made to be less than the Doped ions concentration of fin side wall, and then makes
Threshold voltage rise at the top of fin.To sum up, fin side wall and fin top can be made by adjusting the thickness on the barrier layer
Threshold voltage it is identical, so as to improve the performance of formed semiconductor structure.
Further, during forming the doped layer, the stressor layers can provide stress for fin, so as to for
The transistor formed provides corresponding channel stress, and then can increase the migration speed of carrier in formed transistor channel
Rate, therefore, the forming method can further improve formed semiconductor structure performance.Specifically, the semiconductor structure
For PMOS transistor when, the lattice constants of the stressor layers is less than the lattice constant of the fin, then the stressor layers are to described
At the top of fin and side wall applies tensile stress, so as to provide compression along the fin extending direction for the fin, so as to
The migration rate of the channel carrier of formed PMOS transistor can be increased；When the semiconductor structure is NMOS transistor,
The lattice constant of the stressor layers is more than the lattice constant of the fin, then the stressor layers are applied to fin top and side wall
Pressurize stress, so as to provide tensile stress along the fin extending direction for the fin, to be formed so as to increase
The migration rate of the channel carrier of PMOS transistor.It can be seen that the forming method can further improve to form half
Conductor structure performance.
Description of the drawings
Fig. 1 to Fig. 6 is the structure diagram of each step of one embodiment of forming method of the semiconductor structure of the present invention；
Fig. 7 to Figure 15 is the structure diagram of each step of another embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
The forming method of existing semiconductor structure there are problems, such as：The semiconductor structure performance formed compared with
Difference.
The reason for semiconductor structure poor-performing that a kind of forming method of semiconductor structure of analysis below is formed.
The forming method of semiconductor structure includes：Substrate is provided；Ion implanting is carried out to the substrate, in the substrate
Inject Doped ions；After ion implanting, gate structure is formed over the substrate.
Wherein, during ion implanting is carried out to substrate, often make the Doped ions concentration injected in substrate identical,
It is not easy to meet requirement of the different crystal pipe formed on substrate to different levels of doping.For example, the ion implanting is used to adjust
Section forms the threshold voltage of semiconductor structure.The substrate includes first area and second area, first area institute shape
Threshold voltage into transistor forms with the second area threshold voltage of transistor and differs.The ion implanting makes institute
It is identical with the Doped ions concentration adulterated in second area substrate to state first area, so that the threshold of first area and second area
Threshold voltage is identical, so as to be not easy to meet simultaneously first area and the requirement to threshold voltage of transistor that second area is formed.
In addition, if the substrate includes substrate and the fin in the substrate, since gate structure is to fin top
The control action of portion and side wall differs, and is easy to cause at the top of fin and the threshold voltage of side wall differs.In order to ensure fin
The top threshold voltage identical with side wall tool at the top of fin with the Doped ions concentration of side wall, it is necessary to being adjusted.It is however, straight
It connects and fin progress ion implanting can not control the Doped ions concentration with side wall injection at the top of fin, so as to be difficult pair
Threshold voltage is adjusted.
To solve the technical problem, the present invention provides a kind of forming method of semiconductor structure, including：Lining is provided
Bottom, the substrate include first area and second area；Barrier layer is formed on the substrate of the first area and second area,
The barrier layer thickness of the first area and the barrier layer thickness of the second area differ；It is formed after barrier layer, to institute
It states substrate and is doped processing, the first doped region is formed in the substrate of first area, is formed in the substrate of second area
Two doped regions, first doped region are different from the doping concentration of the second doped region.
Wherein, it is doped before processing, forms barrier layer over the substrate.Due to the barrier layer of the first area
The barrier layer thickness of thickness and the second area differs, can be according to described the during the barrier layer is formed
The thickness on the barrier layer is adjusted in doping concentration needed for one doped region and the second doped region, so that the doping of substrate
Concentration meets the first area simultaneously and second area forms the needs of semiconductor devices.Specifically, it mixes when described first
When the doping concentration of diamicton is higher, it can be stopped by reducing the barrier layer thickness on the first area substrate so as to reduce
Layer makes the doping concentration of first doped region higher the barrier effects of Doped ions；When second doped region
It, can be by making barrier layer on the second area substrate that there is smaller thickness, so as to reduce the when doping concentration is higher
Two region blocks layers make the second doped region have higher doping concentration the barrier effects of Doped ions.
It is understandable for the above objects, features and advantages of the present invention is enable to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 1 to Fig. 6 is the structure diagram of each step of one embodiment of forming method of the semiconductor structure of the present invention.
In the present embodiment, the forming method of the semiconductor structure to be formed for being doped to substrate so as to adjust
The threshold voltage of transistor, in other embodiments, the forming method of the semiconductor structure can be also used for being formed the not isomorphous
The source and drain doping area of body pipe either for lightly doped drain injection or anti-break-through injection etc. during.
It please refers to Fig.1, substrate 100 is provided, the substrate 100 includes first area A and second area B.
In the present embodiment, the first area A is used to form the first transistor；The second area B is used to form second
Transistor.The first transistor has different threshold voltages from the second transistor.
In the present embodiment, the substrate 100 is planar substrate, specifically, the substrate 100 is silicon substrate.In other realities
It applies in example, the substrate can also be the Semiconductor substrates such as germanium substrate, silicon-Germanium substrate, silicon-on-insulator or germanium on insulator.
In the present embodiment, also there is isolation structure 101 in the substrate 100, the isolation structure 101 is described for isolating
First area A and second area B.
In the present embodiment, the material of the isolation structure 101 is silica.In other embodiments, the isolation structure
Material can also be silicon nitride or silicon oxynitride.
Subsequently barrier layer, the stop of the first area A are formed on the substrate 100 first area A and second area B
Layer thickness and the barrier layer thickness of the second area B differ.
In the present embodiment, the step of forming the barrier layer, is as shown in Figures 2 and 3.
It please refers to Fig.2, initial resistance layer 110 is formed on the substrate 100 first area A and second area B.
The initial resistance layer 110 is subsequently used for forming barrier layer.
In the present embodiment, the material of the initial resistance layer 110 is silica.In other embodiments, the initial resistance
The material of barrier can also be silicon nitride, silicon oxynitride, silicon, germanium, SiGe or carbon silicon.
In the present embodiment, forming the technique of the initial resistance layer 110 includes：Chemical vapor deposition method, thermal oxide work
Skill, physical gas-phase deposition or atom layer deposition process.
It please refers to Fig.3, patterned mask is formed on the initial resistance layer 110 (as shown in Figure 2) of the second area B
Layer 112.
The mask layer 112 is used to protect initial resistance layer 110 below.
It should be noted that in the present embodiment, the first area A is for forming high threshold voltage transistors, described the
Two region B are used to form low threshold voltage transistor.During follow-up doping treatment, in the first area A substrates 100
The Doped ions of incorporation high concentration are needed, the Doped ions of low concentration are mixed in the second area B substrates 100.Thus may be used
See, the barrier layer thickness of the first area A should be less than the thickness on the second area B barrier layers.
In other embodiments, for forming low threshold voltage transistor, the second area is used for for the first area
Form high threshold voltage transistors.During follow-up doping treatment, need to mix low concentration in the first area substrate
Doped ions, in the second area substrate mix high concentration Doped ions.It can be seen that the resistance of the first area
Barrier thickness should be more than the thickness on the second area barrier layer.
In other embodiments, the Doped ions concentration in the substrate can also be along the either direction line in substrate surface
Property variation.So as to the barrier layer thickness along the either direction linear change in the substrate surface.
By that can obtain above, in the present embodiment, the mask layer 112 covers the initial resistance layer 110 of the second area B,
Expose the initial resistance layer 110 of the first area A.
In other embodiments, the barrier layer thickness of the first area should be more than the thickness on the second area barrier layer
The initial resistance layer of degree, then the mask layer covering first area exposes the initial resistance layer of the second area.
With continued reference to Fig. 3, the initial resistance layer 110 (as shown in Figure 2) is carved for mask with the mask layer 112
Erosion.
It is described to etch to reduce the initial resistance layer 110 (as shown in Figure 2) of the first area A in the present embodiment
Thickness forms barrier layer 111.
The barrier layer 111 is used to that the Doped ions concentration mixed in successive substrates 100 to be adjusted.
In the present embodiment, the initial resistance layer 110 is performed etching by dry etch process.In other embodiment
In, the initial resistance layer can also be performed etching by wet-etching technology.
In the present embodiment, the material identical of the material on the barrier layer 111 and the initial resistance layer 110.Specifically, institute
The material for stating barrier layer 111 is silica.In other embodiments, the material on the barrier layer can also be silicon nitride, nitrogen oxygen
SiClx, silicon, germanium, SiGe or carbon silicon.
After being performed etching to the initial resistance layer 110, the method for forming the barrier layer 111 further includes：Removal institute
State mask layer 112.
In the present embodiment, removing the technique of the mask layer 112 includes：Dry etch process or wet-etching technology.
It please refers to Fig.4, is formed after barrier layer 111, processing is doped to the substrate 100, the lining of A in first area
The first doped region 171 is formed in bottom 100, the second doped region 172, first doping are formed in the substrate 100 of second area B
Area 171 is different from the doping concentration of the second doped region 172.
The doping treatment is used to mix Doped ions in the substrate 110.
In the present embodiment, the Doped ions are for being adjusted the threshold voltage of formed transistor, in other realities
It applies in example, the Doped ions can be also used for forming well region, lightly doped drain or dizzy area.
It should be noted that in the present embodiment, since 111 thickness of barrier layer of the first area A is smaller, described first
Region A barrier layers 111 are small to the barrier effect of Doped ions, therefore during doping treatment there are more Doped ions to wear
The barrier layer 111 for crossing the first area A enters in first area A substrates 100, so that being adulterated in first area A substrates 100
The concentration of ion is higher；Simultaneously as 111 thickness of barrier layer of the second area B is larger, the second area B barrier layers
The barrier effect of 111 pairs of Doped ions is larger, therefore has less Doped ions through described the during doping treatment
The barrier layer 111 of two region B into second area B substrates 100 so that in second area B substrates 100 Doped ions it is dense
It spends relatively low.It can be seen that the doping treatment can make the threshold voltage for the first transistor being subsequently formed be more than described second
The threshold voltage of transistor, so as to fulfill the adjusting to formed semiconductor structure threshold voltage.
In the present embodiment, the step of doping treatment, includes：Ion implanting is carried out to the substrate 100, in the lining
The Doped ions are injected in bottom 100.
In other embodiments, the step of doping treatment includes：Doped layer is formed in the barrier layer surface, it is described
There are Doped ions in doped layer；The doped layer is made annealing treatment, the Doped ions is made to diffuse into the substrate；
After the annealing, the doped layer is removed.
Fig. 5 is refer to, removes the barrier layer 111 (as described in Figure 4).
In the present embodiment, removing the technique on the barrier layer 111 includes：Dry etch process or wet-etching technology.
Fig. 6 is refer to, after removing the barrier layer 111, gate structure is formed on the substrate 100.
In the present embodiment, the gate structure includes：First grid structure on the first area A substrates 100
121；Second grid structure 122 on the second area B substrates 100.
The first transistor includes：First area A substrates 100, the first doped region 171 and first grid structure 121；Institute
Stating second transistor includes：Second area B substrates 100, the second doped region 172 and second grid structure 122.
In the present embodiment, the first grid structure 121 includes：The first grid on the first area A substrates 100
Dielectric layer；First grid on first gate dielectric layer.
In the present embodiment, the second grid structure 122 includes：Second gate on the second area B substrates 100
Dielectric layer；Second grid on second gate dielectric layer.
In the present embodiment, the material of first gate dielectric layer and the second gate dielectric layer is silica.In other embodiment
In, the material of first gate dielectric layer and the second gate dielectric layer can also be high K (K is more than 3.9) dielectric material.
In the present embodiment, the material of the first grid and second grid is polysilicon.In other embodiments, described
The material of one grid and second grid can also be metal.
To sum up, in the forming method of semiconductor structure provided in an embodiment of the present invention, it is doped before processing, described
Barrier layer is formed on substrate.Due to the barrier layer thickness not phase of barrier layer thickness and the second area of the first area
It together, can be according to the doping concentration needed for first doped region and the second doped region during the barrier layer is formed
The thickness on the barrier layer is adjusted, so that the doping concentration of substrate meets the first area and second area simultaneously
The needs of formed semiconductor devices.Specifically, when the doping concentration of first doped layer is higher, it can be by reducing
The barrier layer thickness on the substrate of first area is stated, so as to reduce barrier effect of the barrier layer to Doped ions, and then makes described
The doping concentration of one doped region is higher；It, can be by making secondth area when the doping concentration of second doped region is higher
Barrier layer on the substrate of domain has smaller thickness, so as to reduce barrier effect of the second area barrier layer to Doped ions, into
And make the second doped region that there is higher doping concentration.
Fig. 7 to Figure 15 is the structure diagram of each step of another embodiment of forming method of semiconductor structure of the present invention.
Fig. 7 is refer to, substrate 200 is provided, the substrate 200 includes first area and second area.
In the present embodiment, there is fin 201 on the substrate 200, the fin 201 includes the first area and second
Region, the first area are located on second area top.
In the present embodiment, the material of the substrate 200 and fin 201 is silicon.In other embodiments, the substrate and fin
The material in portion can also be germanium or SiGe.
In the present embodiment, the step of forming the substrate 200 and fin 201, includes：Initial substrate is provided；To described initial
Substrate is patterned, and forms substrate 200 and the fin 201 on the substrate 200.
It should be noted that be patterned to the initial substrate, it is described during forming the fin 201
Different shapes is easily formed on 201 top of fin.For example, the first area fin 201 has tip or the fin
201 tops are cylindrical surface.The present embodiment is illustrated so that 201 top of fin has tip as an example.
Fig. 8 is refer to, isolation structure 202 is formed on the substrate 200, the isolation structure 202 covers the fin
201 partial sidewalls, 202 surface of isolation structure are less than 201 top surface of fin.
The isolation structure 202 is used to implement the isolation between different fins 201.
In the present embodiment, the material of the isolation structure 202 is silica.In other embodiments, the isolation structure
Material can also be silicon nitride or silicon oxynitride.
In the present embodiment, the step of forming isolation structure 202, includes：Initial isolation is formed on the substrate 200
Structure, it is described to be initially higher than 201 top surface of fin every body structure surface；The initial isolation structure is performed etching, is made
The initial isolation structure surface is less than 201 top surface of fin.
Subsequently at the top of the fin and fin sidewall surfaces form barrier layer.In the present embodiment, the barrier layer is formed
The step of as shown in Figure 9 and Figure 10.
Fig. 9 is refer to, at the top of the fin and fin sidewall surfaces form initial resistance layer 210.
The initial resistance layer 210 is used to be subsequently formed barrier layer.
In the present embodiment, the material of the initial resistance layer 210 is silica.In other embodiments, the initial resistance
The material of barrier 210 can also be silicon nitride, silicon oxynitride, germanium, silicon or SiGe.
If the thickness of the initial resistance layer 210 is too small, it is unfavorable for playing barrier effect to subsequent Doped ions；If
The thickness of the initial resistance layer 210 is too small big, it is not easy to and subsequent Doped ions is made to diffuse into the fin 201, so as to
Easily increase technology difficulty.Specifically, in the present embodiment, the thickness of the initial resistance layer 210 is 0.5nm~5nm.
In the present embodiment, forming the technique of the initial resistance layer 210 includes chemical vapor deposition method, thermal oxide work
Skill, physical gas-phase deposition or atom layer deposition process.
0 is please referred to Fig.1, the initial resistance layer 210 is performed etching, it is part or all of on 201 top of removal fin
The initial resistance layer 210 of thickness forms barrier layer 211.
The barrier layer 211 is used to that the Doped ions concentration that follow-up 201 side wall of fin and top mix to be adjusted.Tool
Body, it, can be by reducing the 201 top table of fin if the Doped ions concentration needed for 201 top of the fin is higher
211 thickness of barrier layer in face reduces barrier effect of the barrier layer 211 to Doped ions of 201 top surface of fin, so as to increase
The Doped ions concentration at 201 top of fin；If the Doped ions concentration needed for 201 side wall of fin is higher, can pass through
Reduce 211 thickness of barrier layer of 201 sidewall surfaces of fin, so as to reduce the barrier layer 211 of 201 sidewall surfaces of fin to mixing
The barrier effect of heteroion, and then the Doped ions concentration of 201 side wall of fin can be increased.
It should be noted that since the first area fin 201 has tip, the semiconductor structure formed is in technique
In the process, gate structure is stronger to the control ability at the tip, so as to which the raceway groove for easily making 201 top of fin is opened
It opens, the tip is easily reduced the threshold voltage at 201 top of fin.In the present embodiment, in order to make 201 top of fin
It is identical with the threshold voltage of side wall, it is necessary to improve the Doped ions concentration in 201 top of the fin.
It, can be by the way that 211 thickness of barrier layer of 201 top surface of fin be made to be less than the fin in the present embodiment
211 thickness of barrier layer of 201 sidewall surfaces makes the 201 top Doped ions concentration of fin be higher than the 201 side wall table of fin
The Doped ions concentration in face.
In other embodiments, the Doped ions concentration needed for the fin top may also be below the fin side wall institute
The Doped ions concentration needed, then by the way that the barrier layer thickness of the fin top surface is made to be more than the resistance of the fin sidewall surfaces
Barrier thickness is adjusted.
In the present embodiment, anisotropic dry etch is included to the technique that the initial resistance layer 210 performs etching.Respectively to
The etch rate of different in nature dry etching in the horizontal is less than the etch rate of longitudinal direction, so as to make on 201 top of fin
211 thickness of barrier layer be less than 201 sidewall surfaces of fin 211 thickness of barrier layer.
In the present embodiment, 211 thickness of barrier layer of 201 top surface of fin is not 0.In other embodiments, institute
It can be 0 to state the barrier layer thickness at the top of fin.
In other embodiments, the step of forming the barrier layer includes：It is formed and covers the fin side wall and top table
The initial resistance layer in face；Form graph layer in the initial resistance layer surface, the graph layer expose at the top of the fin or
The initial resistance layer of sidewall surfaces；The initial resistance layer is performed etching using the graph layer as mask；To the initial resistance
After barrier performs etching, the mask layer is removed.
It is subsequently formed after barrier layer 211, processing is doped to 201 top of fin and side wall, in first area
Substrate in formed the first doped region, the second doped region, first doped region and second are formed in the substrate of second area
The doping concentration of doped region is different.
In the present embodiment, the step of being doped processing to 201 top of the fin and side wall, is as shown in Figure 11 to Figure 13.
It please refers to Fig.1 1, forms the doped layer 220 covered at the top of the fin side wall and fin, in the doped layer 220
With Doped ions.
The doped layer 220 is used to be doped the fin 201.
In the present embodiment, the Doped ions are used to that the threshold voltage of formed semiconductor structure to be adjusted.At it
In his embodiment, the Doped ions can be also used for forming dizzy area, reduce short-channel effect；Or the Doped ions are used for
Form lightly doped drain.
In the present embodiment, the step of forming doped layer 220, includes：It is formed and covers 201 side wall of fin and top
Stressor layers, and during the stressor layers are formed, the stressor layers are doped, form the doped layer 220.
In the present embodiment, the lattice constant of the stressor layers and the lattice constant of the fin 201 differ, so as to
Stress is provided for fin 201, so as to provide channel stress for the transistor that is formed, and then formed crystal can be increased
The migration rate of carrier in pipe trench road, therefore, the forming method can further improve formed semiconductor structure performance.
If specifically, formed semiconductor structure is PMOS transistor, the lattice constant of the stressor layers is less than described
The lattice constant of fin 201 applies tensile stress so as to the top to the fin 201 and side wall, so as to along the fin
Compression is generated to fin 201 on 201 extending direction of portion, so as to increase the channel carrier of formed PMOS transistor
Migration rate, and then improve PMOS transistor performance.Specifically, the material of the stressor layers is carbon silicon.
If formed semiconductor structure is NMOS transistor, the lattice constant of the stressor layers is more than the fin 201
Lattice constant, apply compression so as to the top to the fin 201 and side wall, so as to prolong along the fin 201
It stretches and tensile stress is generated to fin 201 on direction, so as to increase the migration of the channel carrier of formed NMOS transistor speed
Rate, and then improve NMOS transistor performance.Specifically, the material of the stressor layers is SiGe, it is in other embodiments, described to answer
The material of power layer can also be silicon nitride.
In the present embodiment, forming the technique of the stressor layers includes chemical vapor deposition method or physical vapour deposition (PVD) work
Skill.
In the present embodiment, if formed semiconductor structure be PMOS transistor, the Doped ions be N-type ion, example
Such as phosphonium ion or arsenic ion；If formed semiconductor structure is NMOS transistor, the Doped ions are p-type ion, such as
Boron ion or BF2-Ion.
In other embodiments, the Doped ions form lightly doped drain after can be also used for being formed gate structure,
Then if formed semiconductor structure is PMOS transistor, the Doped ions are p-type ion, such as boron ion or BF2-Ion；
If formed semiconductor structure is NMOS transistor, the Doped ions are N-type ion, such as phosphonium ion or arsenic ion.
In the present embodiment, the concentration of Doped ions is 5E19atoms/cm in the doped layer3~5E21atoms/cm3。
Please refer to Fig.1 2, formed after the doped layer 220, the doped layer 220 is made annealing treatment, make doping from
Son is diffused into the fin 201, and the first doped region 271 is formed in the first area fin 201, in secondth area
The second doped region 272 is formed in domain fin 201.
It should be noted that during the annealing, it is described due to the barrier effect on the barrier layer 211
Doped ions diffuse into 201 side wall of fin and the concentration at top differs.
Specifically, in the present embodiment, 211 thickness of barrier layer of 201 top surface of fin is smaller, to it is described adulterate from
The barrier effect of son is weaker, so that the Doped ions for diffusing into 201 top of fin are more, i.e., described fin 201 pushes up
The Doped ions concentration in portion is higher.
211 thickness of barrier layer of 201 sidewall surfaces of fin is larger, stronger to the barrier effect of the Doped ions,
So that the Doped ions for diffusing into 201 side wall of fin are less, i.e., the Doped ions concentration of described 201 side wall of fin compared with
It is low.
To sum up, the forming method makes the Doped ions concentration at 201 top of fin be more than 201 side wall of fin
Doped ions concentration, so that the raceway groove of 201 side wall of the fin is easier to open；Further, since the 201 top tool of fin
There is tip, the tip can reduce the threshold voltage at 201 top of fin, and therefore, the forming method can make described
201 top of fin and side wall have identical threshold voltage, and then can improve formed semiconductor structure performance.
In the present embodiment, the technological parameter of the annealing includes：Annealing time be 10min~30min, annealing temperature
For 950 DEG C~1100 DEG C；Or the technological parameter of the annealing includes：Annealing time is 11min~30min, and annealing is warm
It spends for 750 DEG C~900 DEG C.
It please refers to Fig.1 3, after annealing, removes the doped layer 220 (as shown in figure 12).
In the present embodiment, removing the technique of the doped layer 220 includes：Dry etch process or wet-etching technology.
4 are please referred to Fig.1, after removing the doped layer 220, removes the barrier layer 211 (as shown in figure 13).
In the present embodiment, removing the technique on the barrier layer 211 includes：Dry etch process or wet-etching technology.
5 are please referred to Fig.1, after removing the barrier layer 211, is developed across the gate structure 230 of the fin 201, institute
It states gate structure 230 and covers 201 partial sidewall of fin and top surface.
The 230 lower section fin 201 of gate structure is used to form transistor channel.
In the present embodiment, the gate structure 230 includes：Across the gate dielectric layer of the fin 201, the gate dielectric layer
Cover 201 partial sidewall of fin and top surface；Grid on the gate dielectric layer.
In the present embodiment, the material of the gate dielectric layer is silica.In other embodiments, the material of the gate dielectric layer
Material can also be high K (K is more than 3.9) dielectric material.
In the present embodiment, the material of the grid is polysilicon.In other embodiments, the material of the grid can be with
For metal.
To sum up, in the forming method of semiconductor structure provided in this embodiment, the substrate includes fin, secondth area
Domain fin has tip, is formed after gate structure, and the gate structure is stronger to the control action at the tip, therefore, institute
Stating tip makes the raceway groove at the top of the fin of formed transistor be easier to open than the raceway groove of side wall.By making at the top of the fin
Barrier layer thickness be less than the fin sidewall surfaces barrier layer thickness, so as to make the Doped ions concentration at the top of fin
Less than the Doped ions concentration of fin side wall, and then raise the threshold voltage at the top of fin.It to sum up, can be by described in adjusting
The thickness on barrier layer makes fin side wall identical with the threshold voltage at the top of fin, so as to improve the property of formed semiconductor structure
Energy.
Further, during forming the doped layer, the stressor layers can provide stress for fin, so as to for
The transistor formed provides corresponding channel stress, and then can increase the migration speed of carrier in formed transistor channel
Rate, therefore, the forming method can further improve formed semiconductor structure performance.Specifically, the semiconductor structure
For PMOS transistor when, the lattice constants of the stressor layers is less than the lattice constant of the fin, then the stressor layers are to described
At the top of fin and side wall applies tensile stress, so as to provide compression along the fin extending direction for the fin, so as to
The migration rate of the channel carrier of formed PMOS transistor can be increased；When the semiconductor structure is NMOS transistor,
The lattice constant of the stressor layers is more than the lattice constant of the fin, then the stressor layers are applied to fin top and side wall
Pressurize stress, so as to provide tensile stress along the fin extending direction for the fin, to be formed so as to increase
The migration rate of the channel carrier of PMOS transistor.It can be seen that the forming method can further improve to form half
Conductor structure performance.
The embodiment of the present invention also provides a kind of semiconductor structure, please refers to Fig.1 3, the semiconductor structure includes：Lining
Bottom, the substrate include first area and second area；Barrier layer on the substrate first area and second area
211,211 thickness of barrier layer of the first area is differed with 211 thickness of barrier layer of the second area；Positioned at the firstth area
The first doped region 271 in the substrate in domain forms the second doped region 272, first doping in the substrate of second area
Area 271 is different from the doping concentration of the second doped region 272.
In the present embodiment, the substrate includes substrate 200 and the fin 201 in the substrate 200.
In the present embodiment, the fin 201 includes the first area and second area, and the first area is located at described
On at the top of second area.
Specifically, in the present embodiment, the Doped ions concentration of first doped region 271 is more than second doped region
272 Doped ions concentration.The Doped ions concentration of 201 side wall of fin is less than the Doped ions at 201 top of fin
Concentration.
In the present embodiment, the semiconductor structure further includes the isolation structure 101 in the substrate.
In the present embodiment, in the thickness on the barrier layer 211, material and forming method embodiment shown in Fig. 7 to Figure 15
The thickness on barrier layer, material identical.
Although present disclosure is as above, present invention is not limited to this.Any those skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure, which is characterized in that including：
Substrate is provided, the substrate includes first area and second area；
Form barrier layer on the substrate of the first area and second area, the barrier layer thickness of the first area with it is described
The barrier layer thickness of second area differs；
It is formed after barrier layer, processing is doped to the substrate, the first doped region is formed in the substrate of first area,
The second doped region is formed in the substrate of second area, first doped region is different from the doping concentration of the second doped region.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of forming barrier layer includes：
Initial resistance layer is formed on the substrate first area and second area；It is formed and covered on the second area initial resistance layer
Film layer；The initial resistance layer is performed etching using the mask layer as mask；After being performed etching to the initial resistance layer,
Remove the mask layer.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of doping treatment wraps
It includes：Ion implanting is carried out to the substrate, injects the Doped ions in the substrate.
4. the forming method of semiconductor structure as described in claim 1, which is characterized in that the step of doping treatment wraps
It includes：Doped layer is formed on the substrate exposed on the barrier layer and barrier layer, there are Doped ions in the doped layer；To institute
It states doped layer to be made annealing treatment, the Doped ions is made to diffuse into the substrate；After the annealing, described in removal
Doped layer.
5. the forming method of semiconductor structure as described in claim 1, which is characterized in that the material on the barrier layer is oxidation
Silicon, silicon nitride, silicon oxynitride, silicon, germanium, SiGe or silicon-carbon.
6. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate includes substrate and is located at
Fin in the substrate, the fin include the first area and second area, and the first area is located at described second
At the top of region.
7. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the step of doping treatment wraps
It includes：Ion implanting is carried out to the fin, the Doped ions are injected in the fin.
8. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the step of doping treatment wraps
It includes：The doped layer for covering the fin side wall and top is formed, there are Doped ions in the doped layer；Form the doped layer
Afterwards, the doped layer is made annealing treatment, Doped ions is made to diffuse into the fin；After the annealing,
Remove the doped layer.
9. the forming method for the semiconductor structure stated such as claim 8, which is characterized in that the material of the doped layer is containing mixing
SiGe, silicon nitride or the carbon silicon of heteroion.
10. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the step of forming the doped layer
Including：The stressor layers for covering the fin side wall and top are formed, and during the stressor layers are formed, to the stress
Layer is doped, and forms the doped layer.
11. the forming method of semiconductor structure as claimed in claim 10, which is characterized in that the stressor layers are used to be formed
PMOS transistor, the lattice constant of the stressor layers are less than the lattice constant of the fin；
Alternatively, the stressor layers, for forming NMOS transistor, the lattice constant of the stressor layers is more than the lattice of the fin
Constant.
12. the forming method of semiconductor structure as claimed in claim 11, which is characterized in that the stressor layers are used to be formed
PMOS transistor, the material of the stressor layers is carbon silicon；
Alternatively, the stressor layers, for forming NMOS transistor, the material of the stressor layers is SiGe.
13. the forming method of semiconductor structure as claimed in claim 8, which is characterized in that the thickness of the doped layer is
20nm~50nm.
14. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the step of forming the barrier layer
Including：Form the initial resistance layer for covering the fin side wall and top surface；Figure is formed in the initial resistance layer surface
Layer, the graph layer exposes at the top of the fin or the initial resistance layer of sidewall surfaces；It is mask to institute using the graph layer
Initial resistance layer is stated to perform etching；After being performed etching to the initial resistance layer, the graph layer is removed.
15. the forming method of semiconductor structure as claimed in claim 14, which is characterized in that the thickness of the initial resistance layer
For 0.5nm~5nm.
16. the forming method of semiconductor structure as claimed in claim 6, which is characterized in that the fin tool of the first area
There is tip, the barrier layer thickness of the first area is less than the barrier layer thickness of the second area.
17. the forming method of semiconductor structure as claimed in claim 16, which is characterized in that the step of forming the barrier layer
Including：Initial resistance layer is formed in the fin side wall and top surface；The initial resistance layer is performed etching, removes fin
The initial resistance layer of the part or all of thickness of top surface.
18. the forming method of semiconductor structure as claimed in claim 17, which is characterized in that carried out to the initial resistance layer
The technique of etching includes：Anisotropic dry etch process.
19. the forming method of semiconductor structure as described in claim 1, which is characterized in that after the doping treatment, also wrap
It includes：Remove the barrier layer.
20. a kind of semiconductor structure formed using such as claim 1 to 19 any one method, which is characterized in that including：
Substrate, the substrate include first area and second area；
Barrier layer on the substrate first area and second area, the barrier layer thickness of the first area and described the
The barrier layer thickness in two regions differs；
The first doped region in the substrate of first area, the second doped region in the substrate of second area, described
One doped region is different from the doping concentration of the second doped region.
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Application publication date: 20180605 |