CN105336621A - Formation method for fin type field-effect transistor - Google Patents
Formation method for fin type field-effect transistor Download PDFInfo
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- CN105336621A CN105336621A CN201410369904.1A CN201410369904A CN105336621A CN 105336621 A CN105336621 A CN 105336621A CN 201410369904 A CN201410369904 A CN 201410369904A CN 105336621 A CN105336621 A CN 105336621A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A formation method for a fin type field-effect transistor is disclosed. The formation method comprises the steps of providing a substrate, wherein a plurality of separated fin parts are formed on the surface of the substrate; forming a separating layer on the surfaces of the side walls and the top parts of the fin parts, wherein the etching speed on the separating layer and the etching speed on the fin parts in an etching process are different; forming an impurity layer on the surface of the separating layer, wherein the impurity layer has atoms with the same material as the fin parts ; the impurity layer is further provided with N type ions or P type ions; performing annealing treatment on the substrate to enable the N type ions or the P type ions in the impurity layer to be diffused into the fin parts through the separating layer to form a doping region in the internal of the fin parts; the impurity layer is converted into an intrinsic layer; taking the separating layer as the etching stop layer and etching off the intrinsic layer; and etching off the separating layer until the top parts and the side wall surfaces of the fin parts are exposed. The concentration uniformity of the formed doping region is improved, the amorphization problem on the fin parts caused by the ion implantation technology is avoided, the completeness of the sizes of the fin parts is kept, and the electrical property of the fin type field-effect transistor is optimized.
Description
Technical field
The present invention relates to field of semiconductor fabrication technology, particularly a kind of formation method of fin field effect pipe.
Background technology
Along with the development of semiconductor process techniques, the development trend that semiconductor technology node follows Moore's Law constantly reduces.In order to adapt to the reduction of process node, have to constantly to shorten the channel length of MOSFET field effect transistor.The shortening of channel length has the tube core density increasing chip, increases the benefits such as the switching speed of MOSFET field effect transistor.
But, along with the shortening of device channel length, distance between device source electrode and drain electrode also shortens thereupon, so grid is deteriorated to the control ability of raceway groove, the difficulty of grid voltage pinch off (pinchoff) raceway groove is also increasing, make sub-threshold leakage (subthresholdleakage) phenomenon, namely so-called short-channel effect (SCE:short-channeleffects) more easily occurs.
Therefore, in order to better adapt to the scaled requirement of device size, semiconductor technology starts from planar MOSFET transistor to the transistor transient of three-dimensional with higher effect gradually, as fin field effect pipe (FinFET).In FinFET, grid at least can control from both sides to ultra-thin body (fin), has the grid more much better than than planar MOSFET devices to the control ability of raceway groove, can be good at suppressing short-channel effect; And FinFET is relative to other devices, there is the compatibility of better existing production of integrated circuits technology.
But the electric property of the fin field effect pipe that prior art is formed has much room for improvement.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of fin field effect pipe, while the even concentration improving doped region, avoids fin and doped region to sustain damage, and improves electric property and the reliability of fin field effect pipe.
For solving the problem, the invention provides a kind of formation method of fin field effect pipe, comprising: provide substrate, described substrate surface is formed with some discrete fins; Form separator at described fin sidewall and top surface, and the etch rate of etching technics to separator is different from the etch rate to fin; Form impurity layer in described insulation surface, in described impurity layer, there is the atom identical with fin material, and also there is in described impurity layer N-type ion or P type ion; Annealing in process is carried out to described substrate, makes the N-type ion in impurity layer or P type ion diffuse in fin by separator, in fin, form doped region, and impurity layer is converted into intrinsic layer; With described separator for etching stop layer, etching removes described intrinsic layer; Etching removes described separator, until expose fin top and sidewall surfaces.
Optionally, the material of described intrinsic layer is silicon, SiGe or carborundum.
Optionally, the material of described separator is silica.
Optionally, the thickness of described separator is 5 dust to 10 dusts.
Optionally, ald or oxidation technology is adopted to form described separator.
Optionally, adopt deionized water ozoniferous to carry out immersion treatment to described fin, described fin portion surface oxidation is formed described separator.
Optionally, in described deionized water ozoniferous, ozone concentration is 20ppm to 100ppm.
Optionally, the technological parameter of described atom layer deposition process is: reacting gas comprises silicon source gas and oxygen source gas, and reacting gas also comprises current-carrying gas, and wherein, silicon source gas is SiH
4, SiH
2cl
2, SiHCl
3or Si
2cl
6, oxygen source gas is O
2or O
3, current-carrying gas is N
2or Ar, silicon source gas flow is 100sccm to 5000sccm, and oxygen source gas flow is 100sccm to 2000sccm, and current-carrying gas flow is 100sccm to 5000sccm, and reaction chamber temperature is 50 degree to 450 degree, and reaction chamber pressure is that 1 holder to 200 is held in the palm.
Optionally, described oxidation technology is remote plasma oxidation or decoupled plasma oxidation.
Optionally, the thickness of described impurity layer is 50 dust to 300 dusts.
Optionally, described N-type ion is P, As or Sb, and described P type ion is B, Ga or In.
Optionally, the material of described impurity layer is mix the silicon of P type ion or mix the SiGe of P type ion.
Optionally, when the material of described impurity layer is the silicon of boron-doping, in impurity layer, boron atomic concentration is 1E21atom/cm
3to 5E25atom/cm
3.
Optionally, the material of described impurity layer is the silicon of doped type N ion or the carborundum of doped type N ion.
Optionally, low-pressure chemical vapor deposition process is adopted to form described impurity layer.
Optionally, the deposition reaction chamber temp of described low-pressure chemical vapor deposition process is 400 degree to 800 degree, and deposition reaction chamber pressure is that 5 holders to 100 are held in the palm.
Optionally, Tetramethylammonium hydroxide or ammoniacal liquor etching is adopted to remove described intrinsic layer.
Optionally, in the process forming described impurity layer or after the described impurity layer of formation, described annealing in process is carried out.
Optionally, the technique of described annealing in process is one or more in the annealing of spike annealing, Millisecond annealing or solid phase epitaxial regrowth.
Optionally, the technological parameter of described solid phase epitaxial regrowth annealing is: annealing temperature is 400 degree to 650 degree, and annealing pressure is that 1 holder to 760 is held in the palm, and anneal duration is 1min to 120min, at N
2or carry out under atmosphere of inert gases.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the embodiment of the present invention, form separator at fin sidewall and top surface, and the etch rate of etching technics to separator is different from the etch rate to fin; Form impurity layer in insulation surface, in described impurity layer, there is the atom identical with fin material, and also there is in described impurity layer N-type ion or P type ion; Annealing in process is carried out to substrate, the N-type ion in impurity layer or P type ion is made to diffuse in fin by separator, doped region is formed in fin, and impurity layer is converted into intrinsic layer, in corresponding intrinsic layer, there is the atom identical with fin material atom, and the content of N-type ion in intrinsic layer or P type ion is considerably less does not even exist, therefore the material character of described intrinsic layer and fin material character are closely, and the etch rate of etching technics to intrinsic layer and the etch rate to fin are closely.And the present invention is formed with separator between intrinsic layer and fin, and the etch rate of etching technics to separator is different from the etch rate to fin, therefore when etching removal intrinsic layer, described separator plays the effect of etching stop layer, prevent etching the etching technics removing intrinsic layer and etching is caused to fin, keep the integrality of fin size, and etching is caused in the doped region avoided being formed in fin, maintain the integrality of doped region, thus improve electric property and the reliability of fin field effect pipe.
Simultaneously, the embodiment of the present invention adopts the N-type ion in impurity layer or P type ion to diffuse into by separator the method that fin forms doped region, because N-type ion or P type ion are by just diffusing in fin after separator, compared with prior art, it is more shallow that the doped region that the embodiment of the present invention is formed can be done.Further, the method for the formation doped region provided by the embodiment of the present invention, avoids the decrystallized problem that ion implantation technology is brought, and compared with prior art, the ion concentration distribution of the doped region that the embodiment of the present invention is formed evenly.
Further, the embodiment of the present invention adopts low-pressure chemical vapor deposition process to form impurity layer, under environment under low pressure, the mean free path of the gaseous molecular of reacting gas is larger, the reacting gas concentration in reaction chamber is made to reach uniform concentration distribution state fast, thus the even concentration of the N-type ion improved in the impurity layer formed or P type ion, and then make formation doped region CONCENTRATION DISTRIBUTION evenly, improve further the electric property of fin field effect pipe.
Further, the thickness of embodiment of the present invention separator is 5 dust to 10 dusts, has both ensured the follow-up effect playing etching stop layer, avoids again the problem that the doped region of causing because separation layer thickness is blocked up is excessively shallow.
Accompanying drawing explanation
The schematic flow sheet of the fin field effect pipe formation method that Fig. 1 provides for an embodiment;
The cross-sectional view of the fin field effect pipe forming process that Fig. 2 to Figure 15 provides for the embodiment of the present invention.
Embodiment
From background technology, the electric property of the fin field effect pipe that prior art is formed has much room for improvement.
Find after deliberation, prior art, when the source region of fin field effect pipe and drain region, adopts the fin of method to fin field effect pipe of ion implantation to adulterate usually; Because fin is stereochemical structure, when the angle of ion implantation is different, concentration and the injection degree of depth of source region and drain region ion implantation will be different, cause occurring that non-conformal (un-conformal) is adulterated problem, the doping content in each region of fin is different, such as, the doping content of fin top area is larger than the doping content of fin sidewall areas; Described non-conformal doping problem causes one of fin field effect pipe electric property difference important reason.
Further, ion implantation technology also can cause fin portion surface decrystallized (amorphization), and the decrystallized fin field effect pipe electric property that also can cause of fin portion surface is poor.
For solving the problem, proposing a kind of formation method of fin field effect pipe, please refer to Fig. 1, comprise the following steps: step S1, provide substrate, described substrate surface is formed with some discrete fins; Step S2, form impurity layer in described fin top surface and sidewall surfaces, there is in described impurity layer N-type ion or P type ion; Step S3, annealing in process is carried out to described substrate, make the N-type ion in impurity layer or P type ion diffuse enter fin, form doped region; Step S4, after the annealing process is completed, etching removes described impurity layer.
Said method avoids the decrystallized problem that ion implantation technology is brought, and the doping content of fin top area and sidewall areas reaches unanimity.
In order to improve the quality of the impurity layer of formation, reduce the hole in impurity layer, with make the N-type ion in impurity layer or P type ion distribution even, improve the uniform concentration distribution of the doped region formed, adopt the material containing silicon, germanium, SiGe, GaAs or carborundum as the material of impurity layer, also there is in impurity layer N-type ion or P type ion accordingly.
But, when after experience annealing in process, N-type ion in impurity layer or P type ion diffuse enter fin, in impurity layer, remaining material is silicon, germanium, SiGe, GaAs or carborundum, described material character and fin material character close, cause etch remove described impurity layer time, described etching technics also has larger etch rate to fin, cause fin and doped region to be partially etched removal, cause electric property and the reliability decrease of fin field effect pipe.
For this reason, the invention provides a kind of formation method of fin field effect pipe, form separator at fin sidewall and top surface; Form impurity layer in insulation surface, in described impurity layer, there is the atom identical with fin material, and there is in described impurity layer N-type ion or P type ion; Annealing in process is carried out to described substrate, makes the N-type ion in impurity layer or P type ion diffuse enter in fin, in fin, form doped region, and impurity layer is converted into intrinsic layer; With described separator for etching stop layer, etching removes described intrinsic layer; Etching removes described separator, until expose fin top and sidewall surfaces.The embodiment of the present invention is by entering the method for fin by the N-type ion in impurity layer or P type ion diffuse, avoid the decrystallized and non-conformal doping problem that ion implantation technology is brought, and prevent the technique removing intrinsic layer from causing harmful effect to fin, make fin have good pattern and complete characteristic size, improve electric property and the reliability of the fin field effect pipe formed.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
The semiconductor structure that Fig. 2 to Figure 15 provides for one embodiment of the invention forms process cross-sectional view.
Please refer to Fig. 2, provide substrate 100, described substrate 100 comprises first area I and second area II, and I substrate 100 surface, first area is formed with some the first discrete fins 101, and second area II substrate 100 surface is formed with some the second discrete fins 102.
Described substrate 100 provides workbench for follow-up formation fin field effect pipe.The material of described substrate 100 is silicon, germanium, SiGe, GaAs, carborundum or isolate supports.
In the present embodiment, the material of described substrate 100 is silicon.
Described first area I is NMOS area or PMOS area, and described second area II is NMOS area or PMOS area; The type of described first area I and second area II can identical also can be contrary, the fin field effect pipe therefore formed can be nmos device, PMOS device or cmos device.The present embodiment with the fin field effect pipe formed for cmos device, and first area I be PMOS area, second area II be NMOS area is that example does exemplary illustrated.
Described first fin 101 and the second fin 102 are adopt dry etching method (RIE:ReactiveIonEtching) to etch an initial semiconductor substrate to be formed.
As an embodiment, the forming step of described first fin 101 and the second fin 102 is: provide initial semiconductor substrate, described initial semiconductor substrate comprises first area and second area; Form patterned mask layer at described initial semiconductor substrate surface, described mask layer defines the position of follow-up formation first fin 101 and the second fin 102; With patterned mask layer for mask, adopt reactive ion etching process, the initial semiconductor substrate of etched portions thickness is to forming substrate 100, described substrate 100 comprises first area I and second area II, form some the first discrete fins 101 on first area I substrate 100 surface, form some the second discrete fins 102 on second area II substrate 100 surface.
In other embodiments, double-pattern exposure method also can be adopted to form the first fin and the second fin, concrete, the processing step forming fin comprises: provide initial semiconductor substrate, described initial semiconductor substrate comprises first area and second area; Patterned sacrifice layer is formed at described initial semiconductor substrate surface; Form the initial side wall film being covered in described sacrificial layer surface and initial semiconductor substrate surface; Return the described initial side wall film of etching, form initial side wall layer at sacrifice layer sidewall; Remove described sacrifice layer; With described initial side wall layer for mask, the initial semiconductor substrate that etching removes segment thickness forms substrate, described substrate comprises first area and second area, forms some the first discrete fins at first area substrate surface, forms some the second discrete fins at second area substrate surface.
Please refer to Fig. 3, substrate 100 surface between the first fin 101 and the second fin 102 forms isolation structure 103, and described isolation structure 103 top surface is lower than the first fin 101 and the second fin 102 top surface.
Described isolation structure 103, for isolating the first adjacent fin 101, the second adjacent fin 102, prevents from being electrically connected between adjacent first fin 101 and adjacent second fin 102.
The material of described isolation structure 103 is silica, silicon nitride or silicon oxynitride,
As an embodiment, the processing step forming described isolation structure 103 comprises: on described substrate 100 surface, the first fin 101 surface and the second fin 102 surface form barrier film, and the top surface of described barrier film is higher than the first fin 101 and the second fin 102 top surface; Return the described barrier film of etching and form isolation structure 103, and isolation structure 103 top surface is lower than the first fin 101 and the second fin 102 top surface.
The present embodiment adopts mobility chemical vapor deposition method to form described barrier film, and the filling effect of the corner of isolation structure 103 between substrate 100 and the first fin 101 making to be formed, the corner between substrate 100 and the second fin 102 is good.
In other embodiments of the present invention, before formation isolation structure, liner oxidation layer can also be formed in the first fin portion surface and the second fin portion surface, described liner oxidation layer can repair damage that the first fin and the second fin sidewall be subject to (such as, the damage that etching technics when forming the first fin and the second fin causes), thering is provided good interfacial state for forming isolation structure, making isolation structure and the first fin and the second fin sidewall contact tight.
Please refer to Fig. 4, form the first mask layer 104 at described isolation structure 103 surface, the first fin 101 top surface and sidewall surfaces and the second fin 102 top surface and sidewall surfaces.
Acting as of described first mask layer 104: first mask layer 104 of follow-up removal first area I, retain first mask layer 104 of second area II, thus prevent the foreign ion in the first impurity layer of follow-up formation from diffusing in the second fin 102, avoid carrying out unnecessary doping to the second fin 102.
The material of described first mask layer 104 is silica, silicon nitride, silicon oxynitride or amorphous carbon; Described first mask layer 104 is single layer structure or laminated construction.Low-pressure chemical vapor deposition process or atom layer deposition process is adopted to form described first mask layer 104.
It is follow-up when first area I forms the first impurity layer, described first impurity layer is also formed at first mask layer 104 surface of second area II, if the thickness of the first mask layer 104 is excessively thin, then the foreign ion of the first impurity layer can diffuse in the second fin 102 by described first mask layer 104, cause and unnecessary doping is carried out to the second fin 102, the electric property of the fin field effect pipe that impact is formed; If the thickness of the first mask layer 104 is blocked up, the etch period needed for the first mask layer 104 that subsequent etching removes first area I is longer, described etching technics increases the harmful effect that the first fin 101 brings, and the etch period needed for the first mask layer 104 that subsequent etching removes second area I is also longer, same described etching technics also increases the harmful effect that the second fin 102 brings.
Comprehensive above-mentioned consideration analysis, in the present embodiment, the thickness of the first mask layer 104 is 500 dust to 2000 dusts.
In the present embodiment, described first mask layer 104 is single layer structure, and the material of the first mask layer 104 is silicon nitride.
Please refer to Fig. 5, form the first photoresist layer 105 on first mask layer 104 surface of described second area II.
Described first photoresist layer 105 removes the mask of first area I first mask layer 104 as subsequent etching.
As a specific embodiment, the forming step of described first photoresist layer 105 comprises: form initial lithographic glue-line on first mask layer 104 surface of described first area I and second area II; Described initial lithographic glue-line is exposed, development treatment, remove and be positioned at the initial lithographic glue-line of first area I, form described first photoresist layer 105.
Please refer to Fig. 6, with described first photoresist layer 105 (please refer to Fig. 5) for mask, etching removes first mask layer 104 of first area I, exposes the first fin 101 sidewall surfaces and top surface; Remove described first photoresist layer 105.
Dry etch process or wet-etching technology etching is adopted to remove first mask layer 104 of first area I.
In the present embodiment, adopt dry etch process etching to remove first mask layer 104 of first area I, the technological parameter of described dry etch process is: etching gas comprises CHF
3and CF
4, CHF
3gas flow be 10sccm to 100sccm, CH
4gas flow be 10sccm to 100sccm, etching cavity pressure be 1 holder to 50 hold in the palm, etching cavity power is 100 watts to 2000 watts.
Please refer to 7, form the first separator 106 at described first fin 101 top surface and sidewall surfaces.
The material of described first separator 106 is silica or silicon oxynitride.Etching technics is different to the etch rate of the first fin 101 to the etch rate of the first separator 106, and the etch rate of etching technics to the first separator 106 is different from the etch rate of the first intrinsic layer to follow-up formation, therefore described first separator 106 plays the effect of protection first fin 101; Follow-up when etching removal the first intrinsic layer, described first separator 106 plays the effect of etching stop layer, prevent follow-up etch removal the first intrinsic layer time etching is caused to the first fin 101, to keep the dimensional integrity of the first fin 101, keep the integrality of the first doped region of follow-up formation simultaneously, improve the electric property of the fin field effect pipe formed.
Simultaneously, owing to forming the first separator 106 at the first fin 101 top and sidewall surfaces, N-type ion in follow-up first impurity layer or P type ion are after passing through described first separator 106, just can diffuse in the first fin 101, prevent N-type ion or P type ion diffuse from entering the degree of depth of the first fin 101 excessively dark.
Due to follow-up after the first separator 106 surface forms the first impurity layer, the N-type ion in the first impurity layer or P type ion can diffuse in the first fin 101 by described first separator 106; If the thickness evenness of the first separator 106 is poor, in first impurity layer of then follow-up formation, to enter the distance of the evolving path in the first fin 101 different for the N-type ion in each region or P type ion diffuse, and the first doped region formed the first fin 101 in can be caused to be that non-conformal is adulterated.Therefore, the present embodiment requires that the thickness evenness of the first separator 106 formed is good.
In order to obtain the first good separator 106 of thickness evenness, the present embodiment adopts atom layer deposition process or oxidation technology to form described first separator 106, according to the characteristic of atom layer deposition process, the first separator 106 of formation is also covered in isolation structure 103 surface and the first mask layer 104 surface.
As a specific embodiment, the technological parameter of described atom layer deposition process is: reacting gas comprises silicon source gas and oxygen source gas, and reacting gas also comprises current-carrying gas, and wherein, silicon source gas is SiH
4, SiH
2cl
2, SiHCl
3or Si
2cl
6, oxygen source gas is O
2or O
3, current-carrying gas is N
2or Ar, silicon source gas flow is 100sccm to 5000sccm, and oxygen source gas flow is 100sccm to 2000sccm, and current-carrying gas flow is 100sccm to 5000sccm, and reaction chamber temperature is 50 degree to 450 degree, and reaction chamber pressure is that 1 holder to 200 is held in the palm.
In other embodiments, in order to obtain the first good separator of thickness evenness, oxidation technology can also be adopted to form described first separator, described oxidation technology is remote plasma (remoteplasma) oxidation or decoupled plasma (decoupleplasma) oxidation, wherein remote plasma oxidation technology is for after reaction chamber produces plasma oxygen outward, by carrier gas or other modes, described plasma oxygen is introduced in reaction chamber, thus oxidation the first fin top surface and sidewall surfaces, the first separator is formed at the first fin top surface and sidewall surfaces.
In remote plasma oxidation technology or decoupled plasma oxidation technology, avoid producing plasma in reaction chamber, the plasma contacted with the first fin portion surface is gentleer, can reduce the damage that plasma causes the first fin; And, because the plasma introduced in reaction chamber is 3 D stereo, and the first fin is also 3-D solid structure, the first separator of formation can be made to be uniformly distributed in the first fin portion surface, be conducive to making the even concentration of follow-up formation first doped region to distribute.
As a specific embodiment, when adopting decoupled plasma oxidation technology to form the first separator, the technological parameter of described decoupled plasma oxidation technology is: reacting gas comprises oxygen source gas, and described oxygen source gas is O
2or O
3in one or both, reaction gas flow is 20sccm to 2000sccm, power is 50 watts to 3000 watts, duty ratio is 5% to 100%, reaction chamber pressure is 5 millitorr to 100 millitorrs, reaction duration is 20 seconds to 300 seconds, and can also pass into diluent gas in reaction chamber, described diluent gas is He or Ar.
In other embodiments, deionized water ozoniferous can also be adopted to carry out immersion treatment to described first fin, because ozone activity is in deionized water higher, at described first fin portion surface oxidation formation first separator.If the ozone ion mass percent in deionized water ozoniferous is too low, then the oxidizability of deionized water ozoniferous is poor, and being oxidized the first fin, to form the difficulty of the first separator larger; If the ozone ion mass percent in deionized water ozoniferous is too high, then the oxidizability of deionized water ozoniferous is excessively strong, easily causes over oxidation first fin; For this reason, when adopt deionized water ozoniferous be oxidized the first fin form the method for the first separator time, in described deionized water ozoniferous, ozone concentration is 20ppm to 100ppm.
Wherein, ppm represents the quality of contained solute in the solution of 1,000,000 parts of unit masses, and a few millionths is just called several ppm, ppm=(quality of the quality/solution of solute) * 1000000.
If the thickness of the first separator 106 is excessively thin, follow-up when etching removal the first intrinsic layer, the first separator 106 is easily all etched removal, causes the first fin 101 to be exposed, causes etching technics to cause etching to the first fin; If the thickness of the first separator 106 is blocked up, the difficulty that the N-type ion in the first impurity layer of follow-up formation or P type ion diffuse enter in the first fin 101 is excessive.
The above analysis, in the present embodiment, the thickness of the first separator 106 is 5 dust to 10 dusts.
Please refer to Fig. 8, form the first impurity layer 107 on described first separator 106 surface.
In other embodiments, when the first separator is only positioned at the first fin top surface and sidewall surfaces, then described first impurity layer is also covered in isolation structure surface and the first mask layer surface.
In described first impurity layer 107, there is the atom identical with the first fin 101 material, the material implementing the first fin 101 due to this is identical with the material of substrate 100, the material of the first fin 101 is silicon, therefore in described first impurity layer 107, there is silicon atom, in described first impurity layer 107, can also germanium atom be had.
Also have N-type ion or P type ion in described first impurity layer 107, wherein, described N-type ion is P, As or Sb, and described P type ion is B, Ga or In.Described first impurity layer 107 for follow-up in the first fin 101 formed the first doped region N-type ion or P type ion are provided.
The present embodiment for first area I for PMOS area does exemplary illustrated, then in the first impurity layer 107 material, there is P type ion in the present embodiment, for described P type ion for B does exemplary illustrated, the material of described first impurity layer 107 is the silicon of boron-doping or the SiGe of boron-doping, and described first impurity layer 107 material is single phase material or many crystalline material.
The reason in the first impurity layer 107 with the atom identical with the first fin 101 material is: the material of the first fin 101 is silicon, germanium, SiGe, carborundum or GaAs, atomic radius and the boron atomic radius of the material of the first fin 101 are comparatively approximate, therefore the integrality of the crystal growth of the first impurity layer 107 can be ensured when formation the first impurity layer 107, the defects such as the hole as far as possible in minimizing first impurity layer 107, improve the uniformity of B ion concentration distribution in the first impurity layer 107, thus improve the ion concentration distribution uniformity of the doped region of follow-up formation.
In order to make the Doped ions concentration range in first of follow-up formation each region of doping consistent, in the present embodiment first impurity layer 107, each region B ion concentration should be uniformly distributed, Doped ions concentration in the first fin 101 region preventing from causing described region corresponding because some region B ion concentration is higher is high, and the degree of depth of doping is darker.
For this reason, the present embodiment adopts low-pressure chemical vapor deposition (LPCVD) technique to form described first impurity layer 107, because in the reaction chamber of low-pressure chemical vapor deposition process, pressure is lower, under the condition that pressure is lower, the mean free path of the gaseous molecular of reacting gas (under certain conditions, gas molecule between double collision can by the mean value of each section of free path) increase, reacting gas in reaction chamber can reach the homogeneous object of concentration fast, eliminate the problem of the boron ion concentration distribution inequality brought by the phase concentrations gradient of boron source gas, make the boron ion concentration uniformity in the first impurity layer 107 formed high.
As a specific embodiment, the material of the first impurity layer 107 is the silicon of boron-doping, low-pressure chemical vapor deposition process is adopted to form described first impurity layer 107, the technological parameter of described low-pressure chemical vapor deposition process is: reacting gas comprises silicon source gas and boron source gas, wherein, silicon source gas is SiH
4, SiH
2cl
2or SiHCl
3, boron source gas is BH
3or B
2h
6, silicon source gas flow is 100sccm to 2000sccm, and boron source gas flow is 100sccm to 2000sccm, and deposition reaction chamber pressure is that 5 holders to 100 are held in the palm, and deposition reaction chamber temp is 400 degree to 800 degree.
In the present embodiment, the thickness of described first impurity layer 107 is 50 dust to 300 dusts, and in the first impurity layer 107, B atomic concentration is 1E21atom/cm
3to 5E25atom/cm
3.
Please refer to Fig. 9, first annealing in process 108 is carried out to described substrate 100, the P type ion diffuse in the first impurity layer 107 (please refer to Fig. 8) is made to enter in the first fin 101, in the first fin 101, form the first doped region 109, and the first impurity layer 107 is converted into the first intrinsic layer 110.
Described first doped region 109 is light doping section or well region.
The thickness evenness of the first separator 106 formed due to the present embodiment is good, and therefore to enter the evolving path of the first fin 101 consistent for the boron ion diffuse in the first each region of impurity layer 107; And the boron ion concentration in the first each region of impurity layer 107 is uniformly distributed, therefore in the first doped region 109, the boron ion concentration in each region reaches unanimity, thus form the first doped region 109 of conformal doping, avoid, because each region in the first doped region 109 has the poor harmful effect caused of larger boron ion concentration, optimizing the electric property of the fin field effect pipe formed.
Further, this embodiment avoids the decrystallized problem that ion implantation technology is brought, make the first fin 101 maintain higher performance.
Simultaneously, owing to being formed with the first separator 106 between the first impurity layer 107 and the first fin 101, B ion in first impurity layer 107 is by just diffusing in the first fin 101 after described first separator 106, the existence of described first separator 106, can prevent B ion diffuse from entering the degree of depth of the first fin 101 excessively dark, with the demand of first doped region 109 more shallow (shallow) of satisfied formation.
After experience first annealing in process 108, B ion diffuse in first impurity layer 107 enters in the first fin 101, in first impurity layer 107, the content of remaining B ion is considerably less does not even contain B ion, therefore after experience first annealing in process 108, first impurity layer 107 is converted into the first intrinsic layer 110, the material of described first intrinsic layer 110 is silicon or SiGe, can also containing a small amount of B ion in the material of described first intrinsic layer 110.
In the present embodiment, after described first impurity layer 107 of formation, carry out the first annealing in process 108, make the boron ion diffuse in the first impurity layer 107 enter in the first fin 101, in the first fin 101, form the first doped region 109.
Described first annealing in process 108 comprises one annealing steps or multiple tracks annealing steps; The technique of described first annealing in process 108 is one or more in spike annealing, Millisecond annealing or solid phase epitaxial regrowth annealing process.
In the present embodiment, the technique of described first annealing in process 108 is solid phase epitaxial regrowth (SPER, SolidPhaseEpitaxialRecrystallization) anneal, the technological parameter of described solid phase epitaxial regrowth annealing is: annealing temperature is 400 degree to 650 degree, annealing pressure is that 1 holder to 760 is held in the palm, anneal duration is 1min to 120min, at N
2or carry out under atmosphere of inert gases.
Due to the annealing temperature of solid phase epitaxial regrowth annealing process relatively low (being 450 degree to 600 degree), less to the harmful effect of the electric property of fin field effect pipe.
In other embodiments, the technique of the first annealing in process be spike annealing or Millisecond annealing time, the annealing temperature of the first annealing in process is 750 degree to 900 degree.
In other embodiments, also the first annealing in process can be carried out while formation first impurity layer, namely original position (in-situ) annealing is carried out when formation the first impurity layer, make while formation first impurity layer, the N-type ion in established first impurity layer or P type ion diffuse enter in the first fin.
Please refer to Figure 10, with described first separator 106 for etching stop layer, etching removes described first intrinsic layer 110 (please refer to Fig. 9).
Material due to the first intrinsic layer 110 is silicon or SiGe, and boron ion concentration in the first intrinsic layer 110 is considerably less does not even have, therefore the material character of described first intrinsic layer 110 and the material character of the first fin 101 more close, etching technics is almost identical with to the etch rate of the first fin 101 to the etch rate of the first intrinsic layer 110.And the etch rate of etching technics to etch rate comparison first intrinsic layer 110 of the first separator 106 is little many, therefore after etching exposes the first separator 106, described etching technics stops, thus can prevent described etching technics from after etching first intrinsic layer 110, continuing etching first fin 101, keep the integrality of the first fin 101 size, and keep the integrality of the first doped region 109, prevent from causing etching to the first doped region 109, improve the electric property of fin field effect pipe.
If the first intrinsic layer 110 is located immediately at the first fin 101 top and sidewall surfaces, then described etching technics is after etching removal first intrinsic layer 110, can cause etching to the first fin 101 come out, and causes the first fin 101 size to reduce; Further, if described etching technics causes etching to the first fin 101, so part or all of first doped region 109 also can be etched removal, affects the performance of the first doped region 109, thus affects electric property and the reliability of fin field effect pipe.
Etching technics described in the present embodiment is wet-etching technology, and as a specific embodiment, the etch liquids of described wet-etching technology is Tetramethylammonium hydroxide (TMAH) or ammoniacal liquor.
In other embodiments, also dry etch process etching can remove described first intrinsic layer, such as, adopt reactive ion etching process, the etching gas of described reactive ion etching process comprises HBr, Cl
2or HCl.
Please refer to Figure 11, etching removes described first separator 106 (please refer to Figure 10), until expose the first fin 101 top and sidewall surfaces; Etching removes described first mask layer 104 (please refer to Figure 10).
In the present embodiment, adopt wet-etching technology etching to remove described first separator 106, the etch liquids of wet-etching technology is hydrofluoric acid solution, and wherein, the volume ratio of hydrogen fluoride and deionized water is 1:300 to 1:700.
In other embodiments, dry etch process also can be adopted to etch and to remove described first separator.
In the present embodiment, adopt wet-etching technology etching to remove described first mask layer 104, the etch liquids of wet-etching technology is hot phosphoric acid solution, and wherein, the mass percent of phosphoric acid is 65% to 85%, and solution temperature is 80 degree to 120 degree.
In other embodiments, dry etch process also can be adopted to etch and to remove described first mask layer.
Please refer to Figure 12, form the second mask layer 111 in isolation structure 103 surface of described first area I, the first fin 101 top and sidewall surfaces.
The forming step of described second mask layer 111 comprises: form the second original mask layer being covered in the first fin 101 top and sidewall surfaces, the second fin 102 top and sidewall surfaces and isolation structure 103 surface; Patterned second photoresist layer is formed on the second original mask layer surface of described first area I; With described patterned second photoresist layer for mask, etching removes the second original mask layer being positioned at second area II, forms the second mask layer 111 in isolation structure 103 surface of first area I, the first fin 101 top and sidewall surfaces.
Please refer to Figure 13, form the second separator 112 at described second fin 102 top surface and sidewall surfaces; Form the second impurity layer 113 on described second separator 112 surface, and described second impurity layer 113 is also covered in isolation structure 103 surface and the second mask layer 111 surface.
The material of described second separator 112 and formation method with reference to the material of the first separator 106 and formation method, can not repeat them here.
Second impurity layer 113 has the atom identical with the second fin 102 material atom, therefore has silicon atom in described second impurity layer 113, and also has N-type ion or P type ion in the second impurity layer 113.
The present embodiment is for second area II for NMOS area does exemplary illustrated, then have N-type ion in the second impurity layer 113, described N-type ion is P, As or Sb, the present embodiment with the N-type ion in described second impurity layer 113 for P does exemplary illustrated.
The material of the second impurity layer 113 is mix the silicon of phosphorus or mix the carborundum of phosphorus, and the thickness of the second impurity layer 113 is 50 dust to 300 dusts.
Low-pressure chemical vapor deposition process is adopted to form described second impurity layer 113, specifically can with reference to the formation method of aforementioned first impurity layer, in the second impurity layer 113 that the present embodiment is formed, the even concentration of the phosphonium ion in each region is high, is conducive to the second doped region of the conformal doping of follow-up formation.
Please refer to Figure 14, second annealing in process 114 is carried out to described substrate 100, the N-type ion diffuse in the second impurity layer 113 (please refer to Figure 13) is made to enter in the second fin 102, in the second fin 102, form the second doped region 115, and the second impurity layer 113 is converted into the second intrinsic layer 116.
Described second doped region 115 is light doping section or well region.
The technique of described second annealing in process 114 can with reference to the technique of aforementioned first annealing in process.
In the second annealing in process 114 process, the P ion in the second impurity layer 113 diffuses in the second fin 102 by the second separator 112, in the second fin 102, form the second doped region 115; Because the P ion concentration distribution in the second impurity layer 113 is even, and the second separator 112 has uniform thickness, and in the second doped region 115 therefore formed, the concentration range in each region is consistent, forms the second doped region 115 of conformal doping.
The material of described second intrinsic layer 116 is silicon or carborundum, can also have a small amount of P ion in described second intrinsic layer 116.
Please refer to Figure 15, with described second separator 112 for etching stop layer, etching removes described second intrinsic layer 116 (please refer to Figure 14); Etching removes described second separator 112 (please refer to Figure 14), until expose the second fin 102 top and sidewall surfaces; Etching removes described second mask layer 111 (please refer to Figure 14).
The technique that etching removes described second intrinsic layer 116, second separator 112, second mask layer 111 respectively with reference to the technique of aforementioned etching removal first intrinsic layer, the first mask layer, can not repeat them here.
The technical scheme of the formation method of fin field effect pipe provided by the invention has the following advantages:
First, form separator at fin sidewall and top surface, and the etch rate of etching technics to separator is different from the etch rate to fin; Form impurity layer in insulation surface, in described impurity layer, there is the atom identical with fin material, and also there is in described impurity layer N-type ion or P type ion; Annealing in process is carried out to substrate, the N-type ion in impurity layer or P type ion is made to diffuse in fin by separator, doped region is formed in fin, and impurity layer is converted into intrinsic layer, in corresponding intrinsic layer, there is the atom identical with fin material atom, and the content of N-type ion in intrinsic layer or P type ion is considerably less does not even exist, therefore the material character of described intrinsic layer and fin material character are closely, and the etch rate of etching technics to intrinsic layer and the etch rate to fin are closely.And the present invention is formed with separator between intrinsic layer and fin, and the etch rate of etching technics to separator is different from the etch rate to fin, therefore when etching removal intrinsic layer, described separator plays the effect of etching stop layer, prevent etching the etching technics removing intrinsic layer and etching is caused to fin, keep the integrality of fin size, and etching is caused in the doped region avoided being formed in fin, maintain the integrality of doped region, thus improve electric property and the reliability of fin field effect pipe.
Secondly, the embodiment of the present invention adopts the N-type ion in impurity layer or P type ion to diffuse into by separator the method that fin forms doped region, because N-type ion or P type ion are by just diffusing in fin after separator, compared with prior art, it is more shallow that the doped region that the embodiment of the present invention is formed can be done.Further, the method for the formation doped region provided by the embodiment of the present invention, avoids the decrystallized problem that ion implantation technology is brought, and compared with prior art, the ion concentration distribution of the doped region that the embodiment of the present invention is formed evenly.
Again, the embodiment of the present invention adopts low-pressure chemical vapor deposition process to form impurity layer, under environment under low pressure, the mean free path of the gaseous molecular of reacting gas is larger, the reacting gas concentration in reaction chamber is made to reach uniform concentration distribution state fast, thus the even concentration of the N-type ion improved in the impurity layer formed or P type ion, and then make formation doped region CONCENTRATION DISTRIBUTION evenly, improve further the electric property of fin field effect pipe.
Finally, the thickness of embodiment of the present invention separator is 5 dust to 10 dusts, has both ensured the follow-up effect playing etching stop layer, avoids again the problem that the doped region of causing because separation layer thickness is blocked up is excessively shallow.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (20)
1. a formation method for fin field effect pipe, is characterized in that, comprising:
There is provided substrate, described substrate surface is formed with some discrete fins;
Form separator at described fin sidewall and top surface, and the etch rate of etching technics to separator is different from the etch rate to fin;
Form impurity layer in described insulation surface, in described impurity layer, there is the atom identical with fin material, and also there is in described impurity layer N-type ion or P type ion;
Annealing in process is carried out to described substrate, makes the N-type ion in impurity layer or P type ion diffuse in fin by separator, in fin, form doped region, and impurity layer is converted into intrinsic layer;
With described separator for etching stop layer, etching removes described intrinsic layer;
Etching removes described separator, until expose fin top and sidewall surfaces.
2. the formation method of fin field effect pipe as claimed in claim 1, it is characterized in that, the material of described intrinsic layer is silicon, SiGe or carborundum.
3. the formation method of fin field effect pipe as claimed in claim 1, it is characterized in that, the material of described separator is silica.
4. the formation method of fin field effect pipe as claimed in claim 1, it is characterized in that, the thickness of described separator is 5 dust to 10 dusts.
5. the formation method of fin field effect pipe as claimed in claim 3, is characterized in that, adopts ald or oxidation technology to form described separator.
6. the formation method of fin field effect pipe as claimed in claim 5, is characterized in that, adopt deionized water ozoniferous to carry out immersion treatment to described fin, and described fin portion surface oxidation is formed described separator.
7. the formation method of fin field effect pipe as claimed in claim 6, it is characterized in that, in described deionized water ozoniferous, ozone concentration is 20ppm to 100ppm.
8. the formation method of fin field effect pipe as claimed in claim 5, it is characterized in that, the technological parameter of described atom layer deposition process is: reacting gas comprises silicon source gas and oxygen source gas, and reacting gas also comprises current-carrying gas, and wherein, silicon source gas is SiH
4, SiH
2cl
2, SiHCl
3or Si
2cl
6, oxygen source gas is O
2or O
3, current-carrying gas is N
2or Ar, silicon source gas flow is 100sccm to 5000sccm, and oxygen source gas flow is 100sccm to 2000sccm, and current-carrying gas flow is 100sccm to 5000sccm, and reaction chamber temperature is 50 degree to 450 degree, and reaction chamber pressure is that 1 holder to 200 is held in the palm.
9. the formation method of fin field effect pipe as claimed in claim 5, is characterized in that, described oxidation technology is remote plasma oxidation or decoupled plasma oxidation.
10. the formation method of fin field effect pipe as claimed in claim 1, it is characterized in that, the thickness of described impurity layer is 50 dust to 300 dusts.
The formation method of 11. fin field effect pipes as claimed in claim 1, it is characterized in that, described N-type ion is P, As or Sb, and described P type ion is B, Ga or In.
The formation method of 12. fin field effect pipes as claimed in claim 11, it is characterized in that, the material of described impurity layer is mix the silicon of P type ion or mix the SiGe of P type ion.
The formation method of 13. fin field effect pipes as claimed in claim 12, it is characterized in that, when the material of described impurity layer is the silicon of boron-doping, in impurity layer, boron atomic concentration is 1E21atom/cm
3to 5E25atom/cm
3.
The formation method of 14. fin field effect pipes as claimed in claim 11, it is characterized in that, the material of described impurity layer is the silicon of doped type N ion or the carborundum of doped type N ion.
The formation method of 15. fin field effect pipes as claimed in claim 11, is characterized in that, adopts low-pressure chemical vapor deposition process to form described impurity layer.
The formation method of 16. fin field effect pipes as claimed in claim 15, it is characterized in that, the deposition reaction chamber temp of described low-pressure chemical vapor deposition process is 400 degree to 800 degree, and deposition reaction chamber pressure is that 5 holders to 100 are held in the palm.
The formation method of 17. fin field effect pipes as claimed in claim 1, is characterized in that, adopts Tetramethylammonium hydroxide or ammoniacal liquor etching to remove described intrinsic layer.
The formation method of 18. fin field effect pipes as claimed in claim 1, is characterized in that, in the process forming described impurity layer or after the described impurity layer of formation, carries out described annealing in process.
The formation method of 19. fin field effect pipes as claimed in claim 18, is characterized in that, the technique of described annealing in process is one or more in the annealing of spike annealing, Millisecond annealing or solid phase epitaxial regrowth.
The formation method of 20. fin field effect pipes as claimed in claim 19, is characterized in that, the technological parameter of described solid phase epitaxial regrowth annealing is: annealing temperature is 400 degree to 650 degree, and annealing pressure is 1 holder to 760 holder, and anneal duration is 1min to 120min, at N
2or carry out under atmosphere of inert gases.
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| CN107785264A (en) * | 2016-08-26 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN108122758A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN108630609A (en) * | 2017-03-20 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | A kind of manufacturing method of semiconductor devices |
| CN108962753A (en) * | 2017-05-19 | 2018-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109309005A (en) * | 2017-07-27 | 2019-02-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113013035A (en) * | 2019-12-20 | 2021-06-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN107785264A (en) * | 2016-08-26 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor devices |
| CN107785264B (en) * | 2016-08-26 | 2020-05-08 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN108122758A (en) * | 2016-11-30 | 2018-06-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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| CN108630609B (en) * | 2017-03-20 | 2021-04-23 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| CN113013035A (en) * | 2019-12-20 | 2021-06-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113013035B (en) * | 2019-12-20 | 2023-07-14 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113764275A (en) * | 2020-06-03 | 2021-12-07 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
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