CN103633025A - Method of forming a complementary metal-oxide semiconductor tube - Google Patents

Method of forming a complementary metal-oxide semiconductor tube Download PDF

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CN103633025A
CN103633025A CN201210299231.8A CN201210299231A CN103633025A CN 103633025 A CN103633025 A CN 103633025A CN 201210299231 A CN201210299231 A CN 201210299231A CN 103633025 A CN103633025 A CN 103633025A
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layer
stress
semiconductor substrate
grid
grid structure
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CN103633025B (en
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陈振兴
叶彬
何凤英
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Abstract

Disclosed is a method of forming a complementary metal-oxide semiconductor tube, the method comprising providing a semiconductor substrate having a first region and a second region that are adjacent to each other; forming a first gate structure on the surface of the first region of the semiconductor substrate; forming a second gate structure on the surface of the second region of the semiconductor substrate; forming, on the surfaces of the semiconductor substrate, the first gate structure and the second gate structure, a first stress oxide layer and a first stress nitride layer disposed on the surface of the first stress oxide layer, and conducting first thermal annealing; after the first thermal annealing, removing the first stress nitride layer and the first stress oxide layer on the top surfaces of the first gate structure and the second gate structure; and then, forming a third mask layer on the surfaces of the semiconductor substrate, the first gate structure and the second gate structure to form a stress layer. The formed semiconductor device is stable in performance.

Description

The formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) pipe (Complementary Metal-Oxide-Semiconductor, CMOS) has become semiconductor device conventional in integrated circuit.Described CMOS pipe comprises: P-type mos pipe (PMOS) and N-type MOS (metal-oxide-semiconductor) transistor (NMOS).
Along with the raising of component density and the integrated level of semiconductor device, the grid size of PMOS pipe or NMOS pipe becomes than in the past shorter; Yet the grid size of PMOS pipe or NMOS pipe shortens and can produce short-channel effect, and then produces leakage current, affects the electric property of CMOS pipe.Prior art mainly, by improving the stress of transistor channel region, to improve carrier mobility, and then improves transistorized drive current, reduces the leakage current in transistor.
The method that prior art improves the stress of PMOS pipe or NMOS pipe channel region is to form stressor layers in the source/drain region of PMOS pipe or NMOS pipe; Wherein, the material of the transistorized stressor layers of PMOS is SiGe (SiGe), the compression forming because of lattice mismatch between silicon and SiGe, thus improve the transistorized performance of PMOS; The material of the stressor layers of NMOS pipe is carborundum (SiC), the tension stress forming because of lattice mismatch between silicon and carborundum, thereby the performance of raising nmos pass transistor.
Yet, the tension stress that forms stressor layers in the source/drain region of NMOS pipe and improve is limited, raising to CMOS performance is less, therefore, prior art is again at NMOS pipe area applications stress memory technique (Stress Memoriztion Technique, SMT), make NMOS pipe in forming process, in channel region, retain stress.
Yet while adopting stress memory technique in the territory, nmos area of CMOS pipe, formed CMOS pipe unstable properties, easily produces leakage current.
More CMOS (Complementary Metal Oxide Semiconductor) pipes and formation technique thereof please refer to the U.S. patent documents that the patent No. is US8101480B1.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe, makes the stable performance of formed CMOS (Complementary Metal Oxide Semiconductor) pipe.
For addressing the above problem, the invention provides a kind of formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe, comprising: Semiconductor substrate is provided, and described Semiconductor substrate has adjacent first area and second area; Surface, first area in described Semiconductor substrate forms first grid structure, and the surface of described first grid structure has the first mask layer; Second area surface in described Semiconductor substrate forms second grid structure, and the surface of described second grid structure has the second mask layer; The the first stress nitride layer that forms the first stress oxidation layer and be positioned at described the first stress oxidation layer surface at described Semiconductor substrate, first grid structure and second grid body structure surface; After forming the first stress oxidation layer and the first stress nitride layer, carry out thermal annealing for the first time; After thermal annealing for the first time, remove the first stress nitride layer; After removing the first stress nitride layer, remove the first stress oxidation layer on described first grid structure and second grid structural top surface, and expose the first mask layer; After exposing the first mask layer, at described Semiconductor substrate, first grid structure and second grid body structure surface, form the 3rd mask layer, described the 3rd mask layer exposes the semiconductor substrate surface of second grid structure both sides; Described the 3rd mask layer of take is mask, in the Semiconductor substrate of described second grid structure both sides, forms stressor layers; After forming stressor layers, remove the first mask layer, the second mask layer and the 3rd mask layer.
Alternatively, the method for the first stress oxidation layer on described removal first grid structural top surface is: after removing the first stress nitride layer, on described the first stress oxidation layer surface, form photoresist layer; Return photoresist layer described in etching, until expose the first stress oxidation layer on first grid structure and second grid structural top surface; After returning etching, take described photoresist layer as mask, remove the first stress oxidation layer on described first grid structure and second grid structural top surface; After removing the first stress oxidation layer on described first grid structure and second grid structural top surface, remove photoresist layer.
Alternatively, take described photoresist layer as mask, the technique of the first stress oxidation layer on described removal first grid structure and second grid structural top surface is dry etch process or wet-etching technology.
Alternatively, the technique of described removal photoresist layer is that one or both in cineration technics and etching technics are used in combination.
Alternatively, before forming photoresist layer, on described the first stress oxidation layer surface, form anti-reflecting layer.
Alternatively, described thermal annealing for the first time comprises rapid thermal annealing, hot furnace annealing or laser pulse annealing, and the temperature of described thermal annealing is for the first time 600 degrees Celsius-1200 degrees Celsius.
Alternatively, the material of described the first stress oxidation layer is silica or silicon oxynitride, and the material of described the first stress nitride layer is silicon nitride.
Alternatively, also comprise: before thermal annealing for the first time, remove the Semiconductor substrate of second area and the first stress oxidation layer of second grid body structure surface and the first stress nitride layer.
Alternatively, also comprise: after removing the first mask layer, the second mask layer and the 3rd mask layer, semiconductor substrate surface in described first grid structure both sides forms the 3rd side wall, and the semiconductor substrate surface in described second grid structure both sides forms the 4th side wall; In the Semiconductor substrate of described the 3rd side wall both sides, form the first source/drain region; In the Semiconductor substrate of described the 4th side wall both sides, form the second source/drain region; After forming the first source/drain region and the second source/drain region, the second stress nitride layer that forms the second stress oxidation layer and be positioned at described the second stress oxidation layer surface at described Semiconductor substrate, first grid structure and second grid body structure surface; After forming the second stress oxidation layer and the second stress nitride layer, carry out thermal annealing for the second time; After thermal annealing for the second time, remove the second stress oxidation layer and the second stress nitride layer.
Alternatively, described the first source/drain region is N-shaped, and described the second source/drain region is p-type.
Alternatively, the material of described the second stress oxidation layer is silica or silicon oxynitride, and the material of described the second stress nitride layer is silicon nitride.
Alternatively, the method for described formation stressor layers is: described the 3rd mask layer of take is mask, adopts etching technics to form opening in the Semiconductor substrate of described second grid structure both sides; In described opening, adopt selective epitaxial depositing operation to form stressor layers, the material of described stressor layers is SiGe.
Alternatively, the sidewall of described opening and semiconductor substrate surface are " Σ " shape.
Alternatively, the material of described the first mask layer, the second mask layer and the 3rd mask layer is silicon nitride.
Compared with prior art, technical scheme of the present invention has the following advantages:
When form the first stress oxidation layer and the first stress nitride layer at described first grid body structure surface, and after carrying out for the first time thermal annealing, remove the first stress nitride layer, and the first stress oxidation layer on first grid structural top surface, can make the 3rd mask layer of follow-up formation directly be formed at the first mask layer and the second mask layer surface, and by the first stress oxidation layer, mutually isolate between Semiconductor substrate and described the 3rd mask layer; In follow-up removal the 3rd mask layer, described the first mask layer and the second mask layer can be removed simultaneously, and described Semiconductor substrate obtains the protection of described the first stress oxidation layer in technical process and can not sustain damage; The stable performance of formed CMOS (Complementary Metal Oxide Semiconductor) pipe, and it is simple to form technique.
Accompanying drawing explanation
Fig. 1 to Fig. 5 is the cross-sectional view of the forming process of the CMOS pipe that in prior art, territory, nmos area adopts stress memory technique;
Fig. 6 to Figure 17 is the cross-sectional view of the forming process of CMOS (Complementary Metal Oxide Semiconductor) pipe described in the embodiment of the present invention.
Embodiment
As stated in the Background Art, while adopting stress memory technique in the territory, nmos area of CMOS pipe, formed CMOS pipe unstable properties, easily produces leakage current.
The existing forming process of the CMOS pipe of stress memory technique that adopts in territory, nmos area please refer to shown in Fig. 1 to Fig. 5, comprising:
Please refer to Fig. 1, Semiconductor substrate 100 is provided, described Semiconductor substrate 100 has adjacent territory, nmos area 101 and PMOS region 102, between territory, described nmos area 101 and PMOS region 102, there is fleet plough groove isolation structure 103,101 surfaces, territory, described nmos area have first grid structure 104, and described PMOS region surface has second grid structure 105; In the Semiconductor substrate 100 of described first grid structure 104 both sides, carry out N-shaped light dope.
Please refer to Fig. 2, after N-shaped light dope, the the first stress nitride layer 107 that forms the first stress oxidation layer 106 and be positioned at described the first stress oxidation layer 106 surface on described Semiconductor substrate 100, first grid structure 104 and second grid structure 105 surfaces, and carry out thermal annealing for the first time.
Please refer to Fig. 3, after thermal annealing for the first time, remove the first stress nitride layer 107(as shown in Figure 2) and the first stress oxidation layer 106(is as shown in Figure 2); Described formation the first stress oxidation layer 106 and the first stress nitride layer 107, thermal annealing and the process of removing the first stress oxidation layer 106 and the first stress nitride layer 107 for the first time, be stress memory technique.
The tension stress that lattice mismatch between described the first stress nitride layer 107, the first stress oxidation layer 106 and Semiconductor substrate 100 produces, by thermal annealing, resided in Semiconductor substrate 100, thereby improved the follow-up carrier mobility that is formed at the NMOS pipe channel region in territory, nmos area 101.
Please refer to Fig. 4, after removing the first stress nitride layer 107 and the first stress oxidation layer 106, on described Semiconductor substrate 100, first grid structure 104 and second grid structure 105 surfaces, form the 3rd mask layer 108, described the 3rd mask layer 108 exposes Semiconductor substrate 100 surfaces of second grid structure 105 both sides, and the material of described the 3rd mask layer 108 is silicon nitride.
Please refer to Fig. 5, take described the 3rd mask layer 108(as shown in Figure 4) be mask, at described second grid, tie the interior formation stressor layers 109 of Semiconductor substrate 100 of 105 structure both sides, and remove described the 3rd mask layer 108; After removing the 3rd mask layer 108, the interior formation of the Semiconductor substrate 100 source/drain region in described first grid structure 104 and second grid structure 105 both sides, thus form CMOS pipe.
It should be noted that, behind formation source/drain region, can again carry out stress memory technique to described first grid structure 104 and second grid structure 105: the second stress nitride layer that forms the second stress oxidation layer and be positioned at described the second stress oxidation layer surface on described Semiconductor substrate 100, first grid structure 104 and second grid structure 105 surfaces, and carry out thermal annealing for the second time; And after thermal annealing for the second time, remove described the second stress oxidation layer and the second stress nitride layer, and stress is resided in the gate electrode of first grid structure 104, further improve the mobility of charge carrier.
The present inventor finds through research, owing to removing the technique of the first stress oxidation layer 106 and the first stress nitride layer 107, it is wet-etching technology, and the etching liquid that etching is removed the first stress oxidation layer 106 is hydrofluoric acid, can cause damage to Semiconductor substrate 100 surfaces, and the lightly doped ion of N-shaped is run off, make easily to make formed CMOS pipe to produce leakage current, cause its service behaviour unstable.
Yet, please refer to Fig. 1, because described first grid structure 104 comprises: first grid dielectric layer 120, be positioned at the first grid electrode layer 121 on first grid dielectric layer 120 surfaces, the first side wall 123 that is positioned at first mask layer 122 on described first grid electrode layer 121 surfaces and is positioned at Semiconductor substrate 100 surfaces of first grid electrode layer 121 both sides, and the material of described the first mask layer 122 is silicon nitride; If after removing the first stress nitride layer 107, retain described the first stress oxidation layer 106, so when follow-up removal the 3rd mask layer 108, described the first mask layer 122 is due to the isolation of the first stress oxidation layer 106, cannot be removed simultaneously, thereby affect the follow-up Implantation to first grid electrode layer 121; And then, need extra technique to remove first mask layer 122 on described first grid electrode layer 121 surfaces, make complex process, increase the time of technological process, and increased cost.
The present inventor after further research, a kind of formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe has been proposed, forming the first stress oxidation layer and the first stress nitride layer, and carry out for the first time after thermal annealing, remove the first stress nitride layer, then remove the first stress oxidation layer on first grid structure second grid structural top surface; The 3rd mask layer of follow-up formation is directly formed at the first mask layer and the second mask layer surface; and Semiconductor substrate and described the 3rd mask layer are isolated mutually by the first stress oxidation layer; thereby when removing the 3rd mask layer; described the first mask layer and the second mask layer are removed simultaneously; and described Semiconductor substrate obtains the protection of described the first stress oxidation layer and can in subsequent technique, not sustain damage; the stable performance of formed CMOS (Complementary Metal Oxide Semiconductor) pipe, and it is simple to form technique.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.Fig. 6 to Figure 17 is the cross-sectional view of the forming process of the CMOS (Complementary Metal Oxide Semiconductor) pipe described in the present embodiment.
Please refer to Fig. 6, Semiconductor substrate 200 is provided, described Semiconductor substrate 200 has adjacent first area 201 and second area 202, between described first area 201 and second area 202, has fleet plough groove isolation structure 203.
Described Semiconductor substrate 200 is used to subsequent technique that workbench is provided, and the material of described Semiconductor substrate 200 is silicon or silicon-on-insulator; The crystal face on described Semiconductor substrate 200 surfaces is (100).
In the present embodiment, described first area 201 is used to form NMOS pipe, and described second area is used to form PMOS pipe; The material of described fleet plough groove isolation structure 203 is silica, and the formation technique of described fleet plough groove isolation structure 203 is well known to those skilled in the art, and therefore not to repeat here.
It should be noted that, the Semiconductor substrate 200 of described first area 201 is before carrying out subsequent technique, through the doping of p-type well region; The Semiconductor substrate 200 of described second area 202 is before carrying out subsequent technique, through the doping of N-shaped well region.
Please refer to Fig. 7, surface, first area 201 in described Semiconductor substrate 200 forms first grid structures 204, and described first grid structure 204 comprises: first grid dielectric layer 220, be positioned at the first grid electrode layer 221 on first grid dielectric layer 220 surfaces, the first side wall 223 that is positioned at first mask layer 222 on described first grid electrode layer 221 surfaces and is positioned at Semiconductor substrate 200 surfaces of first grid electrode layer 221 both sides; Second area 202 surface in described Semiconductor substrate 200 forms second grid structures 205, and described second grid structure 205 comprises: second gate dielectric layer 230, be positioned at the second gate electrode layer 231 on second gate dielectric layer 230 surfaces, the second side wall 233 that is positioned at second mask layer 232 on described second gate electrode layer 231 surfaces and is positioned at Semiconductor substrate 200 surfaces of second gate electrode layer 231 both sides.
The material of described first grid dielectric layer 220 and second gate dielectric layer 230 is silica, the material of described first grid electrode layer 221 and second gate electrode layer 231 is polysilicon, and the material of described the first side wall 223 and the second side wall 233 is one or both combinations in silicon nitride and silica; In the present embodiment, described the first side wall 223 and the second side wall 233 consist of the silicon nitride that is positioned at the silica of described first grid electrode layer 221 and second gate electrode layer 231 both sides and is positioned at described silica outside.
Described first grid structure 204 and second grid structure 205 form simultaneously, save processing step; The formation technique of described first grid structure 204 and second grid structure 205 is: on described Semiconductor substrate 200 surfaces, form gate dielectric membrane, the material of described gate dielectric membrane is silica, and the formation technique of described gate dielectric membrane is chemical vapor deposition method or thermal oxidation technology; On described gate dielectric membrane surface, form gate electrode film, the material of described surface gate electrode is polysilicon, and the formation technique of described gate electrode film is chemical vapor deposition method; At described gate electrode film surface deposition mask film, the material of described mask film is silicon nitride; In the present embodiment, before forming described mask film, at described gate electrode film surface, form gasket film; Mask film, oxide liner film, gate electrode film and gate dielectric membrane described in etching, Semiconductor substrate 200 surfaces in first area 201 form first grid dielectric layer 220, first grid electrode layer 221, the first mask layer 222 and the first laying (not shown) between described first grid electrode layer 221 and the first mask layer 222, described the first laying is formed by gasket film etching, and material is silica; Simultaneously, Semiconductor substrate 200 surfaces at second area 202 form second gate dielectric layer 230, second gate electrode layer 231, the second mask layer 232 and the first laying (not shown) between described second gate electrode layer 231 and the second mask layer 232, described the first laying is formed by gasket film etching, and material is silica; Described the first laying and the second laying, for when follow-up removal the first mask layer 222 and the second mask layer 232, protect the top surface of described first grid electrode layer 221 and second gate electrode layer 231 injury-free.
After etching technics, on described Semiconductor substrate 200, first grid dielectric layer 220, first grid electrode layer 221, the first mask layer 222, second gate dielectric layer 230, second gate electrode layer 231 and the second mask layer 232 surfaces, form side wall film, the material of described side wall film is one or both combinations in silica and silicon nitride; In the present embodiment, described side wall film comprises monox lateral wall film and is positioned at the silicon nitride side wall film of described monox lateral wall film surface; Return side wall film described in etching, form the first side wall 223 and the second side wall 233, in the present embodiment, described the first side wall 223 and the second side wall 233 consist of the monox lateral wall of first grid electrode layer 221 and second gate electrode layer 231 both sides and the silicon nitride side wall in described monox lateral wall outside; Described the first side wall 223 and the second side wall 233, for the mask as light dope technique, can prevent the generation of its effect of short channel, and avoid overlapping electric capacity.
It should be noted that, after forming first grid structure 204 and second grid structure 205, in the Semiconductor substrate 200 of described first grid structure 204 both sides, carry out N-shaped light dope.
Please refer to Fig. 8, the first stress nitride layer 207 that forms the first stress oxidation layer 206 and be positioned at described the first stress oxidation layer 206 surface on described Semiconductor substrate 200, first grid structure 204 and second grid structure 205 surfaces; After forming the first stress oxidation layer 206 and the first stress nitride layer 207, carry out thermal annealing for the first time.
The formation technique of described the first stress nitride layer 207 and the first stress oxidation layer 206 is chemical vapor deposition method; The material of described the first stress nitride layer 207 is silicon nitride, for Semiconductor substrate 200 stress applications to first area 201, and after thermal anneal process, applied stress is resided in Semiconductor substrate 200; The material of described the first stress oxidation layer 206 is silica or silicon oxynitride, for the buffering as between the first stress nitride layer 207 and Semiconductor substrate 200; The thickness of described the first stress oxidation layer 206 is 15-100 dust, and described the first stress nitride layer 207 thickness are 100-600 dust; In the present embodiment, in order to simplify technique, described the first stress nitride layer 207 and the first stress oxidation layer 206 cover Semiconductor substrate 200 surfaces of described first area 201 and second area 202.
In other embodiments, the tension stress applying in order to eliminate described the first stress nitride layer 207, for the harmful effect of Semiconductor substrate 200 that is used to form the second area 202 of PMOS pipe, in deposition, form after the first stress nitride layer 207 and the first stress oxidation layer 206, remove the Semiconductor substrate 200 of second area 202 and the first stress oxidation layer 206 on second grid structure 205 surfaces and the first stress nitride layer 207.
Between described the first stress nitride layer 207 and Semiconductor substrate 200, because lattice mismatch produces stress, described stress comprises the tension stress in horizontal direction, and described tension stress can be transmitted in Semiconductor substrate 200; Follow-up in first area the channel region of the 201 NMOS pipes that form receive after the impact of described tension stress, the mobility of charge carrier improves, formed CMOS (Complementary Metal Oxide Semiconductor) pipe is functional.
Because the lattice mismatch between described the first stress nitride layer 207 and Semiconductor substrate 200 is more serious, the stress that described Semiconductor substrate 200 is produced is larger, if described the first stress nitride layer 207 directly and Semiconductor substrate 200 carry out thermal annealing, can cause damage to Semiconductor substrate 200 surfaces; When described the first stress oxidation layer 206 can make described the first stress nitride layer 207 to Semiconductor substrate 200 stress application, cushion the lattice mismatch between described the first stress nitride layer 207 and Semiconductor substrate 200, avoid damage.
Described thermal annealing for the first time comprises rapid thermal annealing, hot furnace annealing or laser pulse annealing; The temperature of described thermal annealing is for the first time 600 degrees Celsius-1200 degrees Celsius, and protective gas is nitrogen or hydrogen; In the process of thermal annealing for the first time, covering due to described the first stress nitride layer 207, there is recrystallization in described Semiconductor substrate 200, lattice has carried out again arranging, to adapt to the tension stress of described the first stress nitride layer 207 Semiconductor substrate that put on, thereby stress is resided in Semiconductor substrate 200; After follow-up removal the first stress nitride layer 207, in the Semiconductor substrate 200 of recrystallization, still retained stress, thereby make the follow-up channel region that is formed at the NMOS pipe of first area 201 be subject to effect of stress, and then improve the mobility of charge carrier, improved device performance; And the stress residing in Semiconductor substrate 200 is larger, the stress that the channel region of NMOS pipe is subject to is larger, further improves device performance.
Please refer to Fig. 9, after thermal annealing for the first time, remove the first stress nitride layer 207(as shown in Figure 8).
The technique of described removal the first stress nitride layer 207 is dry etching or wet etching, preferably wet-etching technology, and etching liquid is phosphoric acid; Remove after described the first stress nitride layer 207, retain described the first stress oxidation layer 206, described the first stress oxidation layer 206 can protect described Semiconductor substrate 200 surfaces to avoid damage in subsequent technique, thereby reduces the generation of device creepage.
Please refer to Figure 10, after removing the first stress nitride layer, on described the first stress oxidation layer 206 surface, form photoresist film (not shown); Return film described in etching, form photoresist layer 208, until expose the first stress oxidation layer 206 of first grid structure 204 and second grid structure 205 top surfaces.
The formation technique of described photoresist film is spin coating proceeding, and heat-treats, and makes described photoresist layer post bake; Pass through back the photoresist layer 208 of etching technics, when the first stress oxidation layer 206 of follow-up removal first grid structure 204 and second grid structure 205 top surfaces, as mask; While adopting described photoresist layer 208 as mask, during the first stress oxidation layer 206, can not damage described photoresist layer 208 described in follow-up wet etching, protection effect is stronger.
Please refer to Figure 11, after returning etching, the described photoresist layer 208 of take is mask, removes the first stress oxidation layer 206 of described first grid structure 204 and second grid structure 205 top surfaces, and exposes the first mask layer 222 and the second mask layer 232.
The first stress oxidation layer 206 technique of removing described first grid structure 204 and second grid structure 205 top surfaces are dry etching or wet etching, preferably wet-etching technology, and etching liquid is phosphoric acid; When adopting wet-etching technology, described photoresist layer 208, larger with the Etch selectivity between the first mask layer 222 and the second mask layer 232, so the protection of described photoresist layer 208 is respond well.
Please refer to Figure 12, after removing the first stress oxidation layer 206 of described first grid structure 204 and second grid structure 205 top surfaces, remove photoresist layer 208(as shown in figure 11).
The technique of described removal photoresist layer 208 is one or both combinations in cineration technics or wet-etching technology, and the technique of described removal photoresist layer 208 is well known to those skilled in the art, and therefore not to repeat here; The technique of described removal photoresist layer 208 is simple, removes thoroughly, and can not damage remaining the first stress oxidation layer 206, therefore adopts photoresist layer 208 better as the effect of mask.
Remove after the first stress oxidation layer 206 of described first grid structure 204 and second grid structure 205 top surfaces, make the 3rd mask layer of follow-up formation can directly be formed at the surface of the first mask layer 222 and the second mask layer 232; During follow-up removal the 3rd mask layer, described the first mask layer 222 and the second mask layer 232 can be removed simultaneously, avoided described the first mask layer 222 and the second mask layer 232 follow-up to first grid electrode layer 221 and second gate electrode layer 231 carry out Implantation time, cause and stop; In addition, remaining the first stress oxidation layer, when described the 3rd mask layer 209 of follow-up removal, protects described Semiconductor substrate 200 injury-free, has reduced the generation of leakage current, makes device performance stable.
It should be noted that, after removing photoresist layer 208, in the Semiconductor substrate 200 of described second grid structure 205 both sides, carry out p-type light dope.
Please refer to Figure 13, after exposing the first mask layer 222, on described Semiconductor substrate 200, first grid structure 204 and second grid structure 205 surfaces, form the 3rd mask layer 209, described the 3rd mask layer 209 exposes Semiconductor substrate 200 surfaces of second grid structure 205 both sides.
The material of described the 3rd mask layer 209 is silicon nitride, the mask of described the 3rd mask layer 209 when as follow-up formation stressor layers; The formation technique of described the 3rd mask layer 209 is: at described Semiconductor substrate 200, first grid structure 204 and second grid structure 205 surface depositions the 3rd mask film; At described the 3rd mask film surface, form photoresist film, described photoresist film has defined the follow-up correspondence position that need to form stressor layers; Take described photoresist film as the 3rd mask film described in mask etching, form the 3rd mask layer 209.
After forming described the 3rd mask layer, take described photoresist film as the first stress oxidation layer 206 described in mask etching until expose Semiconductor substrate 200, described etching technics is dry etching or wet etching; Because exposed Semiconductor substrate 200 is formed for forming opening in subsequent technique, and described opening is used to form stressor layers, even therefore in the process of the first stress oxidation layer 206 described in etching, Semiconductor substrate 200 is caused to damage, impaired Semiconductor substrate 200 can be removed after forming opening, can not impact the performance of semiconductor device.
Because the material of described the 3rd mask layer 209 is identical with the second mask layer 232 with the first mask layer 222, for silicon nitride, and described the 3rd mask layer 209 is formed at described the first mask layer 222 and the second mask layer 232 surfaces, therefore described the 3rd mask layer 209, the first mask layer 222 and the second mask layer 232 can be removed by same process steps in subsequent technique; Avoided described the first mask layer 222 and the second mask layer 232 in subsequent technique, the Implantation of impact to first grid electrode layer 221 and second gate electrode layer 231.
Please refer to Figure 14, described the 3rd mask layer 209 of take is mask, the interior formation stressor layers 210 of Semiconductor substrate 200 in described second grid structure 205 both sides.
The material of described stressor layers 210 is germanium silicon, and described stressor layers 210, for providing compression to the follow-up channel region that is formed at the PMOS pipe of second area 202, to improve the carrier mobility of PMOS pipe, improves device performance.
The formation technique of described stressor layers 210 is: described the 3rd mask layer 209 of take is mask, and the interior employing etching technics of Semiconductor substrate 200 in described second grid structure 205 both sides forms opening (not shown); In described opening, adopt selective epitaxial depositing operation to form stressor layers 210.
The surface of the sidewall of described opening and Semiconductor substrate 200 forms the (Σ of Sigma, sigma) shape, drift angle on described opening sidewalls is to the interior extension of Semiconductor substrate 200 of described second grid structure 205 belows, make the close together between the adjacent stressor layers 210 of follow-up formation, to put on the stress of channel region of second grid structure 205 belows larger for the stressor layers 210 of follow-up formation, and the performance of formed PMOS pipe improves.
In the present embodiment, the formation step of described opening is: described the 3rd mask layer of take is mask, adopts dry etch process at the interior formation sidewall of the described Semiconductor substrate 200 opening (not shown) vertical with Semiconductor substrate 200 surfaces; After dry etching, adopt opening described in wet etching, make drift angle on described opening sidewalls to the interior extension of Semiconductor substrate 200 of second grid structure 205 belows, form the opening of Sigma's shape.
Described dry etching is anisotropic dry etching, and etching gas is the mist of chlorine, hydrogen bromide or chlorine and hydrogen bromide; Described dry etch process parameter is: the flow of hydrogen bromide is 200sccm ~ 800sccm, the flow of chlorine is 20sccm ~ 100sccm, the flow of inert gas is 50sccm ~ 1000sccm, and the pressure of etching cavity is 2mTorr ~ 200mTorr, and etch period is 15 seconds ~ 60 seconds.
Described wet etching is anisotropic wet etching, and described etching liquid is alkaline solution, and described alkaline solution is potassium hydroxide (KOH), NaOH (NaOH), lithium hydroxide (LiOH), lithium hydroxide ammoniacal liquor (NH 4oH) be one or more combinations in Tetramethylammonium hydroxide (TMAH).
Because the crystal face on described Semiconductor substrate 200 surfaces is (100), and described anisotropic wet etching is very fast perpendicular to Semiconductor substrate 200 surface and the etch rate that is parallel in the direction on Semiconductor substrate 200 surfaces, and etch rate when etching crystal face (111) is the slowest, thereby make the shape of described opening become Sigma's shape; When follow-up, form after stressor layers 210 in described opening, between adjacent stressor layers 210, distance is less, and described stressor layers 210 applies with the stress of channel region larger.
The material of described stressor layers 210 is SiGe, and wherein, the atom percentage concentration of germanium is 1%-50%, preferably 20%-30%; The formation technique of described stressor layers 210 is selective epitaxial depositing operation, and temperature is 500 degrees Celsius-800 degrees Celsius, and air pressure is 1 holder-100 holder, and reacting gas comprises silicon source gas (SiH 4or SiH 2cl 2) and germanium source gas (GeH 4), the flow of described silicon source gas and germanium source gas is 1sccm-1000sccm; The gas of described selective epitaxial depositing operation also comprises HCl and H 2, the flow of described HCl is 1sccm-1000sccm, H 2flow be 0.1slm-50slm.
Please refer to Figure 15, after forming stressor layers 210, remove the first mask layer 222(as shown in figure 14), the second mask layer 232(as shown in figure 14) and the 3rd mask layer 209(as shown in figure 14).
The technique of described removal the first mask layer 222, the second mask layer 232 and the 3rd mask layer 209 is etching technics, preferably wet-etching technology, and etching liquid is phosphoric acid; Due in removing the process of described the 3rd mask layer 209; described the first mask layer 222, the second mask layer 232 and the 3rd mask layer 209 have larger Etch selectivity with respect to remaining the first stress oxidation layer 206; therefore it is injury-free that remaining the first stress oxidation layer 206 can be protected Semiconductor substrate 200 surfaces, makes formed device performance stable.
Please refer to Figure 16, after removing the first mask layer, the second mask layer and the 3rd mask layer, Semiconductor substrate 200 surfaces in described first grid structure 204 both sides form the 3rd side wall 211, on Semiconductor substrate 200 surfaces of described second grid structure 205 both sides, form the 4th side wall 212; The interior formation of Semiconductor substrate 200 the first source/drain region in described the 3rd side wall 210 both sides; The interior formation of Semiconductor substrate 200 the second source/drain region in described the 4th side wall 211 both sides.
The material of described the 3rd side wall 211 and the 4th side wall 212 is one or both combinations in silica and silicon nitride; The formation technique of described the 3rd side wall 211 and the 4th side wall 212 is identical with the formation technique of the first side wall 223 and the second side wall 233, at this, does not repeat.
In one embodiment, before forming the 3rd side wall 211 and the 4th side wall 212, remove the silicon nitride side wall in described the first side wall 223 and the second side wall 233, thereby make the gross thickness of the first side wall 223 and the 3rd side wall 211, and the gross thickness of second side wall 233 and the 4th side wall is more controlled, make formed device performance stable.
The formation technique in described the first source/drain region and the second source/drain region is Implantation; In the Semiconductor substrate 200 of first grid structure 204 and the 3rd side wall 211 both sides and first grid electrode layer 221, carry out Implanted n-Type ion, in the Semiconductor substrate 200 of second grid structure 205 and the 4th side wall 212 both sides and second gate electrode layer 231, inject p-type ion, thereby in first area, 201 form NMOS pipe, at second area 202, form PMOS pipe.
Please refer to Figure 17, after forming the first source/drain region and the second source/drain region, the second stress nitride layer 214 that forms the second stress oxidation layer 213 and be positioned at described the second stress oxidation layer 213 surface on described Semiconductor substrate 200, first grid structure 204 and second grid structure 205 surfaces; After forming the second stress oxidation layer 213 and the second stress nitride layer 214, carry out thermal annealing for the second time.
It should be noted that, after thermal annealing for the second time, remove the second stress oxidation layer 213 and the second stress nitride layer 214(is not shown).
Form described the second stress oxidation layer 213 and the second stress nitride layer 214, and carry out for the second time thermal annealing for tension stress being resided in first grid electrode layer 221, thereby further improve the tension stress that NMOS pipe channel region is subject to, to improve the carrier mobility of the trench area of NMOS pipe.
The material of described the second stress oxidation layer 213 and the second stress nitride layer 214 is identical with the first stress nitride layer with the first stress oxidation layer with formation technique, described thermal anneal process is for the second time with thermal annealing is identical for the first time, identical when the technique of described removal the second stress oxidation layer 213 and the second stress nitride layer 214 is identical with the first stress nitride layer with removal the first stress oxidation layer, at this, do not repeat.
It should be noted that, after removing described the second stress oxidation layer 213 and the second stress nitride layer 214, in described the first source/drain region, the second source/drain region, first grid electrode layer 221 and second gate electrode layer 231 surfaces form electrode layer (not shown), described electrode layer is for as the source/drain region of device and the electrode of gate electrode; The material of described electrode layer is metal silicide (salicide), comprises titanium silicon, nisiloy or cobalt silicon; The formation technique of described electrode layer is: in the first source/drain region, the second source/drain region, first grid electrode layer 221 and second gate electrode layer 231 surfaces form mask layers, described mask layer exposes the first source/drain region, the second source/drain region, first grid electrode layer 221 and second gate electrode layer 231 surfaces; After forming mask layer, in described the first source/drain region, the second source/drain region, first grid electrode layer 221 and the 231 surface selectivity epitaxial depositions of second gate electrode layer form silicon layers; In described silicon surface deposition, form metal level, the material of described metal level is titanium, nickel or cobalt; After forming metal level, carry out thermal annealing, make described metal level and silicon layer reaction, form electrode layer; Remove the remaining metal level of electrode layer surface and mask layer.
After forming electrode layer, in each electrode layer surface, form conductive plunger, described conductive plunger is used for being electrically connected to each electrode layer, thereby the source/drain region of formed CMOS (Complementary Metal Oxide Semiconductor) pipe and gate electrode layer are loaded to bias voltage; The formation technique of described conductive plunger is well known to those skilled in the art, and therefore not to repeat here.
In the present embodiment, when having formed the first stress oxidation layer and the first stress nitride layer, and after carrying out for the first time thermal annealing, remove the first stress oxidation layer at the first stress nitride layer and the first mask layer and the second mask layer top, the 3rd mask layer that makes follow-up formation directly with the first mask layer and the second mask layer, and semiconductor substrate surface is protected by remaining the first stress oxidation layer; When follow-up removal the 3rd mask layer, the first mask layer and the second mask layer are removed simultaneously, thereby have avoided described the first mask layer and the follow-up Implantation to first grid electrode layer and second gate electrode layer of the second mask layer impact; In addition, when removing the 3rd mask layer, Semiconductor substrate is protected by remaining the first stress oxidation layer, has avoided the damage of described semiconductor substrate surface and makes device produce leakage current; Formed device performance is stable.
In sum, when forming the first stress oxidation layer and the first stress nitride layer at described first grid structure second grid body structure surface, and after carrying out for the first time thermal annealing, remove the first stress nitride layer, and the first stress oxidation layer on first grid structure second grid structural top surface, can make the 3rd mask layer of follow-up formation directly be formed at the first mask layer and the second mask layer surface, and Semiconductor substrate is mutually isolated between described the 3rd mask layer by the first stress oxidation layer; In follow-up removal the 3rd mask layer, described the first mask layer and the second mask layer can be removed simultaneously, and described Semiconductor substrate obtains the protection of described the first stress oxidation layer in technical process and can not sustain damage; The stable performance of formed CMOS (Complementary Metal Oxide Semiconductor) pipe, and it is simple to form technique.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection range of technical solution of the present invention.

Claims (20)

1. a formation method for CMOS (Complementary Metal Oxide Semiconductor) pipe, is characterized in that, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate has adjacent first area and second area;
Surface, first area in described Semiconductor substrate forms first grid structure, and the surface of described first grid structure has the first mask layer;
Second area surface in described Semiconductor substrate forms second grid structure, and the surface of described second grid structure has the second mask layer;
The the first stress nitride layer that forms the first stress oxidation layer and be positioned at described the first stress oxidation layer surface at described Semiconductor substrate, first grid structure and second grid body structure surface;
After forming the first stress oxidation layer and the first stress nitride layer, carry out thermal annealing for the first time;
After thermal annealing for the first time, remove the first stress nitride layer;
After removing the first stress nitride layer, remove the first stress oxidation layer on described first grid structure and second grid structural top surface, and expose the first mask layer;
After exposing the first mask layer, at described Semiconductor substrate, first grid structure and second grid body structure surface, form the 3rd mask layer, described the 3rd mask layer exposes the semiconductor substrate surface of second grid structure both sides;
Described the 3rd mask layer of take is mask, in the Semiconductor substrate of described second grid structure both sides, forms stressor layers;
After forming stressor layers, remove the first mask layer, the second mask layer and the 3rd mask layer.
2. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, it is characterized in that, the method of the first stress oxidation layer on described removal first grid structural top surface is: after removing the first stress nitride layer, on described the first stress oxidation layer surface, form photoresist layer; Return photoresist layer described in etching, until expose the first stress oxidation layer on first grid structure and second grid structural top surface; After returning etching, take described photoresist layer as mask, remove the first stress oxidation layer on described first grid structure and second grid structural top surface; After removing the first stress oxidation layer on described first grid structure and second grid structural top surface, remove photoresist layer.
3. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 2, it is characterized in that, take described photoresist layer as mask, and the technique of the first stress oxidation layer on described removal first grid structure and second grid structural top surface is dry etch process or wet-etching technology.
4. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 2, is characterized in that, the technique of described removal photoresist layer is for adopting one or both in cineration technics and etching technics to be used in combination.
5. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 2, is characterized in that, before forming photoresist layer, on described the first stress oxidation layer surface, forms anti-reflecting layer.
6. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, it is characterized in that, described thermal annealing for the first time comprises rapid thermal annealing, hot furnace annealing or laser pulse annealing, and the temperature of described thermal annealing is for the first time 600 degrees Celsius-1200 degrees Celsius.
7. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, the material of described the first stress oxidation layer is silica or silicon oxynitride, and the material of described the first stress nitride layer is silicon nitride.
8. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, it is characterized in that, also comprise: before thermal annealing for the first time, remove the Semiconductor substrate of second area and the first stress oxidation layer of second grid body structure surface and the first stress nitride layer.
9. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, it is characterized in that, also comprise: after removing the first mask layer, the second mask layer and the 3rd mask layer, semiconductor substrate surface in described first grid structure both sides forms the 3rd side wall, and the semiconductor substrate surface in described second grid structure both sides forms the 4th side wall; In the Semiconductor substrate of described the 3rd side wall both sides, form the first source/drain region; In the Semiconductor substrate of described the 4th side wall both sides, form the second source/drain region; After forming the first source/drain region and the second source/drain region, the second stress nitride layer that forms the second stress oxidation layer and be positioned at described the second stress oxidation layer surface at described Semiconductor substrate, first grid structure and second grid body structure surface; After forming the second stress oxidation layer and the second stress nitride layer, carry out thermal annealing for the second time; After thermal annealing for the second time, remove the second stress oxidation layer and the second stress nitride layer.
10. the formation method of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 9, is characterized in that, described the first source/drain region is N-shaped, and described the second source/drain region is p-type.
The 11. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 9, is characterized in that, the material of described the second stress oxidation layer is silica or silicon oxynitride, and the material of described the second stress nitride layer is silicon nitride.
The 12. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 9, it is characterized in that, the temperature of described thermal annealing is for the second time 600 degrees Celsius-1200 degrees Celsius, and described thermal annealing for the second time comprises rapid thermal annealing, hot furnace annealing or laser pulse annealing.
The 13. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, it is characterized in that, the method of described formation stressor layers is: described the 3rd mask layer of take is mask, adopts etching technics to form opening in the Semiconductor substrate of described second grid structure both sides; In described opening, adopt selective epitaxial depositing operation to form stressor layers, the material of described stressor layers is SiGe.
The 14. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 13, is characterized in that, sidewall and the semiconductor substrate surface of described opening is " Σ " shape.
The 15. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 14, it is characterized in that, the formation technique of described opening is: described the 3rd mask layer of take is mask, adopts anisotropic dry etch process to form the sidewall opening vertical with Semiconductor substrate; After dry etching, adopt the sidewall of opening described in anisotropic wet-etching technology etching, described opening sidewalls is extended in Semiconductor substrate.
The 16. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, before forming first grid structure, described Semiconductor substrate are carried out to the doping of p-type well region; Before forming second grid structure, described Semiconductor substrate is carried out to the doping of N-shaped well region.
The 17. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, before forming the first stress oxidation layer and the first stress nitride layer, in the Semiconductor substrate of described first grid structure both sides, carry out N-shaped light dope; Before forming the 3rd mask layer, in the Semiconductor substrate of described second grid structure both sides, carry out p-type light dope.
The 18. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, it is characterized in that, described first grid structure comprises: first grid dielectric layer, be positioned at the first grid electrode layer on first grid dielectric layer surface, the first side wall that is positioned at described first grid electrode layer and is positioned at the semiconductor substrate surface of described first grid electrode layer both sides; Described second gate dielectric layer comprises: second gate dielectric layer, be positioned at the second gate electrode layer on second gate dielectric layer surface, the second side wall that is positioned at described second gate electrode layer and is positioned at the semiconductor substrate surface of described second gate electrode layer both sides.
The 19. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that, the material of described the first mask layer, the second mask layer and the 3rd mask layer is silicon nitride.
The 20. formation methods of CMOS (Complementary Metal Oxide Semiconductor) pipe as claimed in claim 1, is characterized in that having fleet plough groove isolation structure between described first area and second area.
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