CN104183491B - The forming method of transistor - Google Patents
The forming method of transistor Download PDFInfo
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- CN104183491B CN104183491B CN201310190595.7A CN201310190595A CN104183491B CN 104183491 B CN104183491 B CN 104183491B CN 201310190595 A CN201310190595 A CN 201310190595A CN 104183491 B CN104183491 B CN 104183491B
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of forming method of transistor, including：Substrate is provided, the substrate surface has gate structure；Opening is formed in the substrate of the gate structure both sides；Stressor layers are formed in the opening, the surface of the stressor layers is equal to or higher than substrate surface；Barrier layer is formed in the stress layer surface；After barrier layer is formed, source region and drain region are formed in the substrate of gate structure both sides and stressor layers；After source region and drain region is formed, wet chemical cleaning is carried out to the substrate, gate structure and stressor layers.Stressor layers pattern in the transistor formed is good, and transistor performance is stablized.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of forming method of transistor.
Background technology
Transistor is just being widely used at present as most basic semiconductor devices, with the component density of semiconductor devices
With the raising of integrated level, the grid size of transistor becomes shorter than ever；However, the grid size of transistor, which shortens, can make crystalline substance
Body pipe produces short-channel effect, and then produces leakage current, the final electric property for influencing semiconductor devices.At present, the prior art
Mainly by improving the stress of transistor channel region, to improve carrier mobility, and then the driving current of transistor is improved, subtracted
Leakage current in few transistor.
The method that the prior art improves the stress of transistor channel region is to form stressor layers in the source/drain region of transistor, its
In, the material of the stressor layers of PMOS transistor is SiGe（SiGe）, between silicon and SiGe because lattice mismatch formed compression, from
And improve the performance of PMOS transistor；The material of the stressor layers of nmos pass transistor is carborundum（SiC）, between silicon and carborundum because
The tension that lattice mismatch is formed, so as to improve the performance of nmos pass transistor.
The prior art has the cross-sectional view of the transistor forming process of stressor layers as shown in Figure 1 to Figure 3, bag
Include：
Please refer to Fig.1, there is provided Semiconductor substrate 10,10 surface of Semiconductor substrate have gate structure 11, partly leading
10 surface of body substrate forms mask layer 14, and the mask layer 14 exposes gate structure 11 and needs to form the substrate of stressor layers 10
Surface.
Please refer to Fig.2, be mask with mask layer 14, formed and opened in the Semiconductor substrate 10 of 11 both sides of gate structure
Mouth 12, the side wall of the opening 12 form " Σ " with the surface of Semiconductor substrate 10（Sigma, Sigma）Shape, and " Σ "
The apex angle of shape extends to gate structure 11.
Please refer to Fig.3, form stressor layers 13 in the opening 12, the material of the stressor layers 13 is SiGe or carbonization
Silicon.After stressor layers 13 are formed, silicon layer 15 is formed on 13 surface of stressor layers, after source region and drain region is subsequently formed,
15 surface of silicon layer forms metal silicide contact layer by self-aligned silicide process.
After stressor layers 13 and silicon layer 15 is formed, using stress of the ion implantation technology in 11 both sides of gate structure
Source region or drain region are formed in layer 13 and silicon layer 15（It is not shown）；After source region and drain region is formed, the mask layer 14 is removed.
However, with the transistor of prior art formation, the pattern of stressor layers is bad, is subsequently formed and is electrically connected with stressor layers
Conductive interconnection line after, the loose contact in the conductive interconnection line and source region or drain region, the transistor performance formed is unstable
It is fixed.
The content of the invention
It is of the invention to solve the problems, such as to be to provide a kind of forming method of transistor, make formed stressor layers pattern good,
Ensure that transistor performance is stablized.
To solve the above problems, the present invention provides a kind of forming method of transistor, including：Substrate, the substrate are provided
Surface has gate structure；Opening is formed in the substrate of the gate structure both sides；Stressor layers, institute are formed in the opening
The surface for stating stressor layers is equal to or higher than substrate surface；Barrier layer is formed in the stress layer surface；After barrier layer is formed,
Source region and drain region are formed in the substrate of gate structure both sides and stressor layers；After source region and drain region is formed, to the substrate,
Gate structure and stressor layers carry out wet chemical cleaning.
Optionally, the material on the barrier layer is silica or silicon nitride.
Optionally, the formation process on the barrier layer is thermal oxidation technology or tropical resources technique.
Optionally, the formation process on the barrier layer is atom layer deposition process.
Optionally, the gate structure includes：Positioned at the gate dielectric layer of substrate surface；Grid electricity positioned at gate dielectric layer surface
Pole layer；Positioned at the pseudo- side wall of the substrate surface of gate dielectric layer and gate electrode layer both sides.
Optionally, further include：After stressor layers are formed, formed before barrier layer, remove the pseudo- side wall.
Optionally, after stressor layers are formed, before removing the pseudo- side wall, silicon layer is formed in the stress layer surface；
The barrier layer being subsequently formed covers the side wall of the stressor layers and the side wall and top surface of silicon layer.
Optionally, after barrier layer is formed, the second side wall is formed in the gate structure both sides for removing pseudo- side wall.
Optionally, further include：After barrier layer is formed, formed before the second side wall, carved using anisotropic dry method
Etching technique removes the barrier layer of substrate surface.
Optionally, further include：Second mask layer on gate electrode layer surface is formed at, second mask layer is as etching shape
Mask during into gate dielectric layer and gate electrode layer, the material identical of the material of second mask layer and pseudo- side wall, and removing
While pseudo- side wall, second mask layer is removed.
Optionally, the gate structure further includes：First side of the substrate surface between pseudo- side wall and gate electrode layer
Wall, the material of first side wall are the combination of silica, silicon nitride or silicon oxynitride, and first side wall and pseudo- side wall
The surfacing being in contact is not silicon nitride, after removing pseudo- side wall, exposes first side wall.
Optionally, further include：Before pseudo- side wall is formed, using ion implantation technology in the substrate of gate electrode layer both sides
Form lightly doped district.
Optionally, the material of the stressor layers is SiGe, and the formation process of the stressor layers deposits work for selective epitaxial
Skill.
Optionally, the formation process of the opening is：The first mask layer, first mask are formed in the substrate surface
Layer exposes the gate structure and the substrate surface for needing to be formed stressor layers of the gate structure both sides；With described
One mask layer and the gate structure are substrate described in mask etching, and opening is formed in the substrate of the gate structure both sides.
Optionally, the side wall of the opening and substrate surface are in " Σ " type, and the apex angle of the opening sidewalls is to grid knot
Extension, the technique of the first mask layer etched substrate include below structure：Institute is etched using anisotropic dry etch process
Substrate is stated, opening is formed in the substrate of gate structure both sides, the side wall of the opening is vertical with substrate surface；Using each to different
Property wet-etching technology etch side wall and the bottom of the opening, make the side wall of the opening and substrate surface be in " Σ " type,
And the apex angle of the opening sidewalls extends to gate structure lower section.
Optionally, the material of the substrate is monocrystalline silicon, and the crystal orientation of the substrate surface is<100>Or<110>.
Optionally, the source region and the formation process in drain region are：After stressor layers are formed, in substrate and gate structure table
Face forms photoresist layer, and the photoresist layer, which exposes, to be needed to form the position in source region and drain region；With the photoresist layer mask,
Source region and drain region are formed in the stressor layers of gate structure both sides or substrate using ion implantation technology；Forming source region and drain region
Afterwards, the photoresist layer is removed.
Compared with prior art, technical scheme has the following advantages：
Formed in the substrate of gate structure both sides after stressor layers, in the substrate, gate structure and stress layer surface
Form barrier layer.The barrier layer can cover the surface that the stressor layers are exposed；After source region and drain region is subsequently formed
Wet chemical cleaning process in, the barrier layer can protect the surfaces of the stressor layers from damage, so as to ensure that institute
It is good to state the stressor layers pattern to be formed, then ensure that source region and the stabilization of drain region electric conductivity, make formed transistor
Can be good.
Further, after the pseudo- side wall in forming stressor layers and removing gate structure, formed before the second side wall, adopted
The barrier layer of substrate surface is removed with anisotropic dry etch process, and the barrier layer of substrate surface is removed after being conducive to
Continue the substrate surface in gate structure both sides and form accurate in size second side wall.When the stress layer surface is also formed with silicon layer
When, since damage of the wet chemical cleaning to silicon layer is smaller, it is described it is anisotropic be etched back to technique after, the resistance
Barrier can cover the stressor layers side wall higher than substrate surface, the surface damage wound that stressor layers can be avoided to expose, and stress
The silicon layer of layer top surface can protect the top surface of stressor layers, can still ensure that formed stressor layers pattern is good.
Brief description of the drawings
Fig. 1 to Fig. 3 is the cross-sectional view for the transistor forming process that the prior art has stressor layers；
Fig. 4 be the prior art in wet chemical cleaning process, the cross-section structure that the stressor layers in transistor weather shows
It is intended to；
Fig. 5 to Figure 10 is the cross-sectional view of the transistor forming process of the embodiment of the present invention.
Embodiment
As stated in the Background Art, the stressor layers pattern formed using the prior art is bad, and transistor performance is unstable.
During semiconductor fabrication process, often need to clean using wet chemical（Wet Chemical）Technique is by technique
During be attached to the impurity of substrate or device surface and remove.Study and find by the present inventor, as shown in Figure 3 should
The material of power layer 13, especially silicon germanium material are easily corroded during the wet chemical cleans, and work as SiGe material
The content of germanium is higher in material, and situation about being corroded is more serious.Please continue to refer to Fig. 3, formed in 11 both sides of gate structure source region and
After drain region 13 surface of substrate 10, gate structure 11 or stressor layers is attached to, it is necessary to carry out wet chemical cleaning and remove
Impurity.However, during the wet chemical cleans, the stressor layers 13 using SiGe as material easily suffer erosion, and are formed
Structure as shown in Figure 4.Please refer to Fig.4, influenced be subject to existing technique accuracy, formed using selective epitaxial depositing operation
13 surface of stressor layers be difficult to be completely secured and flushed with 10 surface of substrate, therefore often make formed stressor layers in existing process
13 surface is higher than 10 surface of substrate, to ensure the source region of transistor, drain region and the performance of channel region.However, even in stress
13 surface of layer form silicon layer 15, and the stressor layers 13 still have the surface that a part is exposed, in the mistake of wet chemical cleaning
Cheng Zhong, the part that the stressor layers 13 are exposed are corroded by wet-cleaning solution, are formed depression, are caused formed stressor layers
13 surface topographies are bad, the electric conductivity being easy to cause between the conductive interconnection line being subsequently formed and source region or drain region is unstable,
Poor electric contact, impacts the transistor performance formed.
Further study by the present inventor, formed in the substrate of gate structure both sides after stressor layers,
The substrate, gate structure and stress layer surface form barrier layer.The barrier layer can cover what the stressor layers were exposed
Surface；In the wet chemical cleaning process being subsequently formed after source region and drain region, the barrier layer can protect the stress
The surface of layer is from damage, so as to ensure that the stressor layers pattern of the formation is good, then ensure that source region and drain region are conductive
The stabilization of performance, makes formed transistor performance good.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Fig. 5 to Figure 10 is the cross-sectional view of the transistor forming process of the embodiment of the present invention.
It refer to Fig. 5, there is provided substrate 200,200 surface of substrate have gate structure 201.
The substrate 200 provides workbench for subsequent technique, and the substrate 200 is monocrystalline substrate or silicon-on-insulator
（SOI）Substrate.In the present embodiment, the substrate 200 has first area I, and the first area I should with SiGe for being formed
The transistor of power layer, the first area I pass through fleet plough groove isolation structure（It is unmarked）With other regions of substrate 200 mutually every
From.The crystal orientation on 200 surface of substrate is<100>Or<110>, so that the opening sidewalls subsequently formed in substrate can be with lining
200 surface of bottom is in " Σ " shape, is in the crystal orientation of the present embodiment<100>.
The gate structure 201 is formed at 200 surface of substrate of first area I；In the present embodiment, the substrate 200
Other region surfaces be also formed with some being used to form the gate structures of transistor（It is unmarked）.The gate structure 201 wraps
Include：Gate dielectric layer 210 positioned at 200 surface of substrate；Gate electrode layer 211 positioned at 210 surface of gate dielectric layer；Positioned at gate electrode layer
Second mask 212 on 211 surfaces；The first side wall positioned at 200 surface of substrate of 211 both sides of gate dielectric layer 210 and gate electrode layer
213；Pseudo- side wall 214 positioned at 200 surface of substrate of 211 and first side wall of gate electrode layer, 213 both sides.
The formation process of the gate structure 201 is：Gate dielectric membrane is deposited with this on 200 surface of substrate, is situated between positioned at grid
The gate electrode film of matter film surface；The second mask layer 212, second mask are formed in gate electrode film surface deposition-etch
Layer 212 defines the location and shape of gate electrode layer 211 and gate dielectric layer 210, and the material of second mask layer 212 is oxidation
The combination of silicon, silicon nitride or silica and silicon nitride, in the present embodiment, the material of second mask layer 212 is nitridation
Silicon, can also have silicon oxide layer between second mask layer 212 and gate electrode layer；It is to cover with second mask layer 212
Film etches gate electrode film and gate dielectric membrane, forms gate dielectric layer 210 and gate electrode layer 211；Using depositing operation and return quarter
Etching technique forms the first side wall 213 and pseudo- side wall 214 on 200 surface of substrate of 211 both sides of gate dielectric layer 210 and gate electrode layer,
In the present embodiment, the material of first side wall 213 is the combination of silica, silicon nitride or silica and silicon nitride, described
The material of pseudo- side wall 214 is silicon nitride, and the surfacing that first side wall 213 and pseudo- side wall are in contact is not silicon nitride.
It should be noted that can also be before pseudo- side wall 214 be formed, using lining of the ion implantation technology in 211 both sides of gate electrode layer
Lightly doped district is formed in bottom 200.
In one embodiment, the material of the gate dielectric layer 210 is silica, and the material of the gate electrode layer 211 is more
Crystal silicon.In another embodiment, the material of the gate dielectric layer 210 is high K dielectric material, the material of 211 gate electrode layer
For metal, the gate structure 201 is used to form high-K metal gate（HKMG, High-k Metal Gate）Transistor.When described
The material of gate dielectric layer 210 is high K dielectric material, when the material of the gate electrode layer 211 is metal, the gate structure 201
Using rear grid technique（Gate Last Process）Formed, therefore in current procedures, the gate dielectric layer 210 and gate electrode
The locus of layer 211 is occupied by dummy gate layer, and the material of the dummy gate layer is polysilicon, the dummy gate layer and substrate
There can also be silicon oxide layer to be isolated between 200.Subsequently after source region and drain region is formed, remove dummy gate layer and formed
Gate dielectric layer 210 and gate electrode layer 211.
Fig. 6 is refer to, opening 202 is formed in the substrate 200 of 201 both sides of gate structure.
It is described opening 202 formation process be：The first mask layer 203 is formed on 200 surface of substrate, described first covers
Film layer 203 exposes the substrate 200 for needing to be formed stressor layers of 201 both sides of the gate structure 201 and the gate structure
Surface；With first mask layer 203 and the gate structure 201 for substrate 200 described in mask etching, in the gate structure
Opening 202 is formed in the substrate 200 of 201 both sides, the material of first mask layer 203 is silicon nitride.
In the present embodiment, side wall and the substrate surface of the opening 202 be in " Σ " type, and the top of 202 side walls that are open
The extension of the angular lower section of gate structure 201, is included with the technique of 203 etched substrate 200 of the first mask layer：Using anisotropy
Dry etch process etch the substrate 200, opening is formed in the substrate 200 of 201 both sides of gate structure, the opening
Side wall is vertical with 200 surface of substrate；Side wall and the bottom of the opening are etched using anisotropic wet-etching technology, makes institute
It is in " Σ " type to state the side wall of opening 202 and substrate surface, and the apex angle of 202 side walls of the opening prolongs to the lower section of gate structure 201
Stretch.
The anisotropic dry etch process is：Etching gas include chlorine, hydrogen bromide or chlorine and hydrogen bromide
Mixed gas, the flow of hydrogen bromide for 200 standard milliliters it is per minute~800 standard milliliters are per minute, the flow of chlorine is 20 marks
Quasi- milliliter is per minute~100 standard milliliters are per minute, the flow of inert gas for 50 standard milliliters it is per minute~1000 standard millis
Liter Per Minute, the pressure of etching cavity are the millitorr of 2 millitorrs~200, and etch period is 15 seconds~60 seconds.
The anisotropic wet-etching technology is：Etching liquid includes alkaline solution, and the alkaline solution is hydroxide
Potassium（KOH）, sodium hydroxide（NaOH）, lithium hydroxide（LiOH）, ammonium hydroxide（NH4OH）Or tetramethylammonium hydroxide（TMAH）In one
Kind or multiple combinations.
In the present embodiment, the surface orientation of the substrate 200 is<100>, anisotropic wet-etch rate is vertical
It is straight and parallel to very fast on the direction on 200 surface of substrate, and in crystal orientation<111>Direction on, etch rate is most slow, can make
The side wall of first opening 202 and 200 surface of substrate are in " Σ " shape.
In another embodiment, in order to reduce processing step, additionally it is possible to only with this anisotropic dry etching work
Skill forms opening, and stressor layers are formed in the opening, then the side wall of the opening is formed " U " perpendicular to 200 surface of substrate
Shape opening.
Fig. 7 is refer to, in the opening 202（As shown in Figure 6）Interior formation stressor layers 204, the surface of the stressor layers 204
Equal to or higher than 200 surface of substrate.
The material of the stressor layers 204 is SiGe or carborundum；When first area I is used to form PMOS transistor, institute
The material for stating stressor layers 204 is SiGe, and compression can be obtained in the channel region of the lower section of gate structure 201；When first area I is used
When nmos pass transistor is formed, the material of the stressor layers 204 is carborundum, can in the channel region of the lower section of gate structure 201
Obtain tension.In the present embodiment, the material of the stressor layers 204 is SiGe, and first area I forms PMOS transistor.
The formation process of the stressor layers 204 is selective epitaxial depositing operation, the selective epitaxial depositing operation
Temperature is 500 degrees Celsius~800 degrees Celsius, and air pressure is the support of 1 support~100, and deposition gases include silicon source gas（SiH4Or
SiH2Cl2）And ge source gas（GeH4）Or carbon-source gas（CH4、CH3Cl or CH2Cl2）, the silicon source gas, ge source gas
Or the flow of carbon-source gas is 1 standard milliliters/minute~1000 standard milliliters/minute；In the present embodiment, reacting gas SiH4
And GeH4；The gas of the selective epitaxial depositing operation further includes HCl and H2, the flow of the HCl is 1 standard milliliters/minute
~1000 standard milliliters/minute, H2Flow be the standard liter/min of 0.1 standard liter/min~50.
In the present embodiment, after stressor layers 204 are formed, using selective epitaxial depositing operation in the stressor layers 204
Surface forms silicon layer 205；205 surface of silicon layer forms metal silicide by self-aligned silicide process in subsequent technique and connects
Contact layer, for being electrically connected the conductive plunger being subsequently formed in source region or drain region surface.
In semiconductor technology manufacturing process, often need carry out wet chemical cleaning, with remove be attached to substrate or
The impurity on semiconductor device structure surface, the cleaning solution of the wet chemical cleaning include hydrofluoric acid, SC-1 solution or SPM
Solution etc., these cleaning solutions can achieve the purpose that removing for different types of impurity；However, the wet chemical scavenger
Skill easily causes to corrode to stressor layers 204, when especially cleaning solution includes hydrofluoric acid, easily to SiGe be material stressor layers
204 cause to damage；Moreover, inventor has found that when the Ge content in silicon germanium material is higher, the erosion being subject to is tighter
Weight.In the present embodiment, if during follow-up wet chemical cleaning, 204 surface of stressor layers has the part of exposure, meeting
Cause the pattern of stressor layers 204 bad, influence to be subsequently formed the electrical connection properties of the conductive plunger in source region or drain region surface.
However, since the formation process of the stressor layers 204 is selective epitaxial depositing operation, it is subject to outside existing selectivity
Prolong the limitation of depositing operation accuracy, the stressor layers 204 are difficult to ensure that and are flushed completely with 200 surface of substrate, therefore existing work
Skill often makes the surface of the stressor layers 204 be higher than 200 surface of substrate, to ensure the electrical of source region, drain region or channel region
Energy.In the present embodiment, the surface of the stressor layers 204 is higher than 200 surface of substrate.However, even in 204 surface of stressor layers
Re-form silicon layer 205, the stressor layers 204 are still exposed higher than the partial sidewall on 200 surface of substrate, when being subsequently formed source
When wet chemical cleaning is carried out after area and drain region, easily corrode the exposed surface of the stressor layers 204 and form depression,
So as to influence the performance of stressor layers 204.
Therefore, the present embodiment subsequently forms barrier layer, the stop on substrate 200, stressor layers 204 and 205 surface of silicon layer
Layer can protect the stressor layers 204 injury-free during wet chemical cleaning, so as to ensure that what is formed answers
204 pattern of power layer is good.
Fig. 8 is refer to, after stressor layers 204 and silicon layer 205 is formed, removes the pseudo- side wall 214（As shown in Figure 7）、
First mask layer 203（As shown in Figure 7）With the second mask 212（As shown in Figure 7）.
Since the pseudo- side wall 214 is used to define to form opening 202（As shown in Figure 6）With the position of stressor layers 204, and
And in the etching technics for forming opening 202, the puppet side wall 214, which is inevitably damaged, to be thinned, it is therefore desirable to is gone
Except the pseudo- side wall 214 and accurate in size second side wall is formed in 211 and first side wall of gate electrode layer, 213 both sides, with definition
The source region being subsequently formed and the position in drain region.
In the present embodiment, the material of the pseudo- side wall 214 is silicon nitride, and the technique for removing the pseudo- side wall 214 is wet
Method etching technics, etching liquid include phosphoric acid.By in this present embodiment, the material of 203 and second mask layer 212 of the first mask
Also it is silicon nitride, therefore second mask 212 can remove at the same time with the pseudo- side wall 214, make the second side being subsequently formed
Wall size is accurate.
Fig. 9 is refer to, is removing the pseudo- side wall 214（As shown in Figure 7）Afterwards, in 200 surface of substrate, grid knot
The side wall and top surface on 201 surface of structure, the sidewall surfaces of stressor layers 204 and silicon layer 205 form barrier layer 206.
The material on the barrier layer 206 is silica or silicon nitride；When the material on the barrier layer 206 is silica,
The formation process on the barrier layer 206 is thermal oxidation technology；When the material on the barrier layer 206 is silicon nitride, the barrier layer
206 formation process is tropical resources technique.The barrier layer 206 can be subsequently formed source region and drain region, and remove photoresist
In wet chemical cleaning after layer, protect the stressor layers 206 that SiGe is material from corroding, make the shape of stressor layers 206
Looks are good.
The thermal oxidation technology or tropical resources technique can be formed only on substrate 200, stressor layers 204 and 205 surface of silicon layer
Barrier layer 206,211 surface of gate electrode layer have silicon oxide layer（It is not shown）Without forming barrier layer 206.Moreover, institute
State that 206 thickness of barrier layer that thermal oxidation technology or tropical resources technique are formed is controllable and covering power is good, the stress can be covered
Layer 204 is higher than the side wall of 200 part of substrate, and can make the thinner thickness on the barrier layer 206, does not influence subsequently in grid electricity
The dimensional accuracy for the second side wall that pole layer 211 and 213 both sides of the first side wall are formed.Further, since the chemical property of silicon compares germanium
Vivaciously, can be first with gas reaction and forming silicon nitride or silica in tropical resources technique or thermal oxidation technology.
In the present embodiment, silicon nitride barrier 206, the gas bag of the tropical resources technique are formed using tropical resources technique
Include ammonia（NH4）, temperature is more than 600 degrees Celsius, and the time is 1 minute~30 minutes, the thickness of the silicon nitride barrier 206 formed
Spend for 1 nanometer~5 nanometers.The speed of growth of the tropical resources technique is slower, the thickness on barrier layer 206 more accurately may be used
Control；Moreover, the gas of tropical resources technique is easily entered in the groove between gate structure 201 and stressor layers 204, make the resistance to be formed
206 better quality of barrier, covering power are more preferably；In addition, silicon nitride is not easy to be removed by hydrofluoric acid, stressor layers 204 can be protected.
In another embodiment, silica barrier layer 206, the gas of the thermal oxidation technology are formed using thermal oxidation technology
For oxygen, temperature is 700 degrees Celsius~1000 degrees Celsius, and the time is 1 minute~30 minutes, the silica barrier layer formed
206 thickness is 1 nanometer~5 nanometers.The speed that the thermal oxidation technology forms barrier layer 206 is fast, when advantageously reducing technique
Between；However, the silica is easily removed by hydrofluoric acid, therefore, the thickness of the silica barrier layer 206 needs to guarantee
Stressor layers 204 are protected in cleaning process, without being completely removed in cleaning process.
In other embodiments, the formation process on the barrier layer 206 is atom layer deposition process, the atomic layer deposition
The temperature of technique is 350 degrees Celsius~550 degrees Celsius, and air pressure is the support of 0.1 support~0.5, and the thickness on the barrier layer 206 formed is
1 nanometer~5 nanometers.The barrier layer 206 formed covers substrate 200,201 surface of stressor layers 204, silicon layer 205 and gate structure；
206 thickness of barrier layer that the atom layer deposition process is formed is thin and covering power is good, and substrate 200 and gate structure 201
The barrier layer of top surface can be removed subsequently through anisotropic dry etch process.
0 is please referred to Fig.1, using the barrier layer 206 on 200 surface of anisotropic dry etch process removal substrate, and
After the barrier layer 206 for removing 200 surface of substrate, the second side wall 215 is formed on 200 surface of substrate of 201 both sides of gate structure.
When forming barrier layer 206 using tropical resources or tropical resources technique, between the gate structure 201 and stressor layers
200 surface of substrate also there is barrier layer 206 to cover, if directly forming the second side wall 215 on 206 surface of barrier layer, can lead
Cause formed 215 size of the second side wall inaccurate.
In another embodiment, the use atom layer deposition process forms barrier layer 206, then substrate 200 and grid knot
201 surface of structure is all covered with barrier layer 206, also needs to remove using anisotropic dry etch process, to ensure the second side
The accurate size of wall 215.
In the present embodiment, the barrier layer 206 on 200 surface of substrate is removed before the second side wall 215 is formed, it is described to remove lining
The method on the barrier layer 206 on 200 surface of bottom is anisotropic dry etch process, the quarter of the anisotropic dry etching
Erosion gas includes CF4、H2And O2, air pressure is the millitorr of 0.1 millitorr~100, and etch period is 15 seconds~60 seconds.The anisotropy
Dry etch process can retain the barrier layers 206 of 205 sidewall surfaces of the stressor layers 204 and silicon layer so that follow-up
206 surface of stressor layers is protected in cleaning process, while removes the barrier layer 206 on 200 surface of substrate, to form accurate size
The second side wall 215.
The material of second side wall 215 is the combination of silica, silicon nitride or silica and silicon nitride, second side
The formation process of wall 215 is depositing operation and is etched back to technique, second side wall 215 be used to defining the source region that is subsequently formed and
Drain region（It is not shown）Position.
The source region and the formation process in drain region are：After 206 and second side wall 215 of barrier layer is formed, in substrate 200
Photoresist layer is formed with 201 surface of gate structure（It is not shown）, the photoresist layer defines the position in source region and drain region, with institute
It is mask to state photoresist layer, is formed using ion implantation technology in the stressor layers 204 or substrate 200 of 201 both sides of gate structure
Source region and drain region.In the present embodiment, the first area I is used to form PMOS transistor, and the material of the stressor layers 204 is
SiGe, therefore the ion that the source region and drain region are injected is p-type ion.
Please continue to refer to Figure 10, after source region and drain region is formed, remove the photoresist layer, and to the substrate 200,
Gate structure 201 and stressor layers 204 carry out wet chemical cleaning.
, it is necessary to the photoresist layer be removed, to carry out follow-up technique, such as in substrate after source region and drain region is formed
The gate structure both sides in 200 other regions form stressor layers, and the material of the stressor layers can be carborundum, make the grid
Structure can form nmos pass transistor.However, after photoresist layer is removed, the semiconductor device on the substrate 200 and its surface
Part body structure surface easily adheres to the impurity of preamble technique generation, such as oxide and organic matter, therefore is carrying out subsequent technique step
, it is necessary to be cleaned to the semiconductor device structure of substrate 200 and its surface, to remove the impurity before rapid.
In the present embodiment, impurity, the cleaning solution of the wet chemical cleaning are removed using wet chemical cleaning
Including hydrofluoric acid, SC-1 solution or SPM solution etc., different types of impurity such as oxide, metal ion can be removed or had
Machine thing etc..Wherein, hydrofluoric acid easily causes to corrode to silicon germanium material, and in the present embodiment, the stressor layers 204 using SiGe as material
Side wall higher than 200 surface of substrate is blocked layer 206 and covers, can be described in protection during the wet chemical cleaning
Stressor layers 204, so as to ensure that the pattern of the stressor layers 204 is good, stablize formed transistor performance from damage.
The present embodiment is higher than substrate surface using tropical resources technique after silicon Germanium stress layer and silicon layer is formed in stressor layers
Sidewall sections form barrier layer, and the stressor layers top surface has silicon layer；The formation of source region and drain region is completed, and is being gone
After photoresist layer, carry out wet chemical cleaning remove substrate or semiconductor device structure surface it is miscellaneous when, the silicon
Germanium stressor layers are protected higher than the part of substrate surface, thus stressor layers will not washed liquid erosion, ensure that should
The pattern of power layer is good.
In conclusion being formed in the substrate of gate structure both sides after stressor layers, in the substrate, gate structure and answer
Power layer surface forms barrier layer.The barrier layer can cover the surface that the stressor layers are exposed；Be subsequently formed source region and
In wet chemical cleaning process after drain region, the barrier layer can protect the surface of the stressor layers from damage, so that
It ensure that the stressor layers pattern of the formation is good, then ensure that source region and the stabilization of drain region electric conductivity, make what is formed
Transistor performance is good.
Further, after the pseudo- side wall in forming stressor layers and removing gate structure, formed before the second side wall, adopted
The barrier layer of substrate surface is removed with anisotropic dry etch process, and the barrier layer of substrate surface is removed after being conducive to
Continue the substrate surface in gate structure both sides and form accurate in size second side wall.When the stress layer surface is also formed with silicon layer
When, since damage of the wet chemical cleaning to silicon layer is smaller, it is described it is anisotropic be etched back to technique after, the resistance
Barrier can cover the stressor layers side wall higher than substrate surface, the surface damage wound that stressor layers can be avoided to expose, and stress
The silicon layer of layer top surface can protect the top surface of stressor layers, can still ensure that formed stressor layers pattern is good.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art, are not departing from this
In the spirit and scope of invention, it can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the scope of restriction.
Claims (11)
- A kind of 1. forming method of transistor, it is characterised in that including：Substrate is provided, the substrate surface has gate structure, and the gate structure includes：Positioned at the gate medium of substrate surface Layer；Gate electrode layer positioned at gate dielectric layer surface；Positioned at the pseudo- side wall of the substrate surface of gate dielectric layer and gate electrode layer both sides；Opening is formed in the substrate of the gate structure both sides；Stressor layers are formed in the opening, the surface of the stressor layers is equal to or higher than substrate surface；Silicon layer is formed in the stress layer surface；After silicon layer is formed, the pseudo- side wall is removed；After the pseudo- side wall is removed, formed and cover the side wall of the stressor layers and the side wall of silicon layer and top surface Barrier layer；Remove the barrier layer of substrate surface；After the barrier layer of substrate surface is removed, the substrate surface in gate structure both sides forms the second side wall；After the second side wall is formed, photoresist layer is formed in substrate and gate structure surface, the photoresist layer, which exposes, to be needed Form the position in source region and drain region；With the photoresist layer mask, source region is formed in the stressor layers of gate structure both sides or substrate using ion implantation technology And drain region；After source region and drain region is formed, the photoresist layer is removed；After the photoresist layer is removed, wet chemical cleaning is carried out to the substrate, gate structure and stressor layers.
- 2. the forming method of transistor as claimed in claim 1, it is characterised in that the material on the barrier layer is silica or nitrogen SiClx.
- 3. the forming method of transistor as claimed in claim 2, it is characterised in that the formation process on the barrier layer is thermal oxide Technique or tropical resources technique.
- 4. the forming method of transistor as claimed in claim 2, it is characterised in that the formation process on the barrier layer is atomic layer Depositing operation.
- 5. the forming method of transistor as claimed in claim 1, it is characterised in that further include：It is formed at gate electrode layer surface Second mask layer, mask when second mask layer forms gate dielectric layer and gate electrode layer as etching, second mask The material identical of the material of layer and pseudo- side wall, and while pseudo- side wall is removed, remove second mask layer.
- 6. the forming method of transistor as claimed in claim 1, it is characterised in that the gate structure further includes：Positioned at pseudo- side First side wall of the substrate surface between wall and gate electrode layer, the material of first side wall is silica, silicon nitride or nitrogen oxygen The combination of SiClx, and first side wall is not silicon nitride with the surfacing that pseudo- side wall is in contact, after removing pseudo- side wall, Expose first side wall.
- 7. the forming method of transistor as claimed in claim 1, it is characterised in that further include：Before pseudo- side wall is formed, use Ion implantation technology forms lightly doped district in the substrate of gate electrode layer both sides.
- 8. the forming method of transistor as claimed in claim 1, it is characterised in that the material of the stressor layers is SiGe, described The formation process of stressor layers is selective epitaxial depositing operation.
- 9. the forming method of transistor as claimed in claim 1, it is characterised in that the formation process of the opening is：Described Substrate surface forms the first mask layer, and first mask layer exposes the gate structure and the gate structure both sides Need to form the substrate surface of stressor layers；Using first mask layer and the gate structure as substrate described in mask etching, Opening is formed in the substrate of the gate structure both sides.
- 10. the forming method of transistor as described in right wants 9, it is characterised in that the side wall of the opening is in substrate surface " Σ " type, and the apex angle of the opening sidewalls extends to gate structure lower section, the technique bag of the first mask layer etched substrate Include：The substrate is etched using anisotropic dry etch process, opening is formed in the substrate of gate structure both sides, it is described The side wall of opening is vertical with substrate surface；Side wall and the bottom of the opening are etched using anisotropic wet-etching technology, It is in " Σ " type to make the side wall of the opening and substrate surface, and the apex angle of the opening sidewalls extends to gate structure lower section.
- 11. the forming method of transistor as claimed in claim 10, it is characterised in that the material of the substrate is monocrystalline silicon, institute The crystal orientation for stating substrate surface is<100>Or<110>.
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