CN105702724B - Semiconductor devices and forming method thereof - Google Patents
Semiconductor devices and forming method thereof Download PDFInfo
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- CN105702724B CN105702724B CN201410707067.9A CN201410707067A CN105702724B CN 105702724 B CN105702724 B CN 105702724B CN 201410707067 A CN201410707067 A CN 201410707067A CN 105702724 B CN105702724 B CN 105702724B
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Abstract
A kind of semiconductor devices and forming method thereof, forming method includes: to form substrate；Gate structure is formed on the substrate；The protective layer for protecting the gate structure is covered in the substrate and the gate structure；Groove is formed in the substrate of gate structure two sides；The filling semiconductor material into the groove, to form stressor layers；Ion doping is carried out to the semiconductor material, forms source region and drain region；After the protective mulch the step of, before the step of filling semiconductor material forms stressor layers, the forming method of the semiconductor devices further include: dry method cleaning is carried out to the semiconductor devices using fluoro-gas.The present invention can be avoided a large amount of defects generated after epitaxial growth, can effectively improve the yields in device manufacturing processes, reduce device manufacturing cost.
Description
Technical field
The present invention relates to field of semiconductor manufacture, in particular to a kind of semiconductor devices and forming method thereof.
Background technique
In existing process for fabrication of semiconductor device, the mode for being typically employed in the channel region introducing stress of MOS device is improved
Carrier mobility, and then improve the performance of MOS device.
For PMOS device, source region and drain region are formed using embedded germanium silicon technology, in the channel region of device
Compression is generated, and then improves carrier mobility.So-called embedded germanium silicon technology, which refers to, needs to form source in semiconductor substrate
Groove is formed in the region in area and drain region, germanium silicon material is filled in the groove later as stressor layers, utilizes silicon and germanium silicon
Between lattice mismatch to channel region generate compression.In concrete technology, boron is usually adulterated in situ in epitaxial growth Ge-Si
Ion, to form source region and the drain region of transistor.
But the prior art, after the boron doped germanium silicon technology of epitaxial growth, semiconductor device surface is easy to produce residual
It stays, to form defect.This defect is in the contact being easy between block device in subsequent technique, therefore, these defects pair
Device yield, yields have a great impact.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor devices and forming method, to reduce semiconductor device surface
Defect.
To solve the above problems, the present invention provides a kind of forming method of semiconductor devices, comprising:
Form substrate；
Gate structure is formed on the substrate；
The protective layer for protecting the gate structure is covered in the substrate and the gate structure；
Groove is formed in the substrate of gate structure two sides；
The filling semiconductor material into the groove, to form stressor layers；
Ion doping is carried out to the semiconductor material, forms source region and drain region；
It is described partly to lead before the step of filling semiconductor material forms stressor layers after the protective mulch the step of
The forming method of body device further include: dry method cleaning is carried out to the semiconductor devices using fluoro-gas.
Optionally, the step of formation substrate includes: offer substrate；Groove is formed in the substrate；In the ditch
Trench bottom and side wall cover the first laying；The second laying, second laying are covered in first laying surface
The removal rate that material is set as the second laying in the fluoro-gas dry method cleaning is less than the removal of first laying
Rate；The fill insulant in the groove for being formed with the first laying and the second laying, to form isolation structure.
Optionally, the material of first laying is silica, and the material of second laying is silicon nitride.
Optionally, the thickness of second laying existsMore than.
Optionally, the step of the second laying of the formation includes: by the way of chemical vapor deposition, atomic layer deposition
Form second laying.
Optionally, the protective layer includes the oxide skin(coating) and nitride layer sequentially formed.
Optionally, described the step of groove is formed in the substrate of gate structure two sides includes: to be with the gate structure
Mask carries out the first etching to the protective layer of the gate structure two sides, and the substrate can be exposed by being formed in the protective layer
The opening on surface；Second etching is carried out to the substrate that the opening is exposed, forms groove in substrate；The semiconductor devices
Forming method include: formed protective layer, first etching, second etching and filling semiconductor material any two step it
Between execute one or many fluoro-gas dry method cleaning the step of.The fluoro-gas dry method cleans the gas used
NF3And NH3。
Optionally, NF described in the fluoro-gas dry method cleaning3The flow of gas is 35~100sccm, the NH3's
Flow is 10~400sccm, and scavenging period is 1~60s, and radio-frequency power is 5~100W, and the air pressure range for cleaning environment is 0.5
~20Torr；Temperature range is 20~170 DEG C.
Optionally, the fluoro-gas dry method cleaning step includes: the cleaning agent for generating plasma state in the reactor chamber；
Semiconductor devices is cleaned using the cleaning agent；Greater than 100 DEG C at a temperature of to the semiconductor devices through over cleaning
It is heated；It anneals to the semiconductor devices by heating.Semiconductor devices is cleaned using the cleaning agent
Temperature maintains 35 DEG C.
Optionally, after the formation groove, into the groove the step of filling semiconductor material before, described half
The forming method of conductor device further include: prerinse is carried out to the groove；It is carried out after prerinse step described containing fluorine gas
The cleaning of soma method.
Optionally, the technique of the filling semiconductor material into the groove is selective epitaxial growth process.
It is optionally, described that be doped the step of forming source region and drain region to the semiconductor material include: in selectivity
Ion doping in situ is carried out during epitaxial growth technology forms source region and drain region.
Correspondingly, the present invention also provides a kind of semiconductor device structures, and the semiconductor devices is by the forming method
It is formed, comprising:
Substrate is formed with multiple grooves in the substrate；
The first laying on channel bottom and side wall；
The second laying on first laying；
It is filled in the isolation structure in the groove and being formed on the second laying；
Gate structure on substrate, the gate structure surface and side wall cover matcoveredn；
Stressor layers between the isolation structure and gate structure in substrate are used doped with ion in the stressor layers
Make source region and drain region.
Optionally, include the steps that cleaning using fluoro-gas dry method in the forming process of the semiconductor devices, it is described
The removal rate that second backing layer material is set as the second laying in the fluoro-gas dry method cleaning is less than first lining
The removal rate of bed course.
Optionally, the material of first laying is silica, and the material of second laying is silicon nitride.
Optionally, the thickness of second laying existsMore than.
Compared with prior art, technical solution of the present invention has the advantage that
The present invention is after protective mulch, and before carrying out the step of being epitaxially-formed stressor layers, fluoro-gas is added
The step of dry method is cleaned, fluorine-containing cleaning agent has very strong removal effect to polymer and pollutant, it is possible to reduce the nuclei of crystallization
Quantity so as to effectively reduce the defect generated in subsequently epitaxial growing materials process, and then improves device manufacturing processes
In yields, reduce device manufacturing cost.
Optionally, in the forming process of isolation structure, the second liner is covered on the first laying of trenched side-wall
Layer.Fluoro-gas dry method is cleaned to the removal rate of the second laying less than the removal rate to the first laying, therefore is increased
The side wall of isolation structure can be effectively protected in second laying in the process of cleaning, can effectively eliminate or reduce isolation
The loss of side wall, to prevent isolation structure during cleaning process by excessive etching, prevent going out for electric leakage or short circuit phenomenon
It is existing, and then the yields in device manufacturing processes can be effectively improved, reduce device manufacturing cost.
Detailed description of the invention
Fig. 1 to Fig. 2 is a kind of schematic diagram of method for forming semiconductor devices of the prior art；
Fig. 3 to Fig. 8 is the schematic diagram of each step in method for forming semiconductor devices first embodiment provided by the present invention；
Fig. 9 to Figure 13 is the signal of each step in method for forming semiconductor devices second embodiment provided by the present invention
Figure；
Figure 14 is the Electronic Speculum of the semiconductor devices of method for forming semiconductor devices provided by the present invention and prior art formation
Comparison diagram.
Specific embodiment
It can be seen from background technology that, in the prior art, semiconductor devices can be cleaned after extension growth stress layer,
The cleaning step is easy to form many small defects in semiconductor device surface, in conjunction with device forming process analyzing defect shape
At the reason of:
As shown in Figure 1, epitaxial growth boron doping germanium silicon forms isolation structure in substrate 10 as in the technique of stressor layers
After 11, carry out stress layer epitaxially grown before, semiconductor devices successively passes through: deposition protective layer 12 and etched substrate formed it is recessed
Slot 13 and etc., any one step is all easy to produce pollutant and etch residue (pollutant 14), these pollutions
Object is deposited in 12 surface of protective layer, forms defect.
As shown in Fig. 2, pollutant 14 becomes epitaxial grown material during being epitaxially-formed stressor layers 15
The nuclei of crystallization.Due to nucleation, pollutant 14 can be grown during epitaxial growth to become larger.Thus after epitaxial growth,
Numerous small pollutants can all become the biggish defect 24 of volume.In subsequent technique, the defect 24 will affect device
Between connection conducting, influence properties of product.
In the prior art, reducing the method for above-mentioned epitaxial growth defect, there are mainly two types of: one is boron doped
HCl gas is added during germanium siliceous deposits, to increase etching selection ratio, pollutant is carried out while epitaxial growth so clear
It washes.But this method therefore can reduce thruput, Material growth is made to slow since it is desired that increase HCl gas；Separately
A kind of method is wet-cleaning process, and to remove pollutant, but the effect of this method is very limited.
To solve the technical problem, the present invention provides a kind of semiconductor devices and forming method thereof, including walk as follows
It is rapid:
Form substrate；
Gate structure is formed on the substrate；
The protective layer for protecting the gate structure is covered in the substrate and the gate structure；
Groove is formed in the substrate of gate structure two sides；
The filling semiconductor material into the groove, to form stressor layers；
Ion doping is carried out to the semiconductor material, forms source region and drain region；
It is described partly to lead before the step of filling semiconductor material forms stressor layers after the protective mulch the step of
The forming method of body device further include: dry method cleaning is carried out to the semiconductor devices using fluoro-gas.
The step of present invention is by during semiconductor devices is formed, being added the cleaning of fluoro-gas dry method, so that dirty
Dye object removes as far as possible before material epitaxy growth, so that the nuclei of crystallization of pollutant in material epitaxy growth course be made to subtract as far as possible
It is few, it avoids pollutant and grows up into defect in epitaxial process, to reduce device surface after epitaxial growth
Defects count improves device performance, and then improves the yields in device manufacturing processes.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 3 to Fig. 8 is the signal of each step in the forming method first embodiment of semiconductor devices provided by the present invention
Figure.It should be noted that the present embodiment is illustrated by taking cmos device as an example, the present invention should not be limited with this.
With reference to Fig. 3, substrate 1000 is provided, multiple isolation structures 110 are formed in the substrate 1000.
The semiconductor base 1000 is the workbench of subsequent technique.1000 material of semiconductor base is selected from monocrystalline
Silicon, polysilicon or amorphous silicon；The semiconductor base 1000 can also be selected from silicon, germanium, GaAs or silicon Germanium compound；Described half
Conductor substrate 1000 is also selected from epitaxial layer or epitaxial layer silicon-on；The semiconductor base 1000 can also be it
His semiconductor material, the present invention are not limited in any way this.The material of substrate 1000 described in the present embodiment is silicon.
With reference to Fig. 4, gate structure 102 is formed in the substrate 1000.
The gate structure 102 includes that gate dielectric layer (not indicating) and the gate electrode layer on gate dielectric layer (are not marked
It shows).The material of gate dielectric layer is silica or high dielectric constant material, and the gate electrode layer material is polysilicon or metal.
In the present embodiment, the material of the gate dielectric layer of the gate structure 102 is silica, and gate electrode layer material is polysilicon.
With reference to Fig. 5, protective mulch 120, the protective layer in the substrate 1000 and on the gate structure 102
120 include the oxide skin(coating) 121 and nitride layer 122 sequentially formed.
The protective layer 120 in subsequent etching processes for protecting the substrate and grid from damage, specifically, institute
Stating protective layer 120 includes the oxide skin(coating) 121 and nitride layer 122 sequentially formed.121 material of oxide skin(coating) is oxidation
Silicon can be obtained by the oxidation technology carried out to the substrate 1000 and 102 surface of the gate structure.In addition, the nitrogen
Compound layer 122 selects layer as extension in subsequently epitaxial growing germanium silicon material, specifically, 122 material of the nitride layer is
Silicon nitride.In addition, the oxide skin(coating) 121 and the nitride layer 122 form grid curb wall subsequently through etching, protection is played
Grid and the effect that source region (or drain region) and grid is isolated.
It should be noted that the forming process of the protective layer 120 pollutant 131 easy to form, pollutant 131 can be rear
Become the nuclei of crystallization of Material growth during continuous crystal growth, in epitaxial process, pollutant 131, which can be grown, to become larger,
Form the biggish defect of volume.In subsequent technique, it will affect the connection conducting between device, influence properties of product.This reality
Example is applied after forming the oxide skin(coating) 121 and the nitride layer 122, it is clear to carry out fluoro-gas dry method to the device
It washes.
Specifically, the fluoro-gas dry method cleaning step includes:
Firstly, generating the cleaning agent of plasma in reaction chamber；
Second step cleans semiconductor devices in reaction chamber using the cleaning agent, the temperature of the cleaning process
Degree maintains 35 DEG C,；
Third step, greater than 100 DEG C at a temperature of the semiconductor devices through over cleaning is heated；
4th step anneals to the semiconductor by heating.
In the present embodiment, gas that the dry method cleaning process uses is contains NF3And NH3Gas.Inventor
It is found through experiment that the pollutant main component is metal ion, the intracorporal fluorine ion of purgative gas can be reacted with metal ion,
The fluoride for forming easy cleaning, to realize the removal to pollutant.
Specifically, in the cleaning process, NF3The flow of gas is 35~100sccm, the NH3Flow be 10~
400sccm, the NF3And NH3Flow make to form sufficient concentrations of plasma clean agent in reaction chamber and remove the pollution
Object.Scavenging period is 1~60s, and the scavenging period enables cleaning agent to have time enough and pollutant reaction, removes depollution
Object.In cleaning process, radio-frequency power is 5~100W, and the pressure limit for cleaning environment is 0.5~20Torr；Temperature range is 20
~170 DEG C.The plasma system of the low-power has benefited from NF3And NH3Gas can dissociate under Low emissivity energy, and described
Temperature range then ensure that the generation of cleaning agent reaction.
With reference to Fig. 6, the first etching is carried out to the protective layer 120, the base can be exposed by being formed in the protective layer 120
The opening 103 at bottom 1000.
In the present embodiment, the first etching is carried out to the protective layer 120 using conventional dry etching, in the protective layer
The opening 103 for exposing the substrate 1000 is formed in 120.
It should be noted that being easy the presence of etch residue 132 to the first etching technics of protective layer 120.It is optional
, after the first etching technics, fluoro-gas dry method cleaning is also carried out to the semiconductor devices, it is specifically, fluorine-containing herein
The step of fluoro-gas dry method cleaning carried out after gas dry method cleaning process and above-mentioned formation protective layer, is identical, no longer superfluous herein
It states.
With reference to Fig. 7, the substrate 1000 exposed to the opening 103 carries out the second etching, in source region to be formed and drain region
Groove 104 is formed in 1000 region of substrate.
In the present embodiment, uses and form shape in the technique of wet etching in the substrate 1000 as the recessed of Sigma shape
Slot has the protrusion tip for being directed toward channel region in the middle part of the Sigma connected in star 104, subsequent inside and outside Sigma connected in star 104
When prolonging the germanium silicon material of filling boron-doping, germanium silicon material fills full entire groove, at the tip of the groove 104 protrusion, germanium silicon
Material will introduce bigger compression closer to channel region in channel region.
The technique for forming the Sigma connected in star are as follows: progress plasma etching first, the plasma etching parameter
It include: etching gas include HBr, O2、He、Cl2And NF5, the HBr flow is 100~1000sccm, O2Flow be 2~
20sccm；He flow is 100~1000sccm, Cl2Flow is 2~200sccm, NF5Flow is 2~200sccm, etches air pressure
For 10~200mTorr, bias is 0~400V, and the time is 5~60 seconds；Wet etching is carried out after plasma etching, it is described
Wet-etching technology uses TMAH (tetramethylammonium hydroxide) solution, and the temperature of TMAH is 15 DEG C~70 DEG C, and the time is 20~500
Second.Optionally, the wet-etching technology can also use potassium hydroxide solution or ammonia spirit.
Similar, second of etching of Sigma connected in star 104 is formed in substrate 1000, it is also possible in nitride layer
There are etch residues 203 on 122 surface, therefore, optionally, clean to semiconductor devices fluoro-gas dry method, specifically, this
The step of fluoro-gas dry method carried out after place's fluoro-gas dry method cleaning process and above-mentioned formation protective layer is cleaned is identical, herein
It repeats no more.
It should be noted that the dry method cleaning can also while removing pollutant 203 after groove 104 is formed
Enough natural oxidizing layers of removal 104 surface of groove formation, clean surface is provided for subsequently epitaxial growing semiconductor material.Specifically
, it includes: firstly, generating plasma in reaction chamber that the fluoro-gas dry method, which cleans the step of removing removing natural oxidizing layer,
Cleaning agent:
Generate the chemical reaction of cleaning agent are as follows:
NF3+NH3→NH4F+NH4F.HF
Second step cleans semiconductor devices in reaction chamber using the cleaning agent；
The temperature of the cleaning process maintains 35 DEG C, the chemical reaction of cleaning process are as follows:
NH4F+SiO2→(NH4)2SiF6(solid)+H2O
Or NH4F.HF+SiO2→(NH4)2SiF6(solid)+H2O
Third step, greater than 100 DEG C at a temperature of the semiconductor devices through over cleaning is heated；
4th step anneals to the semiconductor by heating.
The chemical reaction of its annealing process are as follows:
(NH4)2SiF6(solid)→SiF4(gas)+NH3(gas)+HF(gas)
It should also be noted that, in the present embodiment, after groove 104 is formed, fluoro-gas dry method cleaning removal etching
It further include that prewashed step is carried out to semiconductor devices, it is therefore an objective to raw for extension in successive recesses 104 before residue 203
It is long that cleaner surface is provided.
With reference to Fig. 8, the filling semiconductor material into the groove 104 is adulterated in the stressor layers with forming stressor layers
Ion is to form source region or drain region 105.
In the present embodiment, the transistor of formation is PMOS, and the semiconductor material is germanium silicon material, for the ditch to PMOS
Road area provides compression.
It specifically, can also the doped p-type ion in germanium silicon material in situ while epitaxial growth germanium silicon material.For example,
The P-type ion is boron ion, and the formation process that selective epitaxial growth can be used forms stressor layers.In Sigma shape stressor layers
Portion has the protrusion tip for being directed toward channel region, and the germanium silicon material at protrusion tip, will be in channel region closer to channel region
Domain introduces bigger compression, can be more advantageous to the mobility for improving channel region carriers.
It should be noted that optional, appointing in protective mulch, the first etching, the second etching and epitaxial growth
One or many fluoro-gas dry method cleaning steps is executed between two steps of anticipating.Specifically it is included in form protective layer
Later, before the first etching, perhaps after the first etching, before the second etching or after the second etching, epitaxial growth
Before, three time points select wherein any one or more addition fluoro-gas dry method cleaning steps.
Fig. 9 to Figure 13 is the signal of each step in the forming method second embodiment of semiconductor devices provided by the present invention
Figure.
The present embodiment repeats no more in place of being basically the same as those in the first embodiment, the difference of the present embodiment and first embodiment
It is, the step of semiconductor forming method forms substrate is different.In conjunction with reference Fig. 9 to Figure 12, shows the present invention and partly lead
Each step schematic diagram of substrate 2000 is formed in body device forming method second embodiment.
Specifically, the step of forming substrate 2000 includes:
With reference to Fig. 9, semiconductor substrate 200 is provided, forms groove 211 in the semiconductor substrate 200.
It optionally, further include forming barrier layer (figure on 200 surface of substrate before forming groove 211 in the substrate 200
In do not indicate), to protect substrate 200 from the damage of etching technics.
With reference to Figure 10, the first laying 212 and the second laying 213 are sequentially formed in the groove 211, described first
Laying 212 covers the bottom and side wall of the groove 211, and second laying 213 is covered in first laying 212
On.
The effect of first laying 212 is to improve the groove 211 and the subsequent insulant being filled in groove 211
Interfacial characteristics between matter.In the present embodiment, the material of the first laying 212 is silica, and first laying 212 can be with
It is formed by the side wall and bottom that aoxidize the groove 211.In addition, the oxidation process can also repair etch semiconductor substrates
The process of 200 formation grooves 211 is damaged caused by 211 side wall of groove and bottom.
The effect of second laying 213 is to reduce 211 side wall of groove in subsequent fluoro-gas dry cleaning process
Loss.Specifically, 213 material of the second laying is set as the second laying 213 in the fluoro-gas dry method cleaning
Removal rate be less than first laying 212 removal rate.
Semiconductor devices provided by the present invention forms the step of process joined the cleaning of fluoro-gas dry method, used
Fluoro-gas dry method cleaning process is a kind of based on NF3And NH3The cleaning process that gas carries out, is a kind of quarter for oxide
Etching technique.Compared with the method for using diluted hydrofluoric acid to be cleaned in the prior art, is formed in process and be added in semiconductor devices
The step of institute's fluoro-gas dry method cleaning, is easy to keep the loss of isolation structure side wall relatively more, and isolation structure is done in fluoro-gas
It is possible in method cleaning process by overetch.
In the present embodiment, the material of second laying 213 is nitride, and compared with oxide, nitride is fluorine-containing
There is smaller etch rate in gas dry cleaning process, be stop-layer by the second laying 213 of nitride of material, it can
So that etch cleaner stops on the second laying 213, the loss of isolation structure side wall can be efficiently reduced, so as to
The side wall of isolation structure is effectively protected in cleaning process.
Specifically, 213 material of the second laying is silicon nitride in the present embodiment, second laying 213 can pass through
The modes such as chemical vapor deposition and atomic layer deposition are formed.In fluoro-gas dry method cleaning process, the quarter of silica and silicon nitride
Erosion selection ratio is in the range of 6:1 to 10:1.In the present embodiment, the first laying of silica 212 and the second laying of silicon nitride
203 etching selection ratio is 7.06:1.
It should be noted that if the thickness of the second laying 213 is too small, it is difficult to be formed in subsequent cleaning process
The protective effect of effect.The thickness of optional second laying existsMore than.The second of silicon nitride material in the present embodiment
Laying 213 with a thickness of
With reference to Figure 11, the fill insulant in the groove 211 for being formed with the first laying 212 and the second laying 213
214。
The effect of insulating materials 214 is the electric isolution realized between different components region.In the present embodiment, the insulation material
Material is silica.
It should be noted that fill insulant 214 is not only influenced by fill process in groove 211, also by
The influence of 211 pattern of groove is easy when being especially filled to the groove of high-aspect-ratio (depth-to-width ratio is greater than 10) in insulation material
Gap is formed in material.Therefore, optionally, after insulating materials filling is completed, an annealing process is carried out, it is possible to reduce in groove
Gap is formed by 211 when fill insulant.
With reference to Figure 12, planarization process is carried out to the insulating materials 214, forms isolation structure 210, removal semiconductor lining
The barrier layer (not identifying in figure) on 200 surface of bottom forms substrate 2000.
Specifically, the method using chemical mechanical grinding carries out planarization process to the insulating materials 214.In chemical machine
In tool process of lapping, terminated with exposing the surface of semiconductor substrate 200.Later, resistance extra in semiconductor substrate 200 is removed
Barrier (does not identify) in figure, to form the substrate 2000 for being subsequently used for being formed gate structure, source region, drain region and stressor layers.
With reference to Figure 13, device grids structure 202 is formed in the substrate 2000, in the substrate 2000 described in formation
Stressor layers, source region and drain region 205, specific steps are consistent with first embodiment, and details are not described herein.
With reference to Figure 14, the Electronic Speculum of the semiconductor devices of semiconductor devices provided by the present invention and prior art formation is shown
Comparison diagram.It is wherein the case of surface defects after the semiconductor epitaxial growth that prior art is formed shown in A1, A2；B1,B2
Shown in be using technical solution of the present invention formed device, the defect situation of the rear surface of epitaxial growth.Black is round in figure
For chip, white area is the region that device is formed.Black splotch is the number of defect after germanium and silicon epitaxial growth in white area
Amount.It include the technical solution institute of fluoro-gas dry method cleaning using the present invention compared with the semiconductor devices that the prior art is formed
In the device of formation, defect situation is significantly improved.Through detecting, semiconductor devices provided by the present invention can reduce
60% defects count.
Correspondingly, please continue to refer to Figure 13, showing semiconductor device of the present invention the present invention also provides a kind of semiconductor devices
The schematic diagram of one embodiment of part.
The semiconductor devices includes:
Substrate 200 is formed with multiple grooves (not indicating in figure) in the substrate；
Positioned at the first laying 212 of the channel bottom and side wall；
The second laying 213 on first laying 212；
The isolation structure 210 that the groove is formed is filled, the isolation structure 210 is located on the second laying；
The gate structure 202 on the substrate 200；
202 surface of gate structure and side wall cover matcoveredn 220.
Be formed between isolation structure the stressor layers between gate structure in substrate 200, in the stressor layers doped with
Ion is used to form source-drain area 205.
The substrate 200 is the workbench of subsequent technique.200 material of substrate is selected from monocrystalline silicon, polysilicon or non-
Crystal silicon；The substrate 200 can also be selected from silicon, germanium, GaAs or silicon Germanium compound；The substrate 200, which is also selected from, to be had
Epitaxial layer or epitaxial layer silicon-on；The substrate 200 can also be other semiconductor materials, and the present invention does not make any limit to this
It is fixed.The material of substrate 200 described in the present embodiment is silicon.
The effect of first laying 212 is the interfacial characteristics improved between the trenched side-wall and isolation structure 210.
In the present embodiment, the material of the first laying 212 is silica.First laying 212 can be by aoxidizing the groove
Side wall and bottom formed.The oxidation process can also repair right during etching the first laying 212 and forming groove
The damage of etching interface caused by the side wall of groove and bottom.
The effect of second laying 213 is the damage for reducing trenched side-wall in subsequent fluoro-gas dry cleaning process
It loses.It should be noted that joined the fluoro-gas dry method cleaning step of fluoro-gas in the forming process of the semiconductor devices
Suddenly, the material of second laying 213 and the first laying 212 is arranged are as follows: in the fluoro-gas dry cleaning process
The removal rate of second laying 213 is less than the removal rate of first laying 212.In Subsequent semiconductor device shape
At in process, fluoro-gas dry method cleaning process used by the fluoro-gas dry method cleaning step of addition is a kind of based on NF3
And NH3Gas, be a kind of etching technics for oxide.It joined the fluoro-gas dry method when device is formed in process
The loss of cleaning step, isolation structure side wall can be more than using the conventional cleaning process of diluted hydrofluoric acid, and isolation structure was cleaning
It is possible to excessively be etched in journey.
The second laying 213 and described is arranged on the first laying 212 that forming material is oxide in the present embodiment
The material of second laying 213 is nitride.Compared with oxide, nitride has smaller etch rate, using material as nitrogen
Second laying 213 of compound be stop-layer, stop at etch cleaner on the second laying 213, can effectively reduce every
The side wall of isolation structure can be effectively protected in loss from structure side wall in the process of cleaning.
In the present embodiment, the material of the second laying 213 is silicon nitride, in fluoro-gas dry method cleaning process, oxidation
The etching selection ratio of silicon and silicon nitride is in the range of 6:1 to 10:1.Specifically, second laying 213 can be and pass through
The silicon nitride that the modes such as chemical vapor deposition and atomic layer deposition are formed.
It should be noted that if the thickness of the second laying 213 is too small, it is difficult to be formed in subsequent cleaning process
The protective effect of effect.The thickness of optional second laying 213 existsMore than.The of silicon nitride material in the present embodiment
Two layings 213 with a thickness of
The material of isolation structure 210 is insulating materials, can be the silicate glass of silica, fluorine silica glass, Fluorin doped
One of with tetraethyl orthosilicate, using oxide in the present embodiment.
The gate structure 202 includes that gate dielectric layer (not indicating) and the gate electrode layer on gate dielectric layer (are not marked
It shows).The material of gate dielectric layer is silica or high dielectric constant material, and the gate electrode layer material is polysilicon or metal.
In the present embodiment, the material of the gate dielectric layer of the gate structure 202 is silica, and gate electrode layer material is polysilicon.
The protective layer 220 in subsequent etching processes for protecting the grid and substrate from damage, specifically, institute
Stating protective layer 220 includes the oxide layer 221 sequentially formed and nitride layer 222.221 material of oxide skin(coating) is silica,
It can be by being obtained to the substrate 2000 and 211 surface oxidation technique of the gate structure.In addition, the nitride layer 222
Layer is selected as extension in subsequently epitaxial growing germanium silicon material, specific 222 material of nitride layer is silicon nitride.This
Outside, the oxide layer 221 and the nitride layer 222 form grid curb wall subsequently through etching, play protection grid and isolation
The effect of source and drain and grid.
In the present embodiment, the semiconductor devices is that transistor is PMOS, is also existed while epitaxial growth germanium silicon material
The formation work of selective epitaxial growth can be used specifically, the P-type ion is boron ion in doped p-type ion in germanium silicon material
Skill forms stressor layers, and adulterates boron ion during extension growth stress layer and form source region and drain region 205.
Specifically, stressor layers are Sigma shape stressor layers in the present embodiment, have in the middle part of the Sigma shape stressor layers and are directed toward
The protrusion tip of channel region, the germanium silicon material at protrusion tip will introduce bigger closer to channel region in channel region
Compression, can be more advantageous to improve channel region carriers mobility.
It should be noted that the semiconductor devices provided by the invention can with but do not limit by shape provided by the present invention
It is formed at method.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (18)
1. a kind of forming method of semiconductor devices characterized by comprising
Substrate is formed, the substrate includes substrate, the isolation structure in the substrate, is located at the isolation structure and described
The first laying between substrate and the second laying between first laying and the isolation structure；
Gate structure is formed on the substrate；
The protective layer for protecting the gate structure is covered in the substrate and the gate structure；
Groove is formed in the substrate of gate structure two sides；
The filling semiconductor material into the groove, to form stressor layers；
Ion doping is carried out to the semiconductor material, forms source region and drain region；
After the protective mulch the step of, before the step of filling semiconductor material forms stressor layers, the semiconductor device
The forming method of part further include: dry method cleaning, and the fluoro-gas are carried out to the semiconductor devices using fluoro-gas
The removal rate of second laying described in dry method cleaning is less than the removal rate of first laying.
2. the forming method of semiconductor devices as described in claim 1, which is characterized in that the step of formation substrate wraps
It includes:
Substrate is provided；
Groove is formed in the substrate；
The first laying is covered in the channel bottom and side wall；
The second laying is covered in first laying surface；
The fill insulant in the groove for being formed with the first laying and the second laying, to form isolation structure.
3. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that the material of first laying is
Silica, the material of second laying are silicon nitride.
4. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that the thickness of second laying existsMore than.
5. the forming method of semiconductor devices as claimed in claim 2, which is characterized in that the step of forming the second laying is wrapped
It includes: forming second laying by the way of chemical vapor deposition, atomic layer deposition.
6. the forming method of semiconductor devices as described in claim 1, which is characterized in that the protective layer includes sequentially forming
Oxide skin(coating) and nitride layer.
7. the forming method of semiconductor devices as described in claim 1, which is characterized in that the base in gate structure two sides
The step of formation groove, includes: in bottom
Using the gate structure as mask, the first etching is carried out to the protective layer of the gate structure two sides, in the protective layer
Middle formation can expose the opening of the substrate surface；
Second etching is carried out to the substrate that the opening is exposed, forms groove in substrate；
The forming method of the semiconductor devices includes: to form protective layer, the first etching, the second etching and filling semiconductor
The step of cleaning of one or many fluoro-gas dry method is executed between any two step of material.
8. the forming method of semiconductor devices as described in claim 1, which is characterized in that the fluoro-gas dry method cleaning is adopted
Gas includes NF3And NH3。
9. the forming method of semiconductor devices as claimed in claim 8, which is characterized in that in the fluoro-gas dry method cleaning
The NF3The flow of gas is 35~100sccm, the NH3Flow be 10~400sccm, scavenging period be 1~60s, penetrate
Frequency power is 5~100W, and the air pressure range for cleaning environment is 0.5~20Torr；Temperature range is 20~170 DEG C.
10. the forming method of semiconductor devices as described in claim 1, which is characterized in that fluoro-gas dry method cleaning step
Include:
The cleaning agent of plasma state is generated in the reactor chamber；
Semiconductor devices is cleaned using the cleaning agent；
Greater than 100 DEG C at a temperature of the semiconductor devices through over cleaning is heated；
It anneals to the semiconductor devices by heating.
11. the forming method of semiconductor devices as claimed in claim 10, which is characterized in that described to utilize the cleaning agent pair
The temperature that semiconductor devices is cleaned maintains 35 DEG C.
12. the forming method of semiconductor devices as described in claim 1, which is characterized in that after the formation groove, to institute
Before the step of stating filling semiconductor material in groove, the forming method of the semiconductor devices further include: to the groove
Carry out prerinse；The fluoro-gas dry method cleaning is carried out after prerinse step.
13. method for forming semiconductor devices as described in claim 1, which is characterized in that filling half into the groove
The technique of conductor material is selective epitaxial growth process.
14. method for forming semiconductor devices as claimed in claim 13, which is characterized in that it is described to the semiconductor material into
The step of row doping forms source region and drain region includes: that ion doping shape in situ is carried out during selective epitaxial growth process
At source region and drain region.
15. a kind of semiconductor devices, the semiconductor devices is by claim 1 to claim 14 any one claim institute
The forming method for the semiconductor devices stated is formed characterized by comprising
Substrate is formed with multiple grooves in the substrate；
The first laying on channel bottom and side wall；
The second laying on first laying；
It is filled in the isolation structure in the groove and being formed on the second laying；
Gate structure on substrate, the gate structure surface and side wall cover matcoveredn；
Stressor layers between the isolation structure and gate structure in substrate are used as source doped with ion in the stressor layers
Area and drain region.
16. semiconductor devices as claimed in claim 15, which is characterized in that include in the forming process of the semiconductor devices
The step of being cleaned using fluoro-gas dry method, second backing layer material are set as second in the fluoro-gas dry method cleaning
The removal rate of laying is less than the removal rate of first laying.
17. semiconductor devices as claimed in claim 15, which is characterized in that the material of first laying is oxidation
Silicon, the material of second laying are silicon nitride.
18. semiconductor devices as claimed in claim 15, which is characterized in that the thickness of second laying existsWith
On.
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| US6007641A (en) * | 1997-03-14 | 1999-12-28 | Vlsi Technology, Inc. | Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch |
| CN101903984A (en) * | 2007-12-21 | 2010-12-01 | 应用材料股份有限公司 | Passivation layer formation by plasma clean process to reduce native oxide growth |
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| KR100644073B1 (en) * | 2004-12-29 | 2006-11-10 | 동부일렉트로닉스 주식회사 | Method for cleaning silicon nitride layer |
| US20130052809A1 (en) * | 2011-08-25 | 2013-02-28 | United Microelectronics Corporation | Pre-clean method for epitaxial deposition and applications thereof |
| US8697508B2 (en) * | 2012-04-19 | 2014-04-15 | United Microelectronics Corp. | Semiconductor process |
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| US6007641A (en) * | 1997-03-14 | 1999-12-28 | Vlsi Technology, Inc. | Integrated-circuit manufacture method with aqueous hydrogen-fluoride and nitric-acid oxide etch |
| CN101903984A (en) * | 2007-12-21 | 2010-12-01 | 应用材料股份有限公司 | Passivation layer formation by plasma clean process to reduce native oxide growth |
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