CN104183491A - Transistor forming method - Google Patents
Transistor forming method Download PDFInfo
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- CN104183491A CN104183491A CN201310190595.7A CN201310190595A CN104183491A CN 104183491 A CN104183491 A CN 104183491A CN 201310190595 A CN201310190595 A CN 201310190595A CN 104183491 A CN104183491 A CN 104183491A
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- 238000000034 method Methods 0.000 title claims abstract description 110
- 239000000758 substrate Substances 0.000 claims abstract description 145
- 238000004140 cleaning Methods 0.000 claims abstract description 32
- 239000000126 substance Substances 0.000 claims abstract description 30
- 230000004888 barrier function Effects 0.000 claims description 74
- 230000015572 biosynthetic process Effects 0.000 claims description 68
- 239000000463 material Substances 0.000 claims description 48
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 39
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 33
- 229910052710 silicon Inorganic materials 0.000 claims description 33
- 239000010703 silicon Substances 0.000 claims description 33
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 238000005530 etching Methods 0.000 claims description 22
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 21
- 239000000377 silicon dioxide Substances 0.000 claims description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims description 16
- 238000000151 deposition Methods 0.000 claims description 12
- 238000005121 nitriding Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 9
- 238000007254 oxidation reaction Methods 0.000 claims description 9
- 238000005468 ion implantation Methods 0.000 claims description 7
- 238000005137 deposition process Methods 0.000 claims description 6
- 239000013078 crystal Substances 0.000 claims description 5
- 238000000347 anisotropic wet etching Methods 0.000 claims description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 2
- 239000007789 gas Substances 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 15
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 12
- 239000012535 impurity Substances 0.000 description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 7
- 229910010271 silicon carbide Inorganic materials 0.000 description 7
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 6
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- WMFOQBRAJBCJND-UHFFFAOYSA-M Lithium hydroxide Chemical compound [Li+].[OH-] WMFOQBRAJBCJND-UHFFFAOYSA-M 0.000 description 5
- 239000012530 fluid Substances 0.000 description 5
- 239000000243 solution Substances 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 3
- 239000000460 chlorine Substances 0.000 description 3
- 229910052801 chlorine Inorganic materials 0.000 description 3
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000012528 membrane Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 239000012670 alkaline solution Substances 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 239000003595 mist Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02096—Cleaning only mechanical cleaning
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a transistor forming method. The method comprises steps: a substrate is provided, wherein the surface of the substrate has a gate structure; openings are formed inside the substrate at two sides of the gate structure; a stress layer is formed inside the opening, and a stop layer is formed on the surface of the stress layer, wherein the surface of the stress layer is equal to or higher than the surface of the substrate; after the stop layer is formed, a source region and a drain region are formed in the substrate at two sides of the gate structure and the stress layer; and after the source region and the drain region are formed, wet chemical cleaning is carried out on the substrate, the gate structure and the stress layer. Morphology of the stress layer in the formed transistor is good, and the performance of the transistor is stable.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of transistorized formation method.
Background technology
Transistor is just being widely used at present as the most basic semiconductor device, and along with the raising of component density and the integrated level of semiconductor device, transistorized grid size becomes than in the past shorter; But transistorized grid size shortens and can make transistor produce short-channel effect, and then produces leakage current, finally affects the electric property of semiconductor device.At present, prior art mainly, by improving the stress of transistor channel region, to improve carrier mobility, and then improves transistorized drive current, reduces the leakage current in transistor.
The method that prior art improves the stress of transistor channel region is, form stressor layers in transistorized source/drain region, wherein, the material of the transistorized stressor layers of PMOS is SiGe (SiGe), the compression forming because of lattice mismatch between silicon and SiGe, thus the transistorized performance of PMOS improved; The material of the stressor layers of nmos pass transistor is carborundum (SiC), the tension stress forming because of lattice mismatch between silicon and carborundum, thereby the performance of raising nmos pass transistor.
Prior art have stressor layers transistor forming process cross-sectional view as shown in Figure 1 to Figure 3, comprising:
Please refer to Fig. 1, Semiconductor substrate 10 is provided, described Semiconductor substrate 10 surfaces have grid structure 11, form mask layer 14 on Semiconductor substrate 10 surfaces, and described mask layer 14 exposes grid structure 11 and need to form substrate 10 surfaces of stressor layers.
Please refer to Fig. 2, taking mask layer 14 as mask, at the interior formation opening 12 of Semiconductor substrate 10 of described grid structure 11 both sides, the surface of the sidewall of described opening 12 and Semiconductor substrate 10 forms " Σ " (Sigma, Sigma) shape, and the drift angle of described " Σ " shape extends to grid structure 11.
Please refer to Fig. 3, in the interior formation stressor layers 13 of described opening 12, the material of described stressor layers 13 is SiGe or carborundum.After forming stressor layers 13, form silicon layer 15 on described stressor layers 13 surfaces, after follow-up formation source region and drain region, described silicon layer 15 surfaces form metal silicide contact layer by self-aligned silicide process.
After forming stressor layers 13 and silicon layer 15, adopt stressor layers 13 and silicon layer 15 interior formation source region or the drain region (not shown) of ion implantation technology in described grid structure 11 both sides; After forming source region and drain region, remove described mask layer 14.
But in the transistor forming with prior art, the pattern of stressor layers is bad, after the conductive interconnection line that follow-up formation is electrically connected with stressor layers, the loose contact in described conductive interconnection line and source region or drain region, the transistor performance forming is unstable.
Summary of the invention
The problem that the present invention solves is to provide a kind of transistorized formation method, makes formed stressor layers pattern good, ensures that transistor performance is stable.
For addressing the above problem, the invention provides a kind of transistorized formation method, comprising: substrate is provided, and described substrate surface has grid structure; In the substrate of described grid structure both sides, form opening; In described opening, form stressor layers, the surface of described stressor layers is equal to or higher than substrate surface; Form barrier layer on described stressor layers surface; Forming after barrier layer, in the substrate of grid structure both sides and stressor layers, form source region and drain region; After forming source region and drain region, described substrate, grid structure and stressor layers are carried out to wet chemical cleaning.
Optionally, the material on described barrier layer is silica or silicon nitride.
Optionally, the formation technique on described barrier layer is thermal oxidation technology or hot nitriding process.
Optionally, the formation technique on described barrier layer is atom layer deposition process.
Optionally, described grid structure comprises: the gate dielectric layer that is positioned at substrate surface; Be positioned at the gate electrode layer on gate dielectric layer surface; Be positioned at the pseudo-side wall of the substrate surface of gate dielectric layer and gate electrode layer both sides.
Optionally, also comprise: after forming stressor layers, before forming barrier layer, remove described pseudo-side wall.
Optionally, after forming stressor layers, before removing described pseudo-side wall, form silicon layer on described stressor layers surface; The barrier layer of follow-up formation covers the sidewall of described stressor layers and the sidewall of silicon layer and top surface.
Optionally, after forming barrier layer, form the second side wall in the grid structure both sides of removing pseudo-side wall.
Optionally, also comprise: after forming barrier layer, before forming the second side wall, adopt anisotropic dry etch process to remove the barrier layer of substrate surface.
Optionally, also comprise: be formed at second mask layer on gate electrode layer surface, mask when described the second mask layer forms gate dielectric layer and gate electrode layer as etching, the material of described the second mask layer is identical with the material of pseudo-side wall, and in removing pseudo-side wall, remove described the second mask layer.
Optionally, described grid structure also comprises: the first side wall of the substrate surface between pseudo-side wall and gate electrode layer, the material of described the first side wall is the combination of silica, silicon nitride or silicon oxynitride, and the surfacing that described the first side wall contacts with pseudo-side wall is not silicon nitride, after removing pseudo-side wall, expose described the first side wall.
Optionally, also comprise: before forming pseudo-side wall, adopt ion implantation technology to form light doping section in the substrate of gate electrode layer both sides.
Optionally, the material of described stressor layers is SiGe, and the formation technique of described stressor layers is selective epitaxial depositing operation.
Optionally, the formation technique of described opening is: form the first mask layer at described substrate surface, described the first mask layer exposes the substrate surface that need to form stressor layers of described grid structure and described grid structure both sides; Taking described the first mask layer and described grid structure as substrate described in mask etching, in the substrate of described grid structure both sides, form opening.
Optionally, sidewall and the substrate surface of described opening is " Σ " type, and the drift angle of described opening sidewalls extends to grid structure below, the technique of described the first mask layer etched substrate comprises: adopt substrate described in anisotropic dry etch process etching, in the substrate of grid structure both sides, form opening, the sidewall of described opening is vertical with substrate surface; The sidewall and the bottom that adopt opening described in anisotropic wet-etching technology etching, make the sidewall of described opening and substrate surface be " Σ " type, and the drift angle of described opening sidewalls extends to grid structure below.
Optionally, the material of described substrate is monocrystalline silicon, and the crystal orientation of described substrate surface is <100> or <110>.
Optionally, the formation technique in described source region and drain region is: after forming stressor layers, form photoresist layer at substrate and grid structure surface, described photoresist layer exposes the position that need to form source region and drain region; With described photoresist layer mask, adopt ion implantation technology to form source region and drain region in the stressor layers of grid structure both sides or substrate; After forming source region and drain region, remove described photoresist layer.
Compared with prior art, technical scheme of the present invention has the following advantages:
Form stressor layers in the substrate of grid structure both sides after, form barrier layer on described substrate, grid structure and stressor layers surface.Described barrier layer can cover the surface that described stressor layers is exposed; In wet chemical cleaning process after follow-up formation source region and drain region; described barrier layer can protect the surface of described stressor layers to avoid damage; thereby the stressor layers pattern that has ensured described formation is good; then ensured the stable of source region and drain region electric conductivity, made formed transistor performance good.
Further, after forming stressor layers and removing the pseudo-side wall in grid structure, before forming the second side wall, adopt anisotropic dry etch process to remove the barrier layer of substrate surface, and the barrier layer of substrate surface is removed and is conducive to the follow-up substrate surface in grid structure both sides and form accurate in size the second side wall.In the time that described stressor layers surface is also formed with silicon layer; because wet chemical cleaning is less to the damage of silicon layer; after described anisotropic time etching technics; described barrier layer can cover the stressor layers sidewall higher than substrate surface; the surperficial damaged that can avoid stressor layers to expose; and the silicon layer of stressor layers top surface can be protected the top surface of stressor layers, still can ensure that formed stressor layers pattern is good.
Brief description of the drawings
Fig. 1 to Fig. 3 is the cross-sectional view that prior art has the transistor forming process of stressor layers;
Fig. 4 be prior art in wet chemical cleaning process, the cross-sectional view that the stressor layers in transistor weathers;
Fig. 5 to Figure 10 is the cross-sectional view of the transistor forming process of embodiments of the invention.
Embodiment
As stated in the Background Art, the stressor layers pattern that adopts prior art to form is bad, and transistor performance is unstable.
In semiconductor fabrication process process, often need to adopt wet chemical to clean (Wet Chemical) technique and will in technical process, be attached to the Impurity removal of substrate or device surface.Study discovery through the present inventor, in the process that material, the especially silicon germanium material of stressor layers 13 as shown in Figure 3 easily cleans at described wet chemical, be corroded, and when the content of germanium in silicon germanium material higher, situation about being corroded is more serious.Please continue to refer to Fig. 3, after grid structure 11 formation source regions, both sides and drain region, need to carry out wet chemical cleaning and remove the impurity that is attached to substrate 10, grid structure 11 or stressor layers 13 surfaces.But in the process of cleaning at described wet chemical, the stressor layers 13 taking SiGe as material easily suffers erosion, and forms structure as shown in Figure 4.Please refer to Fig. 4, be subject to the impact of existing technique accuracy, stressor layers 13 surfaces that adopt selective epitaxial depositing operation to form are difficult to ensure completely and substrate 10 flush, therefore in existing technique, often make the surface of formed stressor layers 13 higher than substrate 10 surfaces, to ensure the performance of transistorized source region, drain region and channel region.But, even form silicon layer 15 on stressor layers 13 surfaces, described stressor layers 13 still has the surface that a part is exposed out, in the process of cleaning at wet chemical, the part that described stressor layers 13 is exposed out is corroded by wet-cleaned solution, forms depression, causes formed stressor layers 13 surface topographies bad, easily cause that electric conductivity between conductive interconnection line and source region or the drain region of follow-up formation is unstable, poor electric contact, formed transistor performance is impacted.
Further study through the present inventor, form stressor layers in the substrate of grid structure both sides after, form barrier layer on described substrate, grid structure and stressor layers surface.Described barrier layer can cover the surface that described stressor layers is exposed; In wet chemical cleaning process after follow-up formation source region and drain region; described barrier layer can protect the surface of described stressor layers to avoid damage; thereby the stressor layers pattern that has ensured described formation is good; then ensured the stable of source region and drain region electric conductivity, made formed transistor performance good.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 5 to Figure 10 is the cross-sectional view of the transistor forming process of embodiments of the invention.
Please refer to Fig. 5, substrate 200 is provided, described substrate 200 surfaces have grid structure 201.
Described substrate 200 is for subsequent technique provides workbench, and described substrate 200 is monocrystalline substrate or silicon-on-insulator (SOI) substrate.In the present embodiment, described substrate 200 has first area I, and described first area I is used to form the transistor with silicon Germanium stress layer, and described first area I isolates mutually by fleet plough groove isolation structure (unmarked) and other regions of substrate 200.The crystal orientation on described substrate 200 surfaces is <100> or <110>, the opening sidewalls forming in substrate so that follow-up can be " Σ " shape with substrate 200 surfaces, is <100> in the crystal orientation of the present embodiment.
Described grid structure 201 is formed at substrate 200 surfaces of first area I; In the present embodiment, other region surface of described substrate 200 are also formed with some transistorized grid structures (unmarked) that are used to form.Described grid structure 201 comprises: the gate dielectric layer 210 that is positioned at substrate 200 surfaces; Be positioned at the gate electrode layer 211 on gate dielectric layer 210 surfaces; Be positioned at second mask 212 on gate electrode layer 211 surfaces; Be positioned at first side wall 213 on substrate 200 surfaces of gate dielectric layer 210 and gate electrode layer 211 both sides; Be positioned at the pseudo-side wall 214 on substrate 200 surfaces of gate electrode layer 211 and the first side wall 213 both sides.
The formation technique of described grid structure 201 is: deposit gate dielectric membrane, be positioned at the gate electrode film on gate dielectric membrane surface with this on substrate 200 surfaces; Form the second mask layer 212 at gate electrode film surface deposition-etch, described the second mask layer 212 has defined position and the shape of gate electrode layer 211 and gate dielectric layer 210, the material of described the second mask layer 212 is the combination of silica, silicon nitride or silica and silicon nitride, in the present embodiment, the material of described the second mask layer 212 is silicon nitride, between described the second mask layer 212 and gate electrode layer, can also have silicon oxide layer; Taking described the second mask layer 212 as mask etching gate electrode film and gate dielectric membrane, form gate dielectric layer 210 and gate electrode layer 211; Adopt depositing operation and return etching technics and form the first side wall 213 and pseudo-side wall 214 on substrate 200 surfaces of gate dielectric layer 210 and gate electrode layer 211 both sides, in the present embodiment, the material of described the first side wall 213 is the combination of silica, silicon nitride or silica and silicon nitride, the material of described pseudo-side wall 214 is silicon nitride, and the surfacing that described the first side wall 213 and pseudo-side wall contact is not silicon nitride.It should be noted that, can also be before forming pseudo-side wall 214, adopt the substrate 200 interior formation light doping section of ion implantation technology in gate electrode layer 211 both sides.
In one embodiment, the material of described gate dielectric layer 210 is silica, and the material of described gate electrode layer 211 is polysilicon.In another embodiment, the material of described gate dielectric layer 210 is high K dielectric material, and the material of described 211 gate electrode layers is metal, and described grid structure 201 is used to form high-K metal gate (HKMG, High-k Metal Gate) transistor.When the material of described gate dielectric layer 210 is high K dielectric material, when the material of described gate electrode layer 211 is metal, after described grid structure 201 adopts, grid technique (Gate Last Process) forms, therefore in the time of current step, the locus of described gate dielectric layer 210 and gate electrode layer 211 is occupied by dummy gate layer, the material of described dummy gate layer is polysilicon, can also have silicon oxide layer and isolate between described dummy gate layer and substrate 200.Follow-up after forming source region and drain region, remove dummy gate layer and form gate dielectric layer 210 and gate electrode layer 211.
Please refer to Fig. 6, at the interior formation opening 202 of substrate 200 of described grid structure 201 both sides.
The formation technique of described opening 202 is: form the first mask layer 203 on described substrate 200 surfaces, described the first mask layer 203 exposes the substrate that need to form stressor layers 200 surfaces of described grid structure 201 and described grid structure 201 both sides; Taking described the first mask layer 203 and described grid structure 201 as substrate described in mask etching 200, at the interior formation opening 202 of substrate 200 of described grid structure 201 both sides, the material of described the first mask layer 203 is silicon nitride.
In the present embodiment, sidewall and the substrate surface of described opening 202 is " Σ " type, and the drift angle of described opening 202 sidewalls extends to grid structure 201 belows, technique with described the first mask layer 203 etched substrate 200 comprises: adopt substrate 200 described in anisotropic dry etch process etching, the interior formation opening of substrate 200 in grid structure 201 both sides, the sidewall of described opening is vertical with substrate 200 surfaces; The sidewall and the bottom that adopt opening described in anisotropic wet-etching technology etching, make the sidewall of described opening 202 and substrate surface be " Σ " type, and the drift angle of described opening 202 sidewalls extends to grid structure 201 belows.
Described anisotropic dry etch process is: etching gas comprises the mist of chlorine, hydrogen bromide or chlorine and hydrogen bromide, the flow of hydrogen bromide be 200 standard milliliters per minute～800 standard milliliters are per minute, the flow of chlorine be 20 standard milliliters per minute～100 standard milliliters are per minute, the flow of inert gas be 50 standard milliliters per minute～1000 standard milliliters are per minute, the pressure of etching cavity is 2 millitorr～200 millitorrs, and etch period is 15 seconds～60 seconds.
Described anisotropic wet-etching technology is: etching liquid comprises alkaline solution, and described alkaline solution is potassium hydroxide (KOH), NaOH (NaOH), lithium hydroxide (LiOH), ammoniacal liquor (NH
4oH) one or more combinations or in Tetramethylammonium hydroxide (TMAH).
In the present embodiment, the surface orientation of described substrate 200 is <100>, anisotropic wet-etch rate is vertical and be parallel in the direction on substrate 200 surfaces very fast, and in the direction of crystal orientation <111>, etch rate is the slowest, can make the sidewall of the first opening 202 and substrate 200 surfaces be " Σ " shape.
In another embodiment, in order to reduce processing step, can also only adopt with this anisotropic dry etch process and form opening, and form stressor layers in described opening, the sidewall of described opening, perpendicular to substrate 200 surfaces, forms " U " shape opening.
Please refer to Fig. 7, at described opening 202(as shown in Figure 6) in form stressor layers 204, the surface of described stressor layers 204 is equal to or higher than substrate 200 surfaces.
The material of described stressor layers 204 is SiGe or carborundum; In the time that first area I is used to form PMOS transistor, the material of described stressor layers 204 is SiGe, in the channel region of grid structure 201 belows, can obtain compression; In the time that first area I is used to form nmos pass transistor, the material of described stressor layers 204 is carborundum, in the channel region of grid structure 201 belows, can obtain tension stress.In the present embodiment, the material of described stressor layers 204 is SiGe, and first area I forms PMOS transistor.
The formation technique of described stressor layers 204 is selective epitaxial depositing operation, and the temperature of described selective epitaxial depositing operation is 500 degrees Celsius～800 degrees Celsius, and air pressure is 1 holder～100 holder, and deposition gases comprises silicon source gas (SiH
4or SiH
2cl
2) and germanium source gas (GeH
4) or carbon-source gas (CH
4, CH
3cl or CH
2cl
2), the flow of described silicon source gas, germanium source gas or carbon-source gas is 1 standard ml/min～1000 standard ml/min; In the present embodiment, reacting gas is SiH
4and GeH
4; The gas of described selective epitaxial depositing operation also comprises HCl and H
2, the flow of described HCl is 1 standard ml/min～1000 standard ml/min, H
2flow be 0.1 standard liter/min～50 standard liter/min.
In the present embodiment, after forming stressor layers 204, adopt selective epitaxial depositing operation to form silicon layer 205 on described stressor layers 204 surfaces; Described silicon layer 205 surfaces form metal silicide contact layer by self-aligned silicide process in subsequent technique, for being electrically connected the follow-up conductive plunger that is formed at source region or surface, drain region.
In semiconductor technology manufacture process, often need to carry out wet chemical cleaning, to remove the impurity that is attached to substrate or semiconductor device structure surface, the cleaning fluid of described wet chemical cleaning comprises hydrofluoric acid, SC-1 solution or SPM solution etc., and these cleaning fluids can reach for dissimilar impurity the object of removing; But the easy counter stress layer 204 of described wet chemical cleaning causes erosion, when especially cleaning fluid comprises hydrofluoric acid, the stressor layers 204 that is easily material to SiGe causes damage; And inventor is through research discovery, when the Ge content in silicon germanium material is higher, the erosion being subject to is more serious.In the present embodiment, if in follow-up wet chemical cleaning process, stressor layers 204 surfaces have the part of exposure, can cause the pattern of stressor layers 204 bad, affect the electrical connection properties of the follow-up conductive plunger that is formed at source region or surface, drain region.
But, because the formation technique of described stressor layers 204 is selective epitaxial depositing operation, be subject to the restriction of existing selective epitaxial depositing operation accuracy, described stressor layers 204 is difficult to ensure completely and substrate 200 flush, therefore existing technique often makes the surface of described stressor layers 204 higher than described substrate 200 surfaces, to ensure the electrical property of source region, drain region or channel region.In the present embodiment, the surface of described stressor layers 204 is higher than substrate 200 surfaces.But, even form again silicon layer 205 on described stressor layers 204 surfaces, described stressor layers 204 is still exposed out higher than the partial sidewall on substrate 200 surfaces, carry out wet chemical cleaning after follow-up formation source region and drain region time, easily corrode the exposed surface of described stressor layers 204 and form depression, thereby affecting the performance of stressor layers 204.
Therefore; the present embodiment is follow-up forms barrier layer on substrate 200, stressor layers 204 and silicon layer 205 surfaces; described barrier layer can be in wet chemical cleaning process, protects described stressor layers 204 injury-free, thereby has ensured that stressor layers 204 patterns that form are good.
Please refer to Fig. 8, after forming stressor layers 204 and silicon layer 205, remove described pseudo-side wall 214(as shown in Figure 7), the first mask layer 203(as shown in Figure 7) and the second mask 212(as shown in Figure 7).
Because described pseudo-side wall 214 is for defining formed opening 202(as shown in Figure 6) and the position of stressor layers 204, and, in the etching technics of formation opening 202, described pseudo-side wall 214 inevitably sustains damage and is thinned, therefore need to remove described pseudo-side wall 214 and form accurate in size the second side wall at gate electrode layer 211 and the first side wall 213 both sides, to define the source region of follow-up formation and the position in drain region.
In the present embodiment, the material of described pseudo-side wall 214 is silicon nitride, and the technique of removing described pseudo-side wall 214 is wet-etching technology, and etching liquid comprises phosphoric acid.In the present embodiment, the material of described the first mask 203 and the second mask layer 212 is also silicon nitride, and therefore described the second mask 212 can be removed with described pseudo-side wall 214 simultaneously, makes the second side wall size of follow-up formation accurate.
Please refer to Fig. 9, removing described pseudo-side wall 214(as shown in Figure 7) afterwards, form barrier layer 206 at described substrate 200 surfaces, grid structure 201 surfaces, the sidewall surfaces of stressor layers 204 and the sidewall of silicon layer 205 and top surface.
The material on described barrier layer 206 is silica or silicon nitride; In the time that the material on described barrier layer 206 is silica, the formation technique on described barrier layer 206 is thermal oxidation technology; When the material on described barrier layer 206 is silicon nitride, the formation technique on described barrier layer 206 is hot nitriding process.Described barrier layer 206 can be in follow-up formation source region and drain region, and removes in the wet chemical cleaning after photoresist layer, and the stressor layers 206 that protection SiGe is material is avoided corroding, and makes the pattern of stressor layers 206 good.
Described thermal oxidation technology or hot nitriding process can only form barrier layer 206 on substrate 200, stressor layers 204 and silicon layer 205 surfaces, and described gate electrode layer 211 surfaces have silicon oxide layer (not shown) and can not form barrier layer 206.And, barrier layer 206 thickness that described thermal oxidation technology or hot nitriding process form are controlled and covering power good, can cover the sidewall of described stressor layers 204 higher than substrate 200 parts, and can make the thinner thickness on described barrier layer 206, do not affect the dimensional accuracy of follow-up the second side wall forming in gate electrode layer 211 and the first side wall 213 both sides.In addition, because the chemical property of silicon is more active than germanium, in hot nitriding process or thermal oxidation technology, can be first with gas reaction and form silicon nitride or silica.
In the present embodiment, adopt hot nitriding process to form silicon nitride barrier 206, the gas of described hot nitriding process comprises ammonia (NH
4), temperature is greater than 600 degrees Celsius, and the time is 1 minute～30 minutes, and the thickness of the silicon nitride barrier 206 forming is 1 nanometer～5 nanometer.The speed of growth of described hot nitriding process is slower, makes the gauge on barrier layer 206 more accurately controlled; And the gas of hot nitriding process is easy to enter in the groove between grid structure 201 and stressor layers 204, make barrier layer 206 better quality, the covering power of formation better; In addition, silicon nitride is difficult for being removed by hydrofluoric acid, can protect stressor layers 204.
In another embodiment, adopt thermal oxidation technology to form silica barrier layer 206, the gas of described thermal oxidation technology is oxygen, and temperature is 700 degrees Celsius～1000 degrees Celsius, time is 1 minute～30 minutes, and the thickness of the silica barrier layer 206 forming is 1 nanometer～5 nanometer.It is fast that described thermal oxidation technology forms the speed on barrier layer 206, is conducive to reduce the process time; But described silica is easily removed by hydrofluoric acid, therefore, the thickness of described silica barrier layer 206 need to guarantee in cleaning process, to protect stressor layers 204, and can in cleaning process, not be completely removed.
In other embodiments, the formation technique on described barrier layer 206 is atom layer deposition process, the temperature of described atom layer deposition process is 350 degrees Celsius～550 degrees Celsius, and air pressure is 0.1 holder～0.5 holder, and the thickness on the barrier layer 206 forming is 1 nanometer～5 nanometer.The barrier layer 206 forming covers substrate 200, stressor layers 204, silicon layer 205 and grid structure 201 surfaces; Barrier layer 206 thin thickness and covering power that described atom layer deposition process forms are good, and the barrier layer of substrate 200 and grid structure 201 top surfaces can be removed by anisotropic dry etch process follow-up.
Please refer to Figure 10, adopt anisotropic dry etch process to remove the barrier layer 206 on substrate 200 surfaces, and after removing the barrier layer 206 on substrate 200 surfaces, form the second side wall 215 on substrate 200 surfaces of grid structure 201 both sides.
In the time adopting hot nitrogenize or hot nitriding process to form barrier layer 206, substrate 200 surfaces between described grid structure 201 and stressor layers also have barrier layer 206 and cover, if directly form the second side wall 215 on 206 surfaces, described barrier layer, can cause the second formed side wall 215 size inaccuracy.
In another embodiment, described employing atom layer deposition process forms barrier layer 206, substrate 200 and grid structure 201 surfaces are all coated with barrier layer 206, need to adopt equally anisotropic dry etch process to remove, accurate to ensure the size of the second side wall 215.
In the present embodiment, remove the barrier layer 206 on substrate 200 surfaces before forming the second side wall 215, the method on the barrier layer 206 on described removal substrate 200 surfaces is anisotropic dry etch process, and the etching gas of described anisotropic dry etching comprises CF
4, H
2and O
2, air pressure is 0.1 millitorr～100 millitorr, etch period is 15 seconds～60 seconds.Described anisotropic dry etch process can retain the barrier layer 206 of described stressor layers 204 and silicon layer 205 sidewall surfaces; thereby in follow-up cleaning process, protect described stressor layers 206 surfaces; remove the barrier layer 206 on substrate 200 surfaces, to form accurate in size the second side wall 215 simultaneously.
The material of described the second side wall 215 is the combination of silica, silicon nitride or silica and silicon nitride, the formation technique of described the second side wall 215 is depositing operation and time etching technics, and described the second side wall 215 is for defining the source region of follow-up formation and the position of drain region (not shown).
The formation technique in described source region and drain region is: after forming barrier layer 206 and the second side wall 215, form photoresist layer (not shown) at substrate 200 and grid structure 201 surfaces, described photoresist layer has defined the position in source region and drain region, taking described photoresist layer as mask, adopt stressor layers 204 or substrate 200 interior formation source region and the drain region of ion implantation technology in grid structure 201 both sides.In the present embodiment, described first area I is used to form PMOS transistor, and the material of described stressor layers 204 is SiGe, and the ion that therefore described source region and drain region are injected is p-type ion.
Please continue to refer to Figure 10, after forming source region and drain region, remove described photoresist layer, and described substrate 200, grid structure 201 and stressor layers 204 are carried out to wet chemical cleaning.
After forming source region and drain region, need to remove described photoresist layer, to carry out follow-up technique, for example, form stressor layers in the grid structure both sides in substrate 200 other regions, and the material of described stressor layers can be carborundum, make described grid structure can form nmos pass transistor.But, after removing photoresist layer, the impurity that preorder technique produces is easily adhered on the semiconductor device structure surface on described substrate 200 and surface thereof, for example oxide and organic substance, therefore before carrying out subsequent process steps, need to clean the semiconductor device structure on substrate 200 and surface thereof, to remove described impurity.
In the present embodiment, adopt wet chemical cleaning to remove impurity, the cleaning fluid of described wet chemical cleaning comprises hydrofluoric acid, SC-1 solution or SPM solution etc., can remove dissimilar impurity such as oxide, metal ion or organic substance etc.Wherein, hydrofluoric acid easily causes corrosion to silicon germanium material; and in the present embodiment; stressor layers 204 taking SiGe as material is blocked layer 206 higher than the sidewall on substrate 200 surfaces and covers; can in described wet chemical cleaning process, protect described stressor layers 204 to avoid damage; thereby the pattern that ensures described stressor layers 204 is good, make formed transistor performance stable.
The present embodiment, after forming silicon Germanium stress layer and silicon layer, adopt hot nitriding process to form barrier layer in stressor layers higher than the sidewall sections of substrate surface, and described stressor layers top surface has silicon layer; In the formation that completes source region and drain region; and after removing photoresist layer; carry out wet chemical cleaning while removing substrate or semiconductor device structure surface assorted; described silicon Germanium stress layer is all protected higher than the part of substrate surface; therefore stressor layers can not be subject to the erosion of cleaning fluid, has ensured that the pattern of stressor layers is good.
In sum, form stressor layers in the substrate of grid structure both sides after, form barrier layer on described substrate, grid structure and stressor layers surface.Described barrier layer can cover the surface that described stressor layers is exposed; In wet chemical cleaning process after follow-up formation source region and drain region; described barrier layer can protect the surface of described stressor layers to avoid damage; thereby the stressor layers pattern that has ensured described formation is good; then ensured the stable of source region and drain region electric conductivity, made formed transistor performance good.
Further, after forming stressor layers and removing the pseudo-side wall in grid structure, before forming the second side wall, adopt anisotropic dry etch process to remove the barrier layer of substrate surface, and the barrier layer of substrate surface is removed and is conducive to the follow-up substrate surface in grid structure both sides and form accurate in size the second side wall.In the time that described stressor layers surface is also formed with silicon layer; because wet chemical cleaning is less to the damage of silicon layer; after described anisotropic time etching technics; described barrier layer can cover the stressor layers sidewall higher than substrate surface; the surperficial damaged that can avoid stressor layers to expose; and the silicon layer of stressor layers top surface can be protected the top surface of stressor layers, still can ensure that formed stressor layers pattern is good.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (17)
1. a transistorized formation method, is characterized in that, comprising:
Substrate is provided, and described substrate surface has grid structure;
In the substrate of described grid structure both sides, form opening;
In described opening, form stressor layers, the surface of described stressor layers is equal to or higher than substrate surface;
Form barrier layer on described stressor layers surface;
Forming after barrier layer, in the substrate of grid structure both sides and stressor layers, form source region and drain region;
After forming source region and drain region, described substrate, grid structure and stressor layers are carried out to wet chemical cleaning.
2. transistorized formation method as claimed in claim 1, is characterized in that, the material on described barrier layer is silica or silicon nitride.
3. transistorized formation method as claimed in claim 2, is characterized in that, the formation technique on described barrier layer is thermal oxidation technology or hot nitriding process.
4. transistorized formation method as claimed in claim 2, is characterized in that, the formation technique on described barrier layer is atom layer deposition process.
5. transistorized formation method as claimed in claim 1, is characterized in that, described grid structure comprises: the gate dielectric layer that is positioned at substrate surface; Be positioned at the gate electrode layer on gate dielectric layer surface; Be positioned at the pseudo-side wall of the substrate surface of gate dielectric layer and gate electrode layer both sides.
6. transistorized formation method as claimed in claim 5, is characterized in that, also comprises: after forming stressor layers, before forming barrier layer, remove described pseudo-side wall.
7. transistorized formation method as claimed in claim 6, is characterized in that, after forming stressor layers, before removing described pseudo-side wall, forms silicon layer on described stressor layers surface; The barrier layer of follow-up formation covers the sidewall of described stressor layers and the sidewall of silicon layer and top surface.
8. transistorized formation method as claimed in claim 7, is characterized in that, after forming barrier layer, forms the second side wall in the grid structure both sides of removing pseudo-side wall.
9. transistorized formation method as claimed in claim 8, is characterized in that, also comprises: after forming barrier layer, before forming the second side wall, adopt anisotropic dry etch process to remove the barrier layer of substrate surface.
10. transistorized formation method as claimed in claim 6, it is characterized in that, also comprise: the second mask layer that is formed at gate electrode layer surface, mask when described the second mask layer forms gate dielectric layer and gate electrode layer as etching, the material of described the second mask layer is identical with the material of pseudo-side wall, and in removing pseudo-side wall, remove described the second mask layer.
11. transistorized formation methods as claimed in claim 6, it is characterized in that, described grid structure also comprises: the first side wall of the substrate surface between pseudo-side wall and gate electrode layer, the material of described the first side wall is the combination of silica, silicon nitride or silicon oxynitride, and the surfacing that described the first side wall contacts with pseudo-side wall is not silicon nitride, after removing pseudo-side wall, expose described the first side wall.
12. transistorized formation methods as claimed in claim 5, is characterized in that, also comprise: before forming pseudo-side wall, adopt ion implantation technology to form light doping section in the substrate of gate electrode layer both sides.
13. transistorized formation methods as claimed in claim 1, is characterized in that, the material of described stressor layers is SiGe, and the formation technique of described stressor layers is selective epitaxial depositing operation.
14. transistorized formation methods as claimed in claim 1, it is characterized in that, the formation technique of described opening is: form the first mask layer at described substrate surface, described the first mask layer exposes the substrate surface that need to form stressor layers of described grid structure and described grid structure both sides; Taking described the first mask layer and described grid structure as substrate described in mask etching, in the substrate of described grid structure both sides, form opening.
15. as right want 14 as described in transistorized formation method, it is characterized in that, sidewall and the substrate surface of described opening is " Σ " type, and the drift angle of described opening sidewalls extends to grid structure below, the technique of described the first mask layer etched substrate comprises: adopt substrate described in anisotropic dry etch process etching, in the substrate of grid structure both sides, form opening, the sidewall of described opening is vertical with substrate surface; The sidewall and the bottom that adopt opening described in anisotropic wet-etching technology etching, make the sidewall of described opening and substrate surface be " Σ " type, and the drift angle of described opening sidewalls extends to grid structure below.
16. transistorized formation methods as claimed in claim 15, is characterized in that, the material of described substrate is monocrystalline silicon, and the crystal orientation of described substrate surface is <100> or <110>.
17. transistorized formation methods as claimed in claim 1, it is characterized in that, the formation technique in described source region and drain region is: after forming stressor layers, form photoresist layer at substrate and grid structure surface, described photoresist layer exposes the position that need to form source region and drain region; With described photoresist layer mask, adopt ion implantation technology to form source region and drain region in the stressor layers of grid structure both sides or substrate; After forming source region and drain region, remove described photoresist layer.
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