CN113948395A - Threshold voltage adjusting method of FinFET - Google Patents

Threshold voltage adjusting method of FinFET Download PDF

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Publication number
CN113948395A
CN113948395A CN202111097919.3A CN202111097919A CN113948395A CN 113948395 A CN113948395 A CN 113948395A CN 202111097919 A CN202111097919 A CN 202111097919A CN 113948395 A CN113948395 A CN 113948395A
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finfet
threshold voltage
dielectric layer
voltage adjustment
input
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李勇
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

The invention discloses a threshold voltage adjusting method of a FinFET, which comprises the following steps: step one, providing a semiconductor substrate which is subjected to a chemical mechanical polishing process of a zeroth interlayer film, wherein the semiconductor substrate comprises a core area and an input/output area; the method comprises the following steps that a fin body, a shallow trench isolation dielectric layer, a first gate dielectric layer and a polycrystalline silicon pseudo gate are formed on a semiconductor substrate, and the first gate dielectric layer is directly used as a gate dielectric layer of an input/output FinFET in an input/output area; step two, removing the polycrystalline silicon pseudo gate in the core area; step three, adjusting and injecting threshold voltage; in the core region, adjusting and injecting a threshold voltage into a first gate dielectric layer penetrating through the top of the top part of the fin body; removing the first photoresist pattern, and protecting the first gate dielectric layer in the input and output area; fourthly, annealing and activating the impurities injected by adjusting the threshold voltage; and step five, performing a metal gate replacement process. The method can avoid damage to the fin body and the gate dielectric layer of the input-output FinFET after threshold voltage adjustment injection.

Description

Threshold voltage adjusting method of FinFET
Technical Field
The present invention relates to the Field of semiconductor integrated circuit manufacturing, and in particular, to a method for adjusting a threshold voltage of a Fin Field Effect Transistor (FinFET).
Background
The FinFET forming process comprises a step of threshold voltage adjusting injection, and the step is used for setting the doping concentration of the surface of a channel region and enabling the threshold voltage of the device to meet requirements.
Fig. 1 is a schematic diagram of a corresponding device structure when performing threshold voltage adjustment implantation in a first FinFET threshold voltage adjustment method in the prior art; the existing first method for adjusting the threshold voltage of a FinFET includes the following steps:
providing a semiconductor substrate 101a, forming fins 101 formed by performing patterned etching on the semiconductor substrate 101a, filling shallow trench isolation dielectric layers 102 in spaced areas between the fins 101, wherein the shallow trench isolation dielectric layers 102 are typically oxide layers, and forming lining oxide layers 102a on inner side surfaces of the spaced areas between the fins 101.
Typically, the patterned etching of the search fin 101 will also employ a hard mask layer, which is typically a stack of silicon oxide 105 and silicon nitride.
The first conventional method is to perform threshold voltage adjustment implantation (Vt implantation) and form a threshold voltage adjustment implantation region 104 under the condition of only remaining silicon oxide 105 after removing the silicon nitride of the hard mask layer; the arrowed line corresponding to reference 103 in fig. 1 represents the threshold voltage adjustment implant.
The impurities of threshold voltage adjustment implant region 104 are then activated by annealing.
In general, the shallow trench isolation dielectric layer 102 may further include a well implantation step after formation of the well region, and the annealing of the well region may be performed after the threshold voltage adjustment implantation, so that the annealing process of the well region may be used to simultaneously perform impurity activation on the threshold voltage adjustment implantation region 104.
The subsequent steps required to form the FinFET may then be performed, including:
a Fin reveal (Fin reveal) process is performed to etch the shallow trench isolation dielectric layer 102 in the spaced areas on both sides of the Fin 101 so that the top surface of the shallow trench isolation dielectric layer 102 is lower than the top surface of the Fin 101, and thus the top portion of the Fin 101 is exposed on the shallow trench isolation dielectric layer 102.
And then, carrying out a first gate dielectric layer forming process. Typically, a Core (Core) region and an input/output (IO) region are included on the same semiconductor substrate 101a, the finfets in the input/output region are input/output finfets, and the finfets in the Core region are Core finfets. The gate dielectric layer of the input/output FinFET is thicker, so that the first gate dielectric layer is usually directly adopted as the gate dielectric layer of the subsequent input/output FinFET in the input/output region; while the first gate dielectric layer in the core region may be removed during the metal gate replacement process and may reform the gate dielectric layer required for the core FinFET, the gate dielectric layer of the core FinFET typically comprises a high dielectric constant (HK) material. The gate dielectric layer of the input-output FinFET is typically an oxide layer and is formed using an in-situ water vapor growth process (ISSG).
Then, a polysilicon circulation (Poly loop) process step is performed. The polysilicon circulation process forms a pattern structure on the polysilicon dummy.
And then, forming a side wall, a source drain region and the like required by the FinFET by using the polycrystalline silicon pseudo gate, wherein the forming process of the source drain region comprises the forming process of an embedded epitaxial layer.
As shown in fig. 1, when the threshold voltage adjustment implantation 103 is performed, the Fin 101 is most likely to be damaged (Fin Damage) because the silicon nitride of the hard mask layer is removed and there is no protection structure on the top of the Fin 101; in addition, most of the implantation impurities of the threshold voltage adjustment implantation 103 are implanted to the outside of the fin 101, so that dose loss (dose loss) occurs.
Fig. 2 is a schematic diagram of a corresponding device structure when performing threshold voltage adjustment implantation in a second FinFET threshold voltage adjustment method in the prior art; the existing second method for adjusting the threshold voltage of a FinFET includes the following steps:
the difference between the existing second FinFET threshold voltage adjustment method and the existing first FinFET threshold voltage adjustment method is: in the second conventional method for adjusting the threshold voltage of the FinFET, the threshold voltage adjustment injection is performed after the first gate dielectric layer 106 is formed by an in-situ water vapor growth process (ISSG). That is, after the Fin 101 top exposure (Fin real) process is completed and the first gate dielectric layer 106 is formed on the surface of the exposed top portion of the Fin 101, the threshold voltage adjustment implantation is performed as indicated by the arrow line corresponding to the mark 103 a. As can be seen from fig. 2, the top portion of the fin 101 is exposed, and the threshold voltage adjustment implantation can be performed by angled implantation, so that the implantation sensitivity is good and the threshold voltage adjustment is facilitated. Generally, a photoresist pattern is formed before the threshold voltage adjustment implantation to define an implantation region, and then the photoresist pattern is removed, so that the first gate dielectric layer 106 is directly exposed, and thus damage may be generated in the photoresist removal process. The first gate dielectric layer 106 may directly serve as a gate dielectric layer of the input/output FinFET, which may adversely affect the performance of the input/output FinFET.
Disclosure of Invention
The invention aims to provide a threshold voltage adjusting method of a FinFET, which can avoid damage to a fin body and a gate dielectric layer of an input/output FinFET after threshold voltage adjustment injection.
In order to solve the above technical problem, the threshold voltage adjusting method of the FinFET provided in the present invention includes the following steps:
the method comprises the steps of firstly, providing a semiconductor substrate which is subjected to a chemical mechanical polishing process of a zeroth interlayer film, wherein the FinFET comprises a core FinFET and an input-output FinFET, the semiconductor substrate comprises a core region and an input-output region, the core region is a forming region of the core FinFET, and the input-output region is a forming region of the input-output FinFET.
The semiconductor substrate is provided with fin bodies, shallow trench isolation medium layers, first gate medium layers and polycrystalline silicon pseudo gates, the shallow trench isolation medium layers are located between the fin bodies, the top portions of the fin bodies are located on the top surfaces of the shallow trench isolation medium layers, well regions are formed in the top portions of the fin bodies, the first gate medium layers cover the side surfaces and the top surfaces of the top portions of the fin bodies, the polycrystalline silicon pseudo gates are formed on the first gate medium layers in a covering mode, the well regions covered by the polycrystalline silicon pseudo gates serve as channel regions of the FinFET, the zero layer interlayer films completely fill the regions between the polycrystalline silicon pseudo gates, and the top surfaces of the zero layer interlayer films are flush with the top surfaces of the polycrystalline silicon pseudo gates.
In the input-output area, the first gate dielectric layer is directly used as the gate dielectric layer of the input-output FinFET, and in the first step, the first gate dielectric layer is directly grown according to the thickness requirement of the gate dielectric layer of the input-output FinFET.
And step two, carrying out first polysilicon etching to remove the polysilicon dummy gate in the core area and reserve the polysilicon dummy gate in the input and output area.
And step three, performing threshold voltage adjustment injection, wherein the area of the threshold voltage adjustment injection is defined by a first photoresist pattern formed by a photoetching process.
In the core region, the threshold voltage adjustment implant penetrates through the first gate dielectric layer at the top of the top portion of the fin body and then enters the top portion of the fin body and achieves adjustment of doping of the channel region of the core FinFET and thus adjustment of the threshold voltage of the core FinFET.
And removing the first photoresist pattern, and in the input and output region, protecting the first gate dielectric layer in the process of removing the photoresist pattern by using the characteristic that the first gate dielectric layer is buried at the bottom of the polycrystalline silicon pseudo gate.
And step four, annealing and activating the impurities injected by adjusting the threshold voltage.
And step five, performing a metal gate replacement process.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
The further improvement is that the step five comprises the following sub-steps:
and step 51, carrying out second polysilicon etching to remove the polysilicon dummy gate of the input and output area.
And step 52, removing the first gate dielectric layer in the core region, and reserving the first gate dielectric layer in the input and output region.
And 53, forming a gate dielectric layer of the core FinFET, and forming metal gates of the core FinFET and the input-output FinFET.
In a further improvement, the gate dielectric layer of the core FinFET in step 53 comprises a high dielectric constant layer.
In a further improvement, the first gate dielectric layer is made of an oxide layer.
The further improvement is that the first gate dielectric layer is formed by adopting an in-situ water vapor growth process.
A further improvement is to omit step four and to achieve activation of the threshold voltage adjustment implanted dopants directly using the thermal process of forming the high dielectric constant layer of the gate dielectric layer of the core FinFET in step 53.
In a further refinement, the material of the high dielectric constant layer comprises hafnium oxide.
In a further improvement, in the first step, the fin body is formed by performing patterned etching on the semiconductor substrate.
The further improvement is that the shallow trench isolation dielectric layer is formed by adopting a deposition and etch-back process, and the shallow trench isolation dielectric layer can completely fill the interval region between the fin bodies after the deposition of the shallow trench isolation dielectric layer is finished; and after the back etching process of the shallow trench isolation medium layer is completed, the shallow trench isolation medium layer is only positioned in the bottom area of the interval area between the fin bodies and exposes the top parts of the fin bodies.
The further improvement is that the well region is formed by performing an ion injection and push well process under the condition that the shallow trench isolation medium layer completely fills the spacing region between the fin bodies and the top surfaces of the shallow trench isolation medium layer and the fin bodies are the same after the shallow trench isolation medium layer is deposited, and performing a back etching process of the shallow trench isolation medium layer after the well region is formed.
In the first step, after the polysilicon dummy gate is formed, a step of forming an embedded epitaxial layer in the fin body on both sides of the polysilicon dummy gate and a step of performing source-drain injection to form a source region and a drain region are further included, and the source region and the drain region are located in the embedded epitaxial layer.
In a further refinement, in step three, the threshold voltage adjustment implant used to adjust the threshold voltage of the core FinFET employs an angled ion implant.
In a further refinement, said core finfets include N-type core finfets and P-type core finfets, said threshold voltage adjustment implant for adjusting a threshold voltage of said N-type core finfets and for adjusting a threshold voltage of said P-type core finfets are performed separately.
A further improvement is that, in step three, in the input-output region, the threshold voltage adjustment implant of the input-output FinFET is adjusted as needed, and the threshold voltage adjustment implant of the input-output FinFET is adjusted to penetrate through the polysilicon dummy gate and the first gate dielectric layer at the top of the top portion of the fin body and then enter the top portion of the fin body.
The invention makes special setting for the sequence of threshold voltage adjustment injection in the whole process flow and makes special setting for the removal process of the polycrystalline silicon pseudo gate, wherein the polycrystalline silicon pseudo gate in the core area is removed and the polycrystalline silicon pseudo gate in the input and output area is reserved by the first polycrystalline silicon etching, the threshold voltage adjustment injection is placed after the first polycrystalline silicon etching, and the first gate dielectric layer of the input and output area can be prevented from being damaged when the photoresist defining the threshold voltage adjustment injection area is removed by utilizing the reserved characteristic of the polycrystalline silicon pseudo gate in the input and output area, so that the device performance of the input and output FinFET can not be influenced.
Meanwhile, the threshold voltage adjustment injection of the core region is similar to the threshold voltage adjustment injection of the second existing method, so that the sensitivity of the threshold voltage adjustment injection of the core region is good, the threshold voltage adjustment is convenient, and the device performance of the core FinFET can be improved. While the sensitivity of the input-output FinFET to threshold voltage adjustment injection is not as high as that of the core FinFET, the present invention can still perform very good threshold voltage adjustment on the input-output FinFET.
Compared with the prior first method which needs higher injection energy when the injection is directly carried out from the top of the fin body so as to damage the fin body, the threshold voltage adjustment injection of the core region can realize the injection with the inclination angle and can be realized by adopting the injection which does not damage the fin body; the threshold voltage of the input and output area can pass through the polycrystalline silicon pseudo gate during adjustment and injection, so that the fin body cannot be damaged, and the damage of the threshold voltage adjustment and injection to the fin body can be avoided.
Therefore, the method can avoid damage to the fin body and the gate dielectric layer of the input-output FinFET after threshold voltage adjustment injection, and can improve the sensitivity of the threshold voltage of the core FinFET, so that the performance of the core FinFET and the performance of the input-output FinFET are improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a schematic structural diagram of a corresponding device during threshold voltage adjustment implantation in a first method for adjusting threshold voltage of a FinFET in the prior art;
fig. 2 is a schematic diagram of a corresponding device structure when threshold voltage adjustment implantation is performed in a second FinFET threshold voltage adjustment method in the prior art;
FIG. 3 is a flow chart of a threshold voltage adjustment method of a FinFET in accordance with an embodiment of the present invention;
fig. 4A-4F are schematic diagrams of device structures in steps of a method for threshold voltage adjustment of a FinFET in accordance with an embodiment of the present invention.
Detailed Description
FIG. 3 is a flow chart of a threshold voltage adjustment method for a FinFET according to an embodiment of the present invention; fig. 4A to 4F are schematic diagrams of device structures in steps of a threshold voltage adjusting method of a FinFET according to an embodiment of the present invention; the threshold voltage adjusting method of the FinFET comprises the following steps:
step one, as shown in fig. 4A, a semiconductor substrate 201a is provided, in which a chemical mechanical polishing process of the zeroth interlayer film 202 is completed, the FinFET includes a core FinFET and an input/output FinFET, the semiconductor substrate 201a includes a core region 301 and an input/output region 302, the core region 301 is a formation region of the core FinFET, and the input/output region 302 is a formation region of the input/output FinFET. In fig. 4A, the core area 301 is located on the left side of the line AA, and the input-output area 302 is located on the right side of the line AA.
The semiconductor substrate 201a is formed with a fin body 201, a shallow trench isolation dielectric layer 202 and a first gate dielectric layer 203. Typically, a plurality of fins 201 are included on the semiconductor substrate 201 a. Only 3 of the fins 201 are shown in fig. 4A.
As shown in fig. 4B, a step of forming a polysilicon dummy gate 204 is further included after forming the first gate dielectric layer 203. In fig. 4B, for convenience of representation, only the polysilicon dummy gate 204 is shown to cover the fins 201 at the same time; in an actual process, the pattern structure of the polysilicon dummy gate 204 can be set as required.
The shallow trench isolation dielectric layer 202 is located between the fin bodies 201, the top portions of the fin bodies 201 are located on the top surfaces of the shallow trench isolation dielectric layers 202, well regions are formed in the top portions of the fin bodies 201, the first gate dielectric layer 203 covers the side surfaces and the top surfaces of the top portions of the fin bodies 201, the polycrystalline silicon dummy gates 204 cover the first gate dielectric layer 203, the well regions covered by the polycrystalline silicon dummy gates 204 serve as channel regions of the FinFET, the zero-level interlayer film 202 completely fills the regions between the polycrystalline silicon dummy gates 204, and the top surfaces of the zero-level interlayer films 202 are parallel to the top surfaces of the polycrystalline silicon dummy gates 204.
In the input/output region 302, the first gate dielectric layer 203 is directly used as a gate dielectric layer of the input/output FinFET, and in step one, the first gate dielectric layer 203 is directly grown according to the thickness requirement of the gate dielectric layer of the input/output FinFET.
In the method according to the embodiment of the present invention, the semiconductor substrate 201a includes a silicon substrate.
The first gate dielectric layer 203 is made of an oxide layer.
The first gate dielectric layer 203 is formed by an in-situ water vapor growth process.
The fin body 201 is formed by performing patterned etching on the semiconductor substrate 201 a.
The shallow trench isolation dielectric layer 202 is formed by adopting a deposition and etch-back process, and after the deposition of the shallow trench isolation dielectric layer 202 is completed, the shallow trench isolation dielectric layer 202 can completely fill the space between the fin bodies 201; after the etching back process of the shallow trench isolation dielectric layer 202 is completed, the shallow trench isolation dielectric layer 202 is only located in the bottom region of the spacer between the fin bodies 201 and exposes the top portions of the fin bodies 201.
The well region is formed by performing an ion injection and push well process under the condition that the shallow trench isolation dielectric layer 202 completely fills the spacer region between the fin bodies 201 and the top surfaces of the shallow trench isolation dielectric layer 202 and the fin bodies 201 are the same after the shallow trench isolation dielectric layer 202 is deposited, and performing a back etching process of the shallow trench isolation dielectric layer 202 after the well region is formed.
After the polysilicon dummy gate 204 is formed, a step of forming an embedded epitaxial layer in the fin body 201 on both sides of the polysilicon dummy gate 204 and a step of performing source-drain injection to form a source region and a drain region are also included, and the source region and the drain region are located in the embedded epitaxial layer.
Step two, as shown in fig. 4C, a first polysilicon etching is performed to remove the polysilicon dummy gate 204 of the core region 301 and to reserve the polysilicon dummy gate 204 of the input/output region 302.
And step three, as shown in fig. 4D, performing threshold voltage adjustment implantation, wherein a region of the threshold voltage adjustment implantation is defined by a first photoresist pattern formed by a photolithography process.
In the core region 301, the threshold voltage adjustment implant penetrates through the first gate dielectric layer 203 on top of the top portion of the fin 201 into the top portion of the fin 201 and enables adjustment of the doping of the channel region of the core FinFET and thus adjustment of the threshold voltage of the core FinFET.
And removing the first photoresist pattern, and in the input/output region 302, protecting the first gate dielectric layer 203 in the process of removing the photoresist pattern by using the characteristic that the first gate dielectric layer 203 is buried at the bottom of the polysilicon dummy gate 204.
The threshold voltage adjustment implant for adjusting the threshold voltage of the core FinFET employs a band angle ion implant.
The core FinFET comprises an N-type core FinFET and a P-type core FinFET, the threshold voltage adjustment injection for adjusting the threshold voltage of the N-type core FinFET and the threshold voltage adjustment injection for adjusting the threshold voltage of the P-type core FinFET are performed separately.
In the i/o region 302, the threshold voltage adjust implant of the i/o FinFET is performed as needed, which passes through the polysilicon dummy gate 204 and the first gate dielectric layer 203 at the top of the top portion of the fin 201 and into the top portion of the fin 201.
In fig. 4D, the threshold voltage adjusting implantation region is marked with a mark 205, and the threshold voltage adjusting implantation of different regions needs to be defined by using the first photoresist patterns corresponding to the separate photolithography processes.
And step four, annealing and activating the impurities injected by adjusting the threshold voltage.
And step five, performing a metal gate replacement process.
The fifth step comprises the following sub-steps:
and 51, performing second polysilicon etching to remove the polysilicon dummy gate 204 of the input/output area 302.
And 52, removing the first gate dielectric layer 203 in the core region 301, and reserving the first gate dielectric layer 203 in the input and output region 302.
And 53, forming a gate dielectric layer of the core FinFET, and forming metal gates of the core FinFET and the input-output FinFET.
The gate dielectric layer of the core FinFET in step 53 includes a high dielectric constant layer. Preferably, step four is omitted and the activation of the threshold voltage adjustment implant impurity is accomplished directly using the thermal process of forming the high dielectric constant layer of the gate dielectric layer of the core FinFET in step 53.
The material of the high dielectric constant layer includes hafnium oxide.
The embodiment of the invention makes special settings for the sequence of threshold voltage adjustment injection in the whole process flow and the removal process of the polysilicon dummy gate 204, wherein the polysilicon dummy gate 204 of the core area 301 is removed and the polysilicon dummy gate 204 of the input-output area 302 is reserved by first polysilicon etching, the threshold voltage adjustment injection is placed after the first polysilicon etching, and the first gate dielectric layer 203 of the input-output area 302 can be prevented from being damaged when the photoresist defining the threshold voltage adjustment injection area is removed by utilizing the reserved characteristics of the polysilicon dummy gate 204 of the input-output area 302, so that the device performance of the input-output FinFET cannot be influenced.
Meanwhile, the threshold voltage adjustment injection of the core region 301 is similar to the threshold voltage adjustment injection of the second conventional method, so that the sensitivity of the threshold voltage adjustment injection of the core region 301 is good, the threshold voltage adjustment is facilitated, and the device performance of the core FinFET can be improved. While the sensitivity of the input-output FinFET to threshold voltage adjustment injection is not as high as that of the core FinFET, the embodiment of the invention can still well adjust the threshold voltage of the input-output FinFET.
Compared with the prior first method which needs higher injection energy when the injection is directly performed from the top of the fin body 201 and damages the fin body 201, the threshold voltage adjustment injection of the core region 301 in the embodiment of the invention can realize the injection with an inclination angle and can be realized by adopting the injection without damaging the fin body 201; the threshold voltage adjustment implant of the input/output region 302 passes through the polysilicon dummy gate 204, so that the fin 201 is not damaged, and thus, the embodiment of the invention can also avoid the damage of the threshold voltage adjustment implant to the fin 201.
As can be seen from the above, the embodiment of the invention can avoid damage to the fin body 201 and the gate dielectric layer of the input/output FinFET after threshold voltage adjustment injection, and can improve the sensitivity of the threshold voltage of the core FinFET, so that the performance of both the core FinFET and the input/output FinFET can be improved.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (15)

1. A threshold voltage adjustment method of a FinFET is characterized by comprising the following steps:
step one, providing a semiconductor substrate which is subjected to a chemical mechanical polishing process of a zeroth interlayer film, wherein a FinFET comprises a core FinFET and an input-output FinFET, the semiconductor substrate comprises a core area and an input-output area, the core area is a forming area of the core FinFET, and the input-output area is a forming area of the input-output FinFET;
the semiconductor substrate is provided with fin bodies, shallow trench isolation medium layers, first gate medium layers and polycrystalline silicon pseudo gates, the shallow trench isolation medium layers are located between the fin bodies, the top portions of the fin bodies are located on the top surfaces of the shallow trench isolation medium layers, well regions are formed in the top portions of the fin bodies, the first gate medium layers cover the side surfaces and the top surfaces of the top portions of the fin bodies, the polycrystalline silicon pseudo gates are formed on the first gate medium layers in a covering mode, the well regions covered by the polycrystalline silicon pseudo gates serve as channel regions of the FinFET, the zero layer interlayer films completely fill the regions between the polycrystalline silicon pseudo gates, and the top surfaces of the zero layer interlayer films are flush with the top surfaces of the polycrystalline silicon pseudo gates;
in the input-output area, the first gate dielectric layer is directly used as the gate dielectric layer of the input-output FinFET, and in the step one, the first gate dielectric layer is directly grown according to the thickness requirement of the gate dielectric layer of the input-output FinFET;
step two, carrying out first polysilicon etching to remove the polysilicon dummy gate of the core area and reserve the polysilicon dummy gate of the input and output area;
step three, threshold voltage adjustment injection is carried out, and a region of the threshold voltage adjustment injection is defined by a first photoresist pattern formed by a photoetching process;
in the core region, the threshold voltage adjustment implant penetrates through the first gate dielectric layer on the top of the top portion of the fin body and then enters the top portion of the fin body and achieves adjustment of doping of the channel region of the core FinFET and thus adjustment of the threshold voltage of the core FinFET;
removing the first photoresist pattern, and in the input and output region, utilizing the characteristic that the first gate dielectric layer is buried at the bottom of the polycrystalline silicon pseudo gate to ensure that the first gate dielectric layer is protected in the process of removing the photoresist pattern;
fourthly, annealing and activating the impurities injected by adjusting the threshold voltage;
and step five, performing a metal gate replacement process.
2. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: the semiconductor substrate includes a silicon substrate.
3. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: the fifth step comprises the following sub-steps:
step 51, performing second polysilicon etching to remove the polysilicon dummy gate of the input/output area;
step 52, removing the first gate dielectric layer in the core region, and reserving the first gate dielectric layer in the input and output region;
and 53, forming a gate dielectric layer of the core FinFET, and forming metal gates of the core FinFET and the input-output FinFET.
4. The method of threshold voltage adjustment of a FinFET of claim 3, wherein: the gate dielectric layer of the core FinFET in step 53 includes a high dielectric constant layer.
5. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: the first gate dielectric layer is made of an oxide layer.
6. The method of threshold voltage adjustment of a FinFET of claim 5, wherein: the first gate dielectric layer is formed by adopting an in-situ water vapor growth process.
7. The method of threshold voltage adjustment of a FinFET of claim 4, wherein: omitting step four and directly utilizing the thermal process of forming the high dielectric constant layer of the gate dielectric layer of the core FinFET in step 53 to effect activation of the threshold voltage adjustment implant impurity.
8. The method of threshold voltage adjustment of a FinFET of claim 4, wherein: the material of the high dielectric constant layer includes hafnium oxide.
9. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in the first step, the fin body is formed by performing patterned etching on the semiconductor substrate.
10. The method of threshold voltage adjustment of a FinFET of claim 9, wherein: the shallow trench isolation medium layer is formed by adopting a deposition and etch-back process, and can completely fill the interval area between the fin bodies after the deposition of the shallow trench isolation medium layer is finished; and after the back etching process of the shallow trench isolation medium layer is completed, the shallow trench isolation medium layer is only positioned in the bottom area of the interval area between the fin bodies and exposes the top parts of the fin bodies.
11. The method of threshold voltage adjustment of a FinFET of claim 10, wherein: and after the shallow trench isolation medium layer is deposited, the shallow trench isolation medium layer is formed by completely filling the spacing region between the fin bodies and performing an ion injection and push well process under the condition that the top surface of the shallow trench isolation medium layer is the same as the top surface of the fin body, and the back etching process of the shallow trench isolation medium layer is performed after the well region is formed.
12. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in the first step, after the polycrystalline silicon dummy gate is formed, a step of forming an embedded epitaxial layer in the fin body on two sides of the polycrystalline silicon dummy gate and a step of performing source and drain injection to form a source region and a drain region are further included, and the source region and the drain region are located in the embedded epitaxial layer.
13. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in step three, the threshold voltage adjustment implant used to adjust the threshold voltage of the core FinFET employs an angled ion implant.
14. The method of threshold voltage adjustment of a FinFET of claim 13, wherein: the core FinFET comprises an N-type core FinFET and a P-type core FinFET, the threshold voltage adjustment injection for adjusting the threshold voltage of the N-type core FinFET and the threshold voltage adjustment injection for adjusting the threshold voltage of the P-type core FinFET are performed separately.
15. The method of threshold voltage adjustment of a FinFET of claim 1, wherein: in the third step, in the input/output region, the threshold voltage adjustment injection of the input/output FinFET is adjusted according to needs, and the threshold voltage adjustment injection of the input/output FinFET is adjusted to penetrate through the polysilicon dummy gate and the first gate dielectric layer on the top of the top portion of the fin body and then enter the top portion of the fin body.
CN202111097919.3A 2021-09-18 2021-09-18 Threshold voltage adjusting method of FinFET Pending CN113948395A (en)

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US4845047A (en) * 1987-06-25 1989-07-04 Texas Instruments Incorporated Threshold adjustment method for an IGFET
CN104795331A (en) * 2014-01-21 2015-07-22 中芯国际集成电路制造(上海)有限公司 Transistor formation method
CN106684042A (en) * 2015-11-05 2017-05-17 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor structure
CN106952810A (en) * 2016-01-06 2017-07-14 中芯国际集成电路制造(上海)有限公司 The manufacture method of semiconductor structure
US9741717B1 (en) * 2016-10-10 2017-08-22 International Business Machines Corporation FinFETs with controllable and adjustable channel doping

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4845047A (en) * 1987-06-25 1989-07-04 Texas Instruments Incorporated Threshold adjustment method for an IGFET
CN104795331A (en) * 2014-01-21 2015-07-22 中芯国际集成电路制造(上海)有限公司 Transistor formation method
CN106684042A (en) * 2015-11-05 2017-05-17 中芯国际集成电路制造(上海)有限公司 Manufacturing method of semiconductor structure
CN106952810A (en) * 2016-01-06 2017-07-14 中芯国际集成电路制造(上海)有限公司 The manufacture method of semiconductor structure
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