CN107045982B - Method for forming semiconductor structure - Google Patents
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- CN107045982B CN107045982B CN201610082771.9A CN201610082771A CN107045982B CN 107045982 B CN107045982 B CN 107045982B CN 201610082771 A CN201610082771 A CN 201610082771A CN 107045982 B CN107045982 B CN 107045982B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
A method of forming a semiconductor structure, comprising: forming a substrate, wherein a fin part is formed on the surface of the substrate; forming a pseudo gate structure crossing the fin part; forming a source region or a drain region in the fin parts at two sides of the pseudo gate structure; forming a dielectric layer on the fin part and the source region or the drain region; removing the pseudo grid electrode of the pseudo grid structure in the core region to expose the oxide layer; performing a first punch-through prevention implantation; removing the oxide layer of the pseudo gate structure in the core region to expose the surface of the fin part in the core region; and forming a metal gate structure on the fin portion. According to the invention, after the pseudo gate structure and the source region or the drain region are formed, the pseudo gate of the pseudo gate structure in the core region is removed, the substrate in the core region is subjected to anti-punch-through injection, and then the oxide layer of the pseudo gate structure is removed to remove the damage of the anti-punch-through injection to the oxide layer, so that the influence on the channel performance caused by the upward diffusion of ions in the anti-punch-through layer in the process of forming the pseudo gate structure and the source region or the drain region can be reduced, and the performance of the formed semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, the gate size of the planar transistor is getting smaller and smaller as the element density and the integration degree of the semiconductor device are improved, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.
In order to overcome the short channel effect of the transistor and suppress the leakage current, a Fin field effect transistor (Fin FET) is proposed in the prior art, and the Fin FET is a common multi-gate device. The structure of the fin field effect transistor comprises: the semiconductor device comprises a fin part and a dielectric layer, wherein the fin part and the dielectric layer are positioned on the surface of a semiconductor substrate, the dielectric layer covers a part of the side wall of the fin part, and the surface of the dielectric layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the dielectric layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as the size of the semiconductor device is continuously reduced, the manufacturing process of the fin field effect transistor is challenged, and it is difficult to ensure the performance of the fin field effect transistor.
Disclosure of Invention
The invention solves the problem of providing a method for forming a semiconductor structure so as to improve the performance of a formed semiconductor device.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
forming a substrate, wherein a fin part is formed on the surface of the substrate, the substrate comprises a core region for forming a core device, and the fin part located in the core region is a fin part in the core region;
forming a pseudo gate structure crossing the fin part, wherein the pseudo gate structure covers part of the side wall and the top surface of the fin part, the pseudo gate structure comprises an oxide layer and a pseudo gate which are sequentially positioned on the fin part, and the pseudo gate structure positioned in the core region is a core region pseudo gate structure;
forming a source region or a drain region in the fin parts at two sides of the pseudo gate structure;
forming a dielectric layer on the fin part and the source region or the drain region, wherein the dielectric layer exposes out of the pseudo gate structure;
removing the dummy grid of the dummy grid structure in the core region and exposing the oxide layer on the surface of the fin part in the core region;
performing first punch-through prevention injection, and forming a first punch-through prevention layer below a source region or a drain region in the fin part of the core region;
removing the oxide layer of the pseudo gate structure in the core region to expose the surface of the fin part in the core region;
and forming a metal gate structure on the fin portion.
Optionally, in the step of forming the substrate, the substrate further includes a peripheral region for forming an input/output device, and the fin portion located in the peripheral region is a peripheral region fin portion; the forming method further includes: after the step of forming the substrate and before the step of forming the pseudo gate structure on the surface of the substrate, performing second punch-through prevention injection to form a second punch-through prevention layer in the fin part of the peripheral area; and in the step of forming a source region or a drain region in the fin parts at two sides of the pseudo gate structure, forming the source region or the drain region in the fin part of the peripheral region above the second anti-punch-through layer.
Optionally, the step of performing a second punch-through prevention implantation to form a second punch-through prevention layer in the fin portion of the peripheral region includes: and performing a second punch-through prevention implantation by adopting a lateral ion implantation mode.
Optionally, the step of performing a second punch-through prevention implantation to form a second punch-through prevention layer in the fin portion of the peripheral region includes: the formed input-output device is an NMOS device, the second punch-through preventing implantation ions are P-type ions, the energy of the second punch-through preventing implantation is 10KeV to 35KeV, and the implantation dosage is 1E13atoms/cm2 to 2E14atoms/cm 2; alternatively, the formed input-output device is a PMOS device, the second punch-through preventing implant ions are N-type ions, the energy of the second punch-through preventing implant is 50KeV to 120KeV, and the implant dose is in the range of 5E12atoms/cm2 to 1E14atoms/cm 2.
Optionally, in the step of forming the dummy gate structure crossing the fin portion, the dummy gate structure located in the peripheral region is a peripheral region dummy gate structure; the forming method further includes: after the step of removing the oxide layer of the pseudo gate structure in the core region and before the step of forming the metal gate structure, removing the pseudo gate of the pseudo gate structure in the peripheral region and exposing the oxide layer on the surface of the fin part in the peripheral region; the step of forming a metal gate structure on the fin includes: forming a metal grid structure on the surface of the fin part in the core region; and forming the metal gate structure on the surface of the fin oxidation layer in the peripheral area.
Optionally, the metal gate structure includes: the high-K dielectric layer and the metal electrode are positioned on the surface of the high-K dielectric layer; the step of forming a metal gate structure on the surface of the fin portion in the core region comprises: sequentially forming a high-K dielectric layer and a metal grid on the surface of the fin part in the core region; the step of forming the metal gate structure on the surface of the peripheral region fin oxide layer comprises: and forming a high-K dielectric layer and a metal grid on the surface of the fin oxide layer in the peripheral area.
Optionally, in the step of forming the dummy gate structure crossing the fin portion, the dummy gate is made of polysilicon.
Optionally, the step of removing the dummy gate of the dummy gate structure in the core region includes: forming a first mask covering the peripheral region; and removing the dummy gate of the dummy gate structure in the core region by using the first mask as a mask and adopting a wet etching mode.
Optionally, in the step of forming a first mask covering the peripheral region, the material of the first mask includes: and (7) photoresist.
Optionally, in the step of forming the dummy gate structure crossing the fin portion, the dummy gate structure further includes a second mask located on a surface of the dummy gate; the step of removing the dummy gate of the dummy gate structure in the core region by adopting a wet etching method comprises the following steps: and sequentially removing the second mask and the pseudo grid electrode by using the first mask as a mask and adopting a wet etching mode to expose the oxide layer on the surface of the fin part in the core region.
Optionally, the material of the second mask comprises silicon nitride; and in the step of sequentially removing the second mask and the pseudo gate by adopting a wet etching mode, removing the second mask by adopting phosphoric acid wet etching, and removing the pseudo gate by adopting tetramethyl ammonium hydroxide wet etching.
Optionally, a first punch-through prevention implantation is performed, and in the step of forming a first punch-through prevention layer under the source region or the drain region in the fin of the core region, the formed core device is an NMOS device, the first punch-through prevention implantation ions are P-type ions, the energy of the first punch-through prevention implantation is 12KeV to 25KeV, and the implantation dose is 1E13atoms/cm2 to 2E14atoms/cm 2; the formed core device is a PMOS device, the first punch-through preventing implant ions are N-type ions, the energy of the first punch-through preventing implant is 70KeV to 140KeV, and the implantation dosage is in the range of 4E12atoms/cm2 to 1E14atoms/cm 2.
Optionally, the step of performing the first punch-through prevention implantation to form the first punch-through prevention layer includes: performing an annealing treatment, wherein the annealing treatment is a spike annealing treatment with the temperature ranging from 950 ℃ to 1050 ℃.
Optionally, in the step of forming the dummy gate structure crossing the fin portion, the oxide layer covers the surface of the fin portion, and the oxide layer is formed in an in-situ water vapor generation manner.
Optionally, the step of forming a substrate, where a fin portion is formed on a surface of the substrate, includes: providing a substrate; forming a semiconductor layer on a substrate; forming a third mask on the semiconductor layer; etching the semiconductor layer by taking the third mask as a mask to form a fin part on the surface of the substrate; the forming method further comprises, after the step of forming the substrate and before the step of forming the oxide layer covering the surface of the fin portion: and removing the third mask.
Optionally, after the step of removing the oxide layer of the core region dummy gate structure and before the step of forming the metal gate structure on the fin portion, the forming method further includes: and repairing the surface of the fin part in the core area.
Optionally, the step of performing a repair process on the surface of the fin in the core region includes: forming the repairing layer on the surface of the fin part in the core region in a thermal oxidation mode; and removing the repairing layer.
Optionally, the step of forming a source region or a drain region in the fin portions on both sides of the dummy gate structure includes: etching the fin parts on two sides of the pseudo gate structure by taking the pseudo gate structure as a mask, and forming an opening in the fin parts; and filling a semiconductor material into the opening to form a stress layer, and doping ions in the stress layer to form a source region or a drain region.
Optionally, the step of filling the semiconductor material into the opening includes: and filling the semiconductor material into the opening in an epitaxial growth mode.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the invention, after the pseudo gate structure and the source region or the drain region are formed, the pseudo gate of the pseudo gate structure in the core region is removed, the anti-punch-through injection is carried out on the substrate in the core region, and then the oxide layer of the pseudo gate structure is removed to remove the damage of the anti-punch-through injection to the oxide layer, so that the influence on the channel performance caused by the upward diffusion of ions in the anti-punch-through layer in the process of forming the pseudo gate structure and the source region or the drain region can be reduced, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure according to the prior art;
fig. 3 to 12 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As can be seen from the background art, as the size of the semiconductor device is continuously reduced, the manufacturing process of the fin field effect transistor is challenged, and it is difficult to ensure the performance of the fin field effect transistor.
In the forming process of the semiconductor structure in the prior art, the reason of the performance problem is analyzed.
Research shows that as the size of a fin portion used for forming a fin field effect transistor is continuously reduced, the bottom of a source region and the bottom of a drain region formed in the fin portion are prone to have a punch-through (punch-through) phenomenon, that is, the bottom of the source region and the bottom of the drain region are punched through, and leakage current is generated at the bottoms of the source region and the drain region. In order to overcome the bottom punch-through phenomenon, one method is to perform a punch-through prevention implantation in the fin portion, and implant inversion ions in the region between the bottoms of the source region and the drain region to isolate the bottoms of the source region and the drain region.
Referring to fig. 1 to 2, schematic structural diagrams of steps of a semiconductor structure forming method in the prior art are shown.
Referring to fig. 1, a substrate 10 is provided, fins 11 and isolation structures 12 located between the fins 11 are formed on a surface of the substrate 10, and the isolation structures 12 cover a portion of sidewall surfaces of the fins 11.
Referring to fig. 2, a punch-through prevention implantation is performed on the isolation structure 12 to form a punch-through prevention layer 13 in the fin 11, and an annealing process is performed to activate the punch-through prevention layer 13.
After the anti-punch-through layer 13 is formed, a gate structure crossing the fin 11 and a source region or a drain region located in the fin on both sides of the gate structure are formed. The semiconductor process after the formation of the punch-through prevention layer 13 causes the diffusion of ions in the punch-through prevention layer 13. Since the punch-through preventing ions are inversion ions, the upward diffusion of the inversion ions causes the performance of the channel region above the punch-through preventing layer 13 to change, thereby affecting the performance of the formed semiconductor structure.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
forming a substrate, wherein a fin part is formed on the surface of the substrate, the substrate comprises a core region for forming a core device, and the fin part located in the core region is a fin part in the core region; forming a pseudo gate structure crossing the fin part, wherein the pseudo gate structure covers part of the side wall and the top surface of the fin part, the pseudo gate structure comprises an oxide layer and a pseudo gate which are sequentially positioned on the fin part, and the pseudo gate structure positioned in the core region is a core region pseudo gate structure; forming a source region or a drain region in the fin parts at two sides of the pseudo gate structure; forming a dielectric layer on the fin part and the source region or the drain region, wherein the dielectric layer exposes out of the dummy gate; removing the dummy grid of the dummy grid structure in the core region and exposing the oxide layer on the surface of the fin part in the core region; performing first punch-through prevention injection, and forming a first punch-through prevention layer below a source region or a drain region in the fin part of the core region; removing the oxide layer of the pseudo gate structure in the core region to expose the surface of the fin part in the core region; and forming a metal gate structure on the fin portion.
According to the invention, after the pseudo gate structure and the source region or the drain region are formed, the pseudo gate of the pseudo gate structure in the core region is removed, the anti-punch-through injection is carried out on the substrate in the core region, and then the oxide layer of the pseudo gate structure is removed to remove the damage of the anti-punch-through injection to the oxide layer, so that the influence on the channel performance caused by the upward diffusion of ions in the anti-punch-through layer in the process of forming the pseudo gate structure and the source region or the drain region can be reduced, and the performance of the formed semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Referring to fig. 3 to fig. 12, schematic structural diagrams of steps of an embodiment of a method for forming a semiconductor structure provided by the present invention are shown.
Referring to fig. 3, a substrate 100 is formed, a fin 110 is formed on a surface of the substrate 100, the substrate 100 includes a core region 100c for forming a core device, and the fin 110 located in the core region 100c is a fin in the core region.
The substrate 100 further includes a peripheral region 100i for forming an input/output device, and the fin portion 110 located in the peripheral region 100i is a peripheral region fin portion. Because the working voltage is different, the thickness of the gate dielectric layer of the core device is different from that of the gate dielectric layer of the input/output device: the thickness of the gate dielectric layer of the input and output device is larger than that of the gate dielectric layer of the core device so as to obtain higher working voltage. The gate dielectric layer comprises a gate oxide layer and a high-K dielectric layer positioned on the surface of the gate oxide layer. The thickness of the gate oxide layer of the input/output device is larger than that of the gate oxide layer of the core device, so that the thickness of the gate dielectric layers of the input/output device and the core device is different.
Specifically, the step of forming the substrate 100 includes: providing a substrate 100; forming a semiconductor layer on the substrate 100; forming a third mask 130 on the semiconductor layer; and etching the semiconductor layer by using the third mask 130 as a mask to form the fin portion 110 on the surface of the substrate 100.
The substrate 100 is used to provide an operation platform for a subsequent semiconductor process. The material of the substrate 100 is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the substrate 100 may also be selected from silicon, germanium, gallium arsenide, or silicon germanium compounds; the substrate 100 may also be other semiconductor materials. The invention is not limited in this regard. In this embodiment, the material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the substrate may also be selected to have an epitaxial layer or a silicon-on-epitaxial layer structure.
The semiconductor layer is used for etching to form the fin 110. Specifically, the semiconductor layer may be formed on the surface of the substrate 100 by using a selective epitaxial deposition process. The material of the semiconductor layer is silicon, germanium, silicon carbide, silicon germanium or the like.
It should be noted that the selection of the substrate 100 and the semiconductor layer is not limited, and a substrate suitable for process requirements or easy integration, and a material suitable for forming the fin portion 110 can be selected. And the thickness of the semiconductor layer can be controlled by the epitaxial process, so that the height of the formed fin portion 110 can be accurately controlled.
It should be further noted that, in other embodiments of the present invention, the base 100 and the fin portion 110 located on the surface of the base 100 may also be formed by directly etching a semiconductor substrate, and the specific forming manner of the base 100 and the fin portion 110 is not limited in the present invention.
A patterned third mask 130 is used to define the location and dimensions of the fin 110. The step of forming the patterned third mask 130 includes: forming a third mask material layer on the surface of the semiconductor substrate; forming a first patterning layer on the surface of the third mask material layer; and etching the third mask material layer by taking the first patterning layer as a mask until the surface of the semiconductor substrate is exposed to form a patterned third mask 130. Specifically, the material of the patterned third mask 130 is silicon nitride.
It should be noted that, in this embodiment, before the step of forming the patterned third mask 130, the forming method further includes forming a buffer layer (not shown in the figure) on the surface of the semiconductor substrate to reduce lattice mismatch between the third mask 130 and the semiconductor substrate. Specifically, in this embodiment, the buffer layer is made of an oxide.
The first patterned layer may be a patterned photoresist layer formed using a coating process and a photolithography process. In addition, in order to reduce the feature size of the fins 110 and the distance between adjacent fins 110, the first patterning layer may be formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned triple patterning (Self-aligned triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
It should be noted that, in the process of forming the fin portion 110, there may be damage or micro unevenness on the surface of the semiconductor substrate that is etched, and in order to repair the damage or unevenness on the surface of the semiconductor substrate to improve the performance of the formed semiconductor structure, in this embodiment, after the step of forming the fin portion 110, the forming method further includes forming a liner oxide layer (L inner oxide) (not shown) on the surfaces of the substrate 100 and the fin portion 110.
It should be noted that in this embodiment, an isolation structure 120 is further disposed between adjacent fins 110, so as to achieve electrical isolation between adjacent fins 110 and between semiconductor devices in other regions of the substrate 100. The steps of the isolation structure 120 include: forming an isolation material layer, wherein the isolation material layer is filled between adjacent fins 110, and the top surface of the isolation material layer is higher than the top surface of each fin 110; a portion of the thickness of the top portion of the isolation material layer is removed to expose a portion of the sidewalls of the fin 110 to form an isolation structure 120.
As the density of semiconductor devices increases, the size between adjacent fins 110 decreases correspondingly, so that the aspect ratio of the trench between adjacent fins 110 increases, and in order to enable the isolation material layer to fill the trench between adjacent fins 110 sufficiently, the step of forming the isolation material layer includes: the isolation material layer is formed using a Fluid Chemical Vapor Deposition (FCVD) process.
Referring to fig. 4 in combination, a dummy gate structure 150 crossing the fin 110 is formed, the dummy gate structure 150 covers a part of the sidewall and the top surface of the fin 110, the dummy gate structure 150 includes an oxide layer 151 and a dummy gate 152 sequentially located on the fin 110, and the dummy gate structure 150 located in the core region 100c is a core region dummy gate structure.
In this embodiment, the substrate 100 further includes a peripheral region 100i for forming an input/output device. Therefore, after the step of forming the substrate 100 and before the step of forming the dummy gate structure 150, the forming method further includes: a second punch-through prevention implant is performed to form a second punch-through prevention layer 140i in the fin portion of the peripheral region.
The anti-punch-through ions are P-type ions or N-type ions. Specifically, the type of the transistor formed by the second punch-through preventing implantation is opposite to that of the transistor formed by the first punch-through preventing implantation: when the formed transistor is an NMOS device, the injected punch-through preventing ions are P-type ions; when the transistor is a PMOS device, the implanted punch-through preventing ions are N-type ions. The punch-through preventing ions are of a type opposite to that of the doped ions in the source region or the drain region formed in the fin 110, so that the doped ions in the source region or the drain region can be prevented from being diffused, and the bottom punch-through phenomenon caused by the fact that the distance between the bottoms of the source region or the drain region is too close can be prevented.
The second punchthrough prevention implant comprises performing a second punchthrough prevention implant by lateral ion implantation (L iterative StraggleImmplant).
Specifically, in the step of forming the second punch-through prevention layer 140i, when the formed input/output device is an NMOS device, the second punch-through prevention implant ions are P-type ions, the energy of the second punch-through prevention implant is 10KeV to 35KeV, and the implant dose is 1E13atoms/cm2To 2E14atoms/cm2(ii) a When the formed device is a PMOS device, the second punch-through preventing implantation ions are N-type ions, the energy of the second punch-through preventing implantation is 50KeV to 120KeV, and the implantation dosage is 5E12atoms/cm2To 1E14atoms/cm2Within the range.
In this embodiment, the transistors formed in the peripheral region 100i are PMOS devices, and thus the anti-punch-through ions implanted by the second anti-punch-through implantation are N-type ions. However, the method of implanting N-type ions is only an example, and in other embodiments of the present invention, when the transistor is an NMOS device, the implanted punch-through preventing ions may also be P-type ions.
It should be noted that, because the thickness of the dielectric layer of the input/output device using the high-K metal gate is greater than the thickness of the dielectric layer of the core device using the high-K metal gate, the subsequently formed dummy gate structure oxide layer located in the peripheral region 100i needs to be retained in the formation process, and is used as the gate oxide layer of the subsequently formed high-K metal gate to increase the gate dielectric layer of the input/output device. Therefore, in order to avoid the gate oxide layer of the input/output device from being affected by the punch-through implantation process, a second punch-through implantation is performed before the step of forming the dummy gate structure, and a second punch-through prevention layer 140i is formed on the fin portion in the peripheral region.
With continuing reference to fig. 4 and with combined reference to fig. 5, fig. 5 is a view along direction a of fig. 4, and a dummy gate structure 150 is formed on the surface of the substrate 100.
It should be noted that, in the step of forming the substrate 100, the third mask 130 is further formed on the top surface of the fin 110 (as shown in fig. 3), so that after the step of forming the substrate 100 and before the step of forming the dummy gate structure 150, the forming method further includes removing the third mask 130 to expose the top surface of the fin 110.
Specifically, in this embodiment, the third mask 130 may be removed after the second punch-through implantation preventing step is performed. The third mask 130 may serve to protect the top of the fin in the peripheral region during the second punchthrough-preventing implant. However, the method of removing the third mask 130 after the second punch-through implantation preventing step is only an example, and the sequence of the second punch-through implantation preventing step and the third mask 130 removing step is not limited in the present invention.
The step of forming the dummy gate structure 150 includes: forming an oxide layer 151, wherein the oxide layer 151 covers the surface of the fin portion 110; a dummy gate 152 is formed on the surface of the oxide layer 151, and the dummy gate 152 crosses over the fin 110 and covers the top and the sidewall of the fin 110.
Specifically, the step of forming the oxide layer 151 covering the surface of the fin 110 includes: the oxide layer 151 is formed by In-Situ Steam Generation (ISSG). The oxide layer 151 formed in an in-situ water vapor generation manner has high density, uniform thickness and good step coverage capability, and can tightly cover the side walls and the top surface of the fin portion 110.
Before the step of forming the oxide layer 151, in this embodiment, the forming method further includes: the surface of the fin 110 is repaired to repair the damage on the surface of the fin 110 in the previous semiconductor process. Specifically, the repair process includes: a sacrificial layer (not shown) is formed covering the surface of the fin 110 and removed.
The step of forming the dummy gate 152 includes: forming a pseudo gate material layer on the surface of the oxide layer 151; forming a patterned second mask 153 on the surface of the dummy gate material layer; and etching the dummy gate material layer by using the patterned second mask 153 as a mask to form a dummy gate 152, wherein the dummy gate 152 crosses the fin 110 and covers part of the sidewall and the top surface of the fin 110. Specifically, the material of the dummy gate 152 is polysilicon.
The second mask 153 is used to define the position and size of the dummy gate 152, and also can protect the dummy gate structure 150 in the subsequent semiconductor process, thereby improving the yield of the semiconductor structure. In this embodiment, the second mask 153 is made of silicon nitride.
It should be noted that the dummy gate structure 150 further includes a dummy gate sidewall (not shown). The pseudo gate side wall is made of one or a combination of silicon oxide, silicon nitride and silicon oxynitride.
Referring to fig. 6, a source region or a drain region 160 is formed in the fin 110 at both sides of the dummy gate structure 150.
Etching the fin parts 110 on two sides of the dummy gate structure 150 by using the dummy gate structure 150 as a mask, and forming openings in the fin parts 110; and filling the opening with a semiconductor material to form a stress layer, and doping ions in the stress layer to form a source region or a drain region 160.
In this embodiment, the substrate 100 includes a core region 100c for forming a core device and a peripheral region 100i for forming an input/output device, and a second penetration preventing layer 140i is formed in the peripheral region 100 i. Therefore, in the step of forming the source region or the drain region 160 in the fin 110 on both sides of the dummy gate structure 150, the source region or the drain region 160 is formed in the fin in the peripheral region above the second penetration preventing layer 140 i.
In this embodiment, the transistors forming the core device and the input/output device are PMOS devices, so the stress layer is an ∑ -shaped stress layer, and the material filling the opening to form the stress layer is a sige material, the ∑ -shaped stress layer formed by the sige material has a protruding tip facing the channel in the channel region, and can introduce a greater stress to the channel region, so that the channel obtains a faster carrier mobility.
Specifically, an epitaxial growth process is adopted to fill the opening with a semiconductor material so as to form a stress layer. In addition, in-situ doping is performed during the epitaxial growth of the semiconductor material to form the source or drain region 160. In this embodiment, the transistor formed is a PMOS device, and therefore P-type ions (e.g., boron ions) are doped in the silicon germanium material during the formation of the source and drain regions 160.
With continued reference to fig. 6, a dielectric layer 170 is formed on the fin 110 and the source or drain region 160, and the dielectric layer 170 exposes the dummy gate structure 150.
It should be noted that, in this embodiment, after the step of forming the source region or the drain region 160 and before the step of forming the dielectric layer 170, the forming method further includes forming a Contact Etch Stop layer (not shown in the figure) (Contact Etch Stop L layer, CES L), where the Contact Etch Stop layer covers the substrate 100, the isolation structure 120, the source region or the drain region 160, and the gate structure 150, and is used as an Etch Stop layer in a subsequent process of forming an interconnect structure.
The dielectric layer 170 is used to achieve electrical isolation between different semiconductor structures. The dielectric layer is made of silicon oxide and can be formed by film deposition technologies such as chemical vapor deposition, physical vapor deposition and atomic layer deposition.
The step of forming the dielectric layer 170 includes: forming a dielectric material layer covering the isolation structure 120, the fin 110, the dummy gate structure 150 and the source or drain region 160; and planarizing the dielectric material layer to form a dielectric layer 170, so that the dielectric layer 170 is flush with the top of the dummy gate 152.
Specifically, in the step of planarizing the dielectric material layer, a chemical mechanical polishing method may be used to planarize the dielectric material layer. The chemical mechanical polishing is stopped when the dummy gate structure 150 is exposed.
Referring to fig. 7, the dummy gate 152 of the dummy gate structure in the core region is removed to expose the oxide layer 151 on the surface of the fin in the core region.
In this embodiment, the substrate 100 further includes a peripheral region 100 for forming an input/output device. The step of removing the dummy gate 152 of the core dummy gate structure thus includes: forming a first mask 180 covering the peripheral region 100 i; and removing the dummy gate 152 of the dummy gate structure in the core region by using the first mask 180 as a mask and adopting a wet etching method.
Specifically, the first mask 180 is used to protect the peripheral region 100i during the process of removing the dummy gate structure 150 in the core region 100 c. The material of the first mask 180 includes: the photoresist may be formed by a photoresist coating process.
The dummy gate structure 150 further includes a second mask 153 on the surface of the dummy gate 152, so that the step of removing the dummy gate 152 in the dummy gate structure in the core region 100c by wet etching includes: and sequentially removing the second mask 153 and the dummy gate 152 of the dummy gate structure in the core region 100c by using the first mask 180 as a mask and adopting a wet etching manner, so as to expose the oxide layer 151 on the surface of the fin portion in the core region.
In this embodiment, the material of the first mask 180 includes photoresist, and the material of the second mask 153 includes silicon nitride. Therefore, in the step of sequentially removing the second mask 153 and the dummy gate 152 of the dummy gate structure in the core region 100c by wet etching, and exposing the oxide layer 151 on the surface of the fin portion in the core region, the second mask 153 is removed by wet etching using phosphoric acid, and the dummy gate 152 is removed by wet etching using tetramethylammonium hydroxide (TMAH).
Referring to fig. 8 to 10, wherein fig. 9 is a cross-sectional view taken along line AA of fig. 8 and fig. 10 is a cross-sectional view taken along line BB of fig. 8, a first anti-punch through implant is performed to form a first anti-punch through layer 140c under the source or drain region 160 in the core fin.
Specifically, the first punchthrough implantation preventing step comprises: the formed core device is an NMOS device, the first punch-through preventing implantation ions are P-type ions, the energy of the first punch-through preventing implantation is 12KeV to 25KeV, and the implantation dosage is 1E13atoms/cm2To 2E14atoms/cm2(ii) a The formed core device is a PMOS device, the first punch-through preventing implantation ions are N-type ions, the energy of the first punch-through preventing implantation is 70KeV to 140KeV, and the implantation dosage is 4E12atoms/cm2To 1E14atoms/cm2Within the range.
In this embodiment, the core device is also a PMOS device. Therefore, the punch-through preventing ions implanted by the first punch-through preventing implant are N-type ions. However, the method of implanting N-type ions is also only an example, and in other embodiments of the present invention, when the transistor is an NMOS device, the implanted anti-punch through ions may also be P-type ions.
Since the first punch-through preventing implantation is performed after the process steps of forming the dummy gate structure 150 and forming the source or drain region 160, punch-through preventing ions in the first punch-through preventing layer are not affected by the preceding semiconductor process, and upward diffusion of punch-through preventing ions during the semiconductor process can be reduced, thereby improving the performance of the formed semiconductor structure.
The step of performing the first punch-through prevention implantation to form the first punch-through prevention layer includes: performing an annealing treatment, wherein the annealing treatment is a spike annealing treatment with the temperature ranging from 950 ℃ to 1050 ℃. The annealing process can activate the first and second penetration preventing layers 140c and 140 i.
Referring to fig. 11, the oxide layer 151 of the dummy gate structure in the core region is removed to expose the surface of the fin portion in the core region.
Because the operating voltage of the core device is low, the thickness of the gate dielectric layer of the core device is small, and therefore the oxide layer 151 of the core region pseudo gate structure is removed to reduce the thickness of the gate dielectric layer of the core region device. In addition, during the process of forming the first anti-punch-through layer 140c by performing the first anti-punch-through implantation, the oxide layer 151 may be damaged, and removing the oxide layer 151 may also prevent the performance of the transistor formed from being affected by the corresponding damage.
Referring to fig. 12, a metal gate structure 200 is formed on the fin 110.
It should be noted that, in this embodiment, after the step of removing the oxide layer 151 of the core dummy gate structure and before the step of forming the metal gate structure 200 on the fin 110, the forming method further includes: and repairing the surface of the core region fin part to repair the damage of the core region fin part in the preorder semiconductor process, and also can smooth the surface of the core region fin part and reduce the occurrence of point discharge.
The step of repairing the surface of the fin part in the core area comprises the following steps: forming the repairing layer on the surface of the fin part in the core region in a thermal oxidation mode; and removing the repairing layer. Specifically, the repair layer may be formed on the surface of the fin 110 in the core region 100c by a thermal oxidation method.
In this embodiment, the substrate 100 further includes a peripheral region 100i for forming an input/output device, and in the step of forming the dummy gate structure, the dummy gate structure located in the peripheral region 100i is a peripheral region dummy gate structure. Therefore, after the step of removing the oxide layer 151 of the core region dummy gate structure and before the step of forming the metal gate structure, the forming method further includes: and removing the dummy gate of the dummy gate structure in the peripheral region 100i to expose the oxide layer 151 on the surface of the fin portion in the peripheral region.
Because the operating voltage of the input/output device is higher, the metal gate structure located in the peripheral region is located on the surface of the oxide layer 151, so as to obtain a gate dielectric layer with a larger thickness. The step of forming the metal gate structure 200 on the fin 110 includes: forming a metal grid structure on the surface of the fin part in the core region; and forming the metal gate structure on the surface of the fin oxide layer 151 in the peripheral region.
The metal gate structure 200 includes: a high-K dielectric layer 210 and a metal electrode 220 on the surface of the high-K dielectric layer 210. The step of forming the metal gate structure 200 on the surface of the fin in the core region includes: sequentially forming a high-K dielectric layer 210 and a metal gate 220 on the surface of the fin part in the core region; the step of forming the metal gate structure 200 on the surface of the fin oxide layer 151 in the peripheral region includes: and forming a high-K dielectric layer 210 and a metal gate 220 on the surface of the fin oxide layer 151 in the peripheral region.
The high-K dielectric layer 210 is used to form a gate dielectric layer of the metal gate structure 200. Specifically, the material of the high-K dielectric layer 210 includes hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
In summary, in the invention, after the dummy gate structure and the source region or the drain region are formed, the dummy gate of the dummy gate structure in the core region is removed, the substrate in the core region is subjected to the anti-punch-through implantation, and then the oxide layer of the dummy gate structure is removed to remove the damage of the anti-punch-through implantation to the oxide layer, so that the influence of upward diffusion of ions in the anti-punch-through layer in the process of forming the dummy gate structure and the source region or the drain region on the channel performance can be reduced, and the performance of the formed semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein a fin part is formed on the surface of the substrate, the substrate comprises a core region for forming a core device and a peripheral region for forming an input/output device, the fin part located in the core region is the fin part in the core region, and the fin part located in the peripheral region is the fin part in the peripheral region;
forming a pseudo gate structure crossing the fin part, wherein the pseudo gate structure covers part of the side wall and the top surface of the fin part, the pseudo gate structure comprises an oxide layer and a pseudo gate which are sequentially positioned on the fin part, the pseudo gate structure positioned in the core region is a pseudo gate structure in the core region, and the pseudo gate structure positioned in the peripheral region is a pseudo gate structure in the peripheral region; before the step of forming the pseudo-gate structure on the surface of the substrate, performing second penetration-preventing injection to form a second penetration-preventing layer in the fin part of the peripheral region;
forming a source region or a drain region in the fin part of the core region at two sides of the pseudo gate structure; forming a source region or a drain region in the fin part of the peripheral region on two sides of the pseudo gate structure and above the second anti-punch-through layer;
forming a dielectric layer on the fin part and the source region or the drain region, wherein the dielectric layer exposes out of the pseudo gate structure;
removing the pseudo grid electrodes of the pseudo grid electrode structures in the core area and the peripheral area, and respectively exposing the oxidation layers on the surfaces of the fin parts in the core area and the peripheral area;
performing first punch-through prevention injection, and forming a first punch-through prevention layer below a source region or a drain region in the fin part of the core region;
removing the oxide layer of the pseudo gate structure in the core region to expose the surface of the fin part in the core region;
and forming a metal grid structure on the surface of the fin part in the core region, and forming the metal grid structure on the surface of the fin part oxidation layer in the peripheral region.
2. The method of claim 1, wherein performing a second anti-punch-through implant forms a second anti-punch-through layer in the periphery region fin comprising: and performing a second punch-through prevention implantation by adopting a lateral ion implantation mode.
3. The method of claim 1, wherein performing a second anti-punch-through implant forms a second anti-punch-through layer in the periphery region fin comprising:
the formed input-output device is an NMOS device, the second punch-through preventing implantation ions are P-type ions, the energy of the second punch-through preventing implantation is 10KeV to 35KeV, and the implantation dosage is 1E13atoms/cm2To 2E14atoms/cm2；
Alternatively, the first and second electrodes may be,
the formed input-output device is a PMOS device, the second punch-through preventing implantation ions are N-type ions, the energy of the second punch-through preventing implantation is 50KeV to 120KeV, and the implantation dosage is 5E12atoms/cm2To 1E14atoms/cm2Within the range.
4. The method of forming of claim 1, wherein the metal gate structure comprises: the high-K dielectric layer and the metal electrode are positioned on the surface of the high-K dielectric layer;
the step of forming a metal gate structure on the surface of the fin portion in the core region comprises: sequentially forming a high-K dielectric layer and a metal grid on the surface of the fin part in the core region;
the step of forming the metal gate structure on the surface of the peripheral region fin oxide layer comprises: and forming a high-K dielectric layer and a metal grid on the surface of the fin oxide layer in the peripheral area.
5. The method of claim 1, wherein in the step of forming the dummy gate structure across the fin, a material of the dummy gate is polysilicon.
6. The method of claim 1, wherein removing the dummy gate of the dummy gate structure of the core region comprises:
forming a first mask covering the peripheral region;
and removing the dummy gate of the dummy gate structure in the core region by using the first mask as a mask and adopting a wet etching mode.
7. The method of claim 6, wherein in the step of forming the first mask covering the peripheral region, a material of the first mask comprises: and (7) photoresist.
8. The method of claim 6, wherein in the step of forming the dummy gate structure across the fin, the dummy gate structure further comprises a second mask on a surface of the dummy gate;
the step of removing the dummy gate of the dummy gate structure in the core region by adopting a wet etching method comprises the following steps: and sequentially removing the second mask and the pseudo grid electrode by using the first mask as a mask and adopting a wet etching mode to expose the oxide layer on the surface of the fin part in the core region.
9. The method of forming in accordance with claim 8 wherein the material of the second mask comprises silicon nitride;
and in the step of sequentially removing the second mask and the pseudo gate by adopting a wet etching mode, removing the second mask by adopting phosphoric acid wet etching, and removing the pseudo gate by adopting tetramethyl ammonium hydroxide wet etching.
10. The method of claim 1, wherein performing a first anti-punch-through implant forms a first anti-punch-through layer in the core fin under the source or drain region,
the formed core device is an NMOS device, the first punch-through preventing implantation ions are P-type ions, the energy of the first punch-through preventing implantation is 12KeV to 25KeV, and the implantation dosage is 1E13atoms/cm2To 2E14atoms/cm2；
The formed core device is a PMOS device, the first punch-through preventing implantation ions are N-type ions, the energy of the first punch-through preventing implantation is 70KeV to 140KeV, and the implantation dosage is 4E12atoms/cm2To 1E14atoms/cm2Within the range.
11. The method of claim 1, wherein performing a first anti-punch-through implant to form a first anti-punch-through layer comprises: performing an annealing treatment, wherein the annealing treatment is a spike annealing treatment with the temperature ranging from 950 ℃ to 1050 ℃.
12. The method of claim 1, wherein in the step of forming the dummy gate structure across the fin, the oxide layer covers a surface of the fin, and the oxide layer is formed by in-situ water vapor generation.
13. The method of claim 1, wherein forming a substrate having a fin formed on a surface thereof comprises:
providing a substrate;
forming a semiconductor layer on a substrate;
forming a third mask on the semiconductor layer;
etching the semiconductor layer by taking the third mask as a mask to form a fin part on the surface of the substrate;
the forming method further comprises, after the step of forming the substrate and before the step of forming the oxide layer covering the surface of the fin portion: and removing the third mask.
14. The method of claim 1, wherein after the step of removing the oxide layer of the core dummy gate structure and before the step of forming the metal gate structure on the fin, the method further comprises: and repairing the surface of the fin part in the core area.
15. The method of claim 14, wherein repairing the surface of the core region fin comprises:
forming a repairing layer on the surface of the fin part in the core region in a thermal oxidation mode;
and removing the repairing layer.
16. The method of claim 1, wherein the step of forming a source region or a drain region in the fin portion at two sides of the dummy gate structure comprises:
etching the fin parts on two sides of the pseudo gate structure by taking the pseudo gate structure as a mask, and forming an opening in the fin parts;
and filling a semiconductor material into the opening to form a stress layer, and doping ions in the stress layer to form a source region or a drain region.
17. The method of forming of claim 16, wherein filling the opening with a semiconductor material comprises: and filling the semiconductor material into the opening in an epitaxial growth mode.
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| CN105097528A (en) * | 2014-05-04 | 2015-11-25 | 中国科学院微电子研究所 | FINFET manufacturing method |
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| CN103855004A (en) * | 2012-11-28 | 2014-06-11 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
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| CN104752215A (en) * | 2013-12-30 | 2015-07-01 | 中芯国际集成电路制造(上海)有限公司 | Transistor forming method |
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