CN104752215A - Transistor forming method - Google Patents

Transistor forming method Download PDF

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CN104752215A
CN104752215A CN201310745735.2A CN201310745735A CN104752215A CN 104752215 A CN104752215 A CN 104752215A CN 201310745735 A CN201310745735 A CN 201310745735A CN 104752215 A CN104752215 A CN 104752215A
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layer
dielectric layer
gate
stop
gate dielectric
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CN104752215B (en
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禹国宾
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Semiconductor Manufacturing International Shanghai Corp
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Semiconductor Manufacturing International Shanghai Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A transistor forming method comprises the steps of providing a substrate, wherein the surface of the substrate is of a pseudo gate electrode structure, and the pseudo gate electrode structure comprises a pseudo gate dielectric layer located on the surface of the substrate and a pseudo gate electrode layer located on the surface of the pseudo gate dielectric layer; forming stop layers on the surfaces of the substrate and the pseudo gate electrode structure, wherein doped ions exist in the stop layers; forming dielectric layers on the surfaces of the stop layers, wherein the surfaces of the dielectric layers are flush with the surface of the stop layer located at the top of the pseudo gate electrode layer; removing the stop layer located at the top of the pseudo gate electrode layer, the pseudo gate electrode layer and the pseudo gate dielectric layer, wherein an opening is formed in the dielectric layers; forming a gate dielectric layer and a gate electrode layer in the opening, wherein the gate dielectric layer is located on the side wall and the surface of the bottom of the opening, and the gate electrode layer is located on the surface of the gate dielectric layer and filled in the opening. A formed transistor is stable in performance and good in appearance and shape.

Description

The formation method of transistor
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly relate to a kind of formation method of transistor.
Background technology
Along with the fast development of ic manufacturing technology, impel the semiconductor device in integrated circuit, especially MOS(Metal Oxide Semiconductor, Metal-oxide-semicondutor) size of device constantly reduces, and meets the miniaturization of integrated circuit development and integrated requirement with this.In the process that the scales of MOS transistor device reduces, existing technique receives challenge using silica or silicon oxynitride as the technique of gate dielectric layer.There are some problems using silica or silicon oxynitride as the transistor that gate dielectric layer is formed, comprised the diffusion of leakage current increase and impurity, thus affect the threshold voltage of transistor, and then affect the performance of semiconductor device.
For overcoming the above problems, be suggested with the transistor that high-K gate dielectric layer and metal gate are formed, i.e. high-K metal gate (HKMG, High K Metal Gate) transistor.Described high-K metal gate transistor adopts high K(dielectric constant) material replaces conventional silica or silicon oxynitride gate dielectric material, while reducing transistor size, the generation of leakage current can be reduced, and improves the performance of transistor.
Particularly, please refer to Fig. 1, Fig. 1 is a kind of cross-sectional view of high-K metal gate transistor, comprise: the dielectric layer 105 and the grid structure 110 that are positioned at substrate 100 surface, the top surface of described grid structure 110 flushes with the surface of described dielectric layer 105, described grid structure 110 comprises: the high-K gate dielectric layer 101 being positioned at substrate 100 surface, is positioned at the metal gate 103 on high-K gate dielectric layer 101 surface, is positioned at the side wall 104 on substrate 100 surface of high-K gate dielectric layer 101 and metal gate 103 both sides; Be positioned at source region and the drain region 106 of the substrate 100 of described grid structure both sides.
But, the unstable properties of the high-K metal gate transistor that prior art is formed.
Summary of the invention
The problem that the present invention solves is to provide a kind of formation method of transistor, improves the pattern of the transistor formed, improves the performance of the transistor formed.
For solving the problem, the invention provides a kind of formation method of transistor, comprise: provide substrate, described substrate surface has dummy gate structure, and described dummy gate structure comprises: be positioned at the pseudo-gate dielectric layer of substrate surface and be positioned at the dummy gate layer on pseudo-gate dielectric layer surface; Form stop-layer at described substrate and dummy gate structure surface, in described stop-layer, there is Doped ions; Form dielectric layer on described stop-layer surface, described dielectric layer surface flushes with the stop-layer surface being positioned at dummy gate layer top; Remove the stop-layer at dummy gate layer top, dummy gate layer and pseudo-gate dielectric layer, in described dielectric layer, form opening; In described opening, form gate dielectric layer and grid layer, described gate dielectric layer is positioned at sidewall and the lower surface of opening, and described grid layer is positioned at gate dielectric layer surface and is formed fills full described opening.
Optionally, the material of described stop-layer is silicon nitride, and described Doped ions is carbon ion.
Optionally, the concentration of the Doped ions in described stop-layer is 0.5E15 atom/square centimeter ~ 12E15 atom/square centimeter.
Optionally, the technique of described Doped ions of adulterating in stop-layer is ion implantation technology or in-situ doped technique.
Optionally, when the technique of the described Doped ions that adulterates in stop-layer is ion implantation technology, Implantation Energy is 200 electron-volts ~ 50 kilo electron volts.
Optionally, the technique removing the stop-layer at dummy gate layer top, dummy gate layer and pseudo-gate dielectric layer comprises: the stop-layer at etching dummy gate layer top, till exposing dummy gate layer top surface; After the stop-layer at etching dummy gate layer top, etch described dummy gate layer and pseudo-gate dielectric layer, till exposing substrate surface.
Optionally, the material of described pseudo-gate dielectric layer is silica, and the material of described dummy gate layer is polysilicon.
Optionally, the formation process of described pseudo-gate dielectric layer comprises thermal oxidation technology.
Optionally, the technique removing pseudo-gate dielectric layer is wet-etching technology or dry etch process.
Optionally, also comprise: before forming gate dielectric layer, in sidewall and the lower surface formation cushion oxide layer of described opening, described gate dielectric layer is formed at described cushion oxide layer surface.
Optionally, the material of described pad silicon oxide layer is silica, and the formation process of described cushion oxide layer is chemical vapor deposition method.
Optionally, the formation process of described gate dielectric layer and gate electrode layer comprises: at sidewall and the lower surface deposition gate dielectric film of dielectric layer surface and opening; The gate electrode film of full gate mouth is filled at gate dielectric film surface deposition; Adopt gate electrode film and gate dielectric film described in CMP (Chemical Mechanical Polishing) process planarization, till exposing dielectric layer surface, described gate electrode film forms grid layer, and described gate dielectric film forms gate dielectric layer.
Optionally, the material of described gate dielectric layer is high K dielectric material, and the material of described grid layer is metal.
Optionally, described dummy gate structure also comprises: be positioned at described dummy gate layer and the pseudo-sidewall surfaces of gate dielectric layer both sides and the side wall of substrate surface.
Optionally, the material of described dielectric layer is silica, and the formation process of described dielectric layer comprises: at stop-layer surface deposition deielectric-coating; Adopt deielectric-coating described in CMP (Chemical Mechanical Polishing) process planarization, until expose the stop-layer of dummy gate layer top surface, form dielectric layer.
Optionally, also comprise: before formation stop-layer, in the substrate of described dummy gate structure both sides, form source region and drain region.
Compared with prior art, technical scheme of the present invention has the following advantages:
In the formation method of transistor of the present invention, form stop-layer at described substrate and dummy gate structure surface, have Doped ions in described stop-layer, the dielectric layer surface of follow-up formation flushes with the stop-layer surface being positioned at dummy gate layer top.In order to remove dummy gate layer and pseudo-gate dielectric layer, need the stop-layer first removing dummy gate layer top, the stop-layer top being then positioned at dummy gate structure sidewall surfaces flushes with dummy gate layer surface, and described dielectric layer surface is higher than stop-layer top and dummy gate layer surface.After removal dummy gate layer, remove in the process of pseudo-gate dielectric layer, owing to having Doped ions in described stop-layer, the etch rate of stop-layer is reduced, and the top surface of described stop-layer can not be cut down; Meanwhile, surface corresponding reduction in the process removing pseudo-gate dielectric layer of described dielectric layer, until flush with the top surface of described stop-layer.Therefore, after the described pseudo-gate dielectric layer of removal, described stop-layer and dielectric layer surface can keep smooth, and the grid layer of follow-up formation and the material of gate dielectric layer not easily residue in stop-layer and dielectric layer surface, ensure that formed transistor performance is stablized; And, namely can reach without the need to carrying out too much change to the forming process of transistor the effect improving transistor performance.
Further, the material of described stop-layer is silicon nitride, and described Doped ions is carbon ion.Material due to described pseudo-gate dielectric layer is silica, in the etching technics removing described pseudo-gate dielectric layer, described etching technics is extremely slow for the silicon nitride etch speed doped with carbon ion, therefore after the described pseudo-gate dielectric layer of removal, the pattern of described stop-layer and size can not change, and dielectric layer surface correspondingly can be reduced to the position flushed with stop-layer top, make the surface of dielectric layer and stop-layer smooth dry.
Accompanying drawing explanation
Fig. 1 is a kind of cross-sectional view of high-K metal gate transistor;
Fig. 2 to Fig. 4 is the cross-sectional view of the process of a kind of formation grid structure as shown in Figure 1;
Fig. 5 to Figure 11 is the cross-sectional view of the forming process of the transistor of the embodiment of the present invention.
Embodiment
As stated in the Background Art, the unstable properties of high-K metal gate transistor that formed of prior art.
Find through research, the technique of existing formation high-K metal gate transistor is rear grid technique (GateLast), and described rear grid technique can cause damage to the size of formed grid structure.Specifically please refer to Fig. 2 to Fig. 4, Fig. 2 to Fig. 4 is the cross-sectional view of the process of a kind of formation grid structure 110 as shown in Figure 1.
Please refer to Fig. 2, substrate 100 is provided, described substrate 100 surface has dummy gate structure 120, described dummy gate structure 120 comprises: be positioned at the pseudo-gate dielectric layer 121 of substrate surface, be positioned at the dummy gate layer 122 on pseudo-gate dielectric layer 121 surface and be positioned at the side wall 123 on dummy gate layer 122 and substrate 100 surface, pseudo-gate dielectric layer 121 both sides, described substrate 100 surface also has dielectric layer 105, and the surface of described dielectric layer 105 flushes with the surface of dummy gate layer 122.
Please refer to Fig. 3, remove described dummy gate layer 122(as shown in Figure 2), in described dielectric layer 105, form opening 124.
Please refer to Fig. 4, remove pseudo-gate dielectric layer 121(bottom described opening 124 as shown in Figure 3).
Wherein, material due to dummy gate layer 122 is polysilicon; and substrate 100 adopts silicon substrate usually; therefore the Etch selectivity between dummy gate layer 122 and substrate 100 is poor; therefore need to form pseudo-gate dielectric layer 121 between pseudo-gate dielectric layer 121 and substrate 100; described pseudo-gate dielectric layer 121 can when removing dummy gate layer 122, and protection substrate 100 surface is injury-free.The material of described pseudo-gate dielectric layer 121 is silica, and formation process is thermal oxidation technology, dummy gate layer 122 and substrate 100 can be made better to combine, be conducive to the carrying out of technique with the silica that thermal oxidation technology is formed.But, with the silica equivalent oxide thickness (EOT that thermal oxidation technology is formed, Equivalent Oxide Thickness) larger, along with reducing of dimensions of semiconductor devices, the pseudo-gate dielectric layer 121 be positioned at bottom opening 124 can cause adverse effect to the transistor performance of follow-up formation, and after the etching technics removing dummy gate layer 122, the thickness of described pseudo-gate dielectric layer 121 is wayward.Therefore, after the described dummy gate layer 122 of removal, need to remove described pseudo-gate dielectric layer 121 and expose substrate 100 surface, so that follow-up substrate 100 surface bottom opening 124 forms cushion oxide layer, gate dielectric layer and gate electrode layer.
But, material due to described dielectric layer 105 is also silica usually, therefore when removing described pseudo-gate dielectric layer 121, the thickness of the corresponding thinning described dielectric layer 105 of meeting, and, described side wall 123 also can be corresponding to etching to a certain extent, causes the uneven surface of described dielectric layer 105 and side wall 123.Follow-up in described opening 124, fill high-K gate dielectric layer and metal gate after, need to adopt glossing to remove the metal gate material on dielectric layer 105 surface, due to the uneven surface of described dielectric layer 105 and side wall 123, the material of metal gate is easily made to residue in dielectric layer 105 surface or side wall 123 top, easily make metal gate top produce leakage current, affect the performance of the transistor formed.
A kind of solution to the problems described above is; barrier layer is formed at substrate 100 and dummy gate structure 120 surface; it is follow-up when source region and surface, drain region form conductive structure; need to adopt etching technics to form opening in dielectric layer 105; and described barrier layer can define the stop position of described etching technics, to protect substrate 100 surface from damage.Described dielectric layer 105 is formed at described barrier layer surface, and the surface of dielectric layer 105 flushes with the barrier layer surface at dummy gate layer 122 top, and namely the surface of described dielectric layer 105 is higher than the surface of dummy gate layer 122.Before follow-up removal dummy gate layer 122 and pseudo-gate dielectric layer 121, need the barrier layer of first removing dummy gate layer 122 top, then top, remaining barrier layer flushes with dummy gate layer 122 surface or side wall 123 top, when the pseudo-gate dielectric layer 121 of follow-up removal, dielectric layer 105 can be made correspondingly to level off to and remain the equal position in top, barrier layer or side wall 123 top, to reach the object making dielectric layer 105 smooth with the surface of side wall 123.But, because the material on described barrier layer is generally silicon nitride, described silicon nitride still can be subject to etching to a certain extent in the process of etching gate dielectric layer 121, top, remaining barrier layer is caused to reduce, make after removal gate dielectric layer 121, described barrier layer is still difficult to reach flush with dielectric layer 105 surface, still understands the material on dielectric layer 105 surface or barrier layer and side wall 123 top kish grid.
In order to solve the problem, after further research, the present invention proposes a kind of formation method of transistor.Wherein, form stop-layer at described substrate and dummy gate structure surface, have Doped ions in described stop-layer, the dielectric layer surface of follow-up formation flushes with the stop-layer surface being positioned at dummy gate layer top.In order to remove dummy gate layer and pseudo-gate dielectric layer, need the stop-layer first removing dummy gate layer top, the stop-layer top being then positioned at dummy gate structure sidewall surfaces flushes with dummy gate layer surface, and described dielectric layer surface is higher than stop-layer top and dummy gate layer surface.After removal dummy gate layer, remove in the process of pseudo-gate dielectric layer, owing to having Doped ions in described stop-layer, the etch rate of stop-layer is reduced, and the top surface of described stop-layer can not be cut down; Meanwhile, surface corresponding reduction in the process removing pseudo-gate dielectric layer of described dielectric layer, until flush with the top surface of described stop-layer.Therefore, after the described pseudo-gate dielectric layer of removal, described stop-layer and dielectric layer surface can keep smooth, and the grid layer of follow-up formation and the material of gate dielectric layer not easily residue in stop-layer and dielectric layer surface, ensure that formed transistor performance is stablized; And, namely can reach without the need to carrying out too much change to the forming process of transistor the effect improving transistor performance.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
Fig. 5 to Figure 11 is the cross-sectional view of the forming process of the transistor of the embodiment of the present invention.
Please refer to Fig. 5, provide substrate 200, described substrate 200 surface has dummy gate structure 201, and described dummy gate structure 201 comprises: be positioned at the pseudo-gate dielectric layer 210 on substrate 200 surface and be positioned at the dummy gate layer 211 on pseudo-gate dielectric layer 210 surface.
Described substrate 200 is silicon substrate, silicon-Germanium substrate, silicon carbide substrates, silicon-on-insulator (SOI) substrate, germanium on insulator (GOI) substrate, glass substrate or III-V substrate (such as silicon nitride or GaAs etc.).In the present embodiment, described substrate 200 surface forms high-K metal gate transistor, and after described high-K metal gate transistor adopts, grid technique is formed, and needs the dummy gate structure 201 first forming alternative described high-K metal gate electrode structure.
In the present embodiment, described substrate 200 has first area I and second area II, and substrate 200 surface of described first area I and second area II all has dummy gate structure 201, described first area I and second area II can be used in the transistor forming difference in functionality or type.In one embodiment, described first area I is for the formation of PMOS transistor, and described second area II is for the formation of nmos pass transistor.In another embodiment, described first area I is for the formation of core devices, and described second area II is for the formation of input and output device.
Described dummy gate structure 201 is that the gate dielectric layer of follow-up formation and grid layer take up space, and the material of described pseudo-gate dielectric layer 210 is silica, and the material of described dummy gate layer 211 is polysilicon.The formation process of dummy gate structure 201 comprises: form pseudo-gate dielectric film on substrate 200 surface; At described pseudo-gate dielectric film surface deposition dummy grid film; Form patterned photoresist layer on described dummy grid film surface, described photoresist layer defines the correspondence position of pseudo-gate dielectric layer 210 and dummy gate layer 211; With described photoresist layer for dummy grid film described in mask etching and pseudo-gate dielectric film, till exposing substrate 200 surface.
Wherein, described pseudo-gate dielectric layer 210 is for when follow-up removal dummy gate layer 211, and protection substrate 200 surface is from damage.In the present embodiment, forming described pseudo-gate dielectric layer 210 technique is thermal oxidation technology, and the pseudo-gate dielectric layer 210 formed can make dummy gate layer 211 be combined with substrate 200 better.But, pseudo-gate dielectric layer 210 equivalent oxide thickness adopting thermal oxidation technology to be formed is higher, be unfavorable for that the size of semiconductor device reduces, and, when follow-up removal dummy gate layer 211, the inevitably pseudo-gate dielectric layer 210 of damaged portion, make the size of pseudo-gate dielectric layer 210 be difficult to accurate control, therefore, follow-up needs removes described pseudo-gate dielectric layer 210, and formed and meet the cushion oxide layer of technical need, as the binder course between the gate dielectric layer of follow-up formation and substrate.
In the present embodiment, described dummy gate structure 201 also comprises: be positioned at the sidewall surfaces of described dummy gate layer 211 and pseudo-gate dielectric layer 210 both sides and the side wall 212 on substrate 200 surface.
Described side wall 212 defines source region in the substrate 200 being formed at dummy gate structure 201 both sides and position, drain region 213.The material of described side wall 212 is one or more overlapping combinations in silica, silicon nitride, silicon oxynitride.The formation process of described side wall 212 comprises: at substrate 200, pseudo-gate dielectric layer 210 and dummy gate layer 211 surface deposition side wall film; Return the described side wall film of etching, till exposing dummy gate layer 211 top surface and substrate 200 surface.
After formation side wall 212, adopt ion implantation technology doped p-type ion or N-type ion in the substrate 200 of dummy gate layer 211 and side wall 212 both sides, form source region and drain region 213.After formation source region and drain region 213, at removal dummy gate layer 211 and pseudo-gate dielectric layer 210, and substitute with high-K gate dielectric layer and metal gate layers, the formation process i.e. rear grid technique of described transistor, namely after formation source region and drain region 213, forms grid layer.
Please refer to Fig. 6, form stop-layer 202 at described substrate 200 and dummy gate structure 201 surface, in described stop-layer 202, there is Doped ions.
Due to follow-up after formation grid layer and gate dielectric layer, need in dielectric layer, form the conductive structure being positioned at source region and surface, drain region 213, to realize the electrical connection of source region and drain region 213 and chip circuit; Wherein, in order to form described conductive structure; etching in the dielectric layer of follow-up formation is needed to form the opening exposing source region and drain region 213; in order to protect substrate 200 surface in described etching technics; before the described dielectric layer of formation, form stop-layer 202 on substrate 200 surface, described dielectric layer is formed at described stop-layer 202 surface; and described stop-layer 202 is different from the material of dielectric layer, make, between described stop-layer 202 and dielectric layer, there is Etch selectivity.
And; after formation stop-layer 202; after subsequent technique forms gate dielectric layer and grid layer; sidewall due to grid layer and side wall 212 has the protection of stop-layer 202; the conductive structure being formed at source region and surface, drain region 213 can remain autoregistration electrical contact (Self-Align Contact) technique and be formed; be conducive to the density and the integrated level that improve semiconductor device, reduce the size of semiconductor device and chip.
Because described stop-layer 202 is formed at dummy gate layer 211 top surface, and the dielectric layer of follow-up formation flushes with stop-layer 202 surface being positioned at dummy gate layer 211 top, described dielectric layer surface can be made higher than dummy gate layer 211 surface, then during the pseudo-gate dielectric layer 210 of follow-up removal, the thickness of dielectric layer can be made to be reduced to the position flushed with stop-layer 202 top.
In order to ensure in the process of follow-up removal gate dielectric layer 210, the size of described stop-layer 202 is precise and stable, need to make described stop-layer 202 can not be subject to etching to affect and height reduction, therefore need the etching technics of removal gate dielectric layer 210 is reduced the etch rate of stop-layer 202, and namely the Doped ions in described stop-layer 202 can improve the Etch selectivity of stop-layer 202, make the technique of subsequent etching gate dielectric layer 210 extremely low for the etch rate of stop-layer 202.
In the present embodiment, the material of described stop-layer 202 is silicon nitride, and the Doped ions in described stop-layer 202 is carbon ion.Because the material of described pseudo-gate dielectric layer 210 is silica, and the technique of etching oxidation silicon is extremely low for the silicon nitride etch speed of carbon dope, therefore, it is possible to ensure in the process of follow-up removal gate dielectric layer 210, the pattern of described stop-layer 202 and size can keep stable, and the height of described stop-layer 202 can not reduce.
The formation process of described stop-layer 202 comprises: at the surface deposition stopper film of substrate 200 and grid structure 201; Doping process is adopted to form Doped ions at described stopper film.Wherein, the concentration of the Doped ions in described stop-layer 202 is 0.5E15 atom/square centimeter ~ 12E15 atom/square centimeter; And the technique of the described Doped ions that adulterates in stop-layer 202 is ion implantation technology or in-situ doped technique.In the present embodiment, the technique of the described Doped ions that adulterates in stop-layer 202 is ion implantation technology, and Implantation Energy is 200 electron-volts ~ 50 kilo electron volts.
Please refer to Fig. 7, form dielectric layer 203 on described stop-layer 202 surface, described dielectric layer 203 surface flushes with stop-layer 202 surface being positioned at dummy gate layer 211 top.
The material of described dielectric layer 203 is one or more combinations in silica, silicon nitride, silicon oxynitride, low-K dielectric material, and the material of described dielectric layer 203 is different from the material of stop-layer 202, make, between described stop-layer 202 and dielectric layer 203, there is Etch selectivity; In the present embodiment, the material of described dielectric layer 203 is silica.
The formation process of described dielectric layer 203 comprises: at stop-layer 202 surface deposition deielectric-coating; Adopt deielectric-coating described in CMP (Chemical Mechanical Polishing) process planarization, until expose the stop-layer 202 of dummy gate layer 211 top surface, form dielectric layer 203.After described CMP (Chemical Mechanical Polishing) process, the surface of described dielectric layer 203 flushes with stop-layer 202 surface being positioned at dummy gate layer 211 top, namely the surface of described dielectric layer 203 is higher than the surface of dummy gate layer 211, then after the pseudo-gate dielectric layer 210 of follow-up removal, the surface of dielectric layer 203 can be made to flush with stop-layer 202 top of fertility, be conducive to making stop-layer 202, dielectric layer 203 and side wall 212 keep smooth, thus at the material of dielectric layer 203, stop-layer 202 top or side wall 212 top surface kish grid after avoiding follow-up formation grid layer.
In the present embodiment, substrate 200 surface has some dummy gate structure 201, and has the groove exposing substrate 200 or source region and drain region 213 between adjacent dummy gate structure 201.In order to reduce the size of semiconductor device and chip, distance between the size of described dummy gate structure 201 and adjacent dummy gate structure 201 is corresponding to be reduced, thus improve the density of transistor or integrated level that are formed, cause the groove between adjacent dummy gate structure 201 to be parallel to the size of substrate 20 surface direction less.And the degree of depth of described groove can not change, then depth-to-width ratio (the AR of described groove, Aspect Ratio) increase, the material for the formation of dielectric layer 203 is easily caused to be difficult to enter described groove, make the dielectric layer inside being formed at groove form space (void), cause the unstable properties of formed semiconductor device.
Therefore, in the present embodiment, the technique forming described deielectric-coating is high-aspect-ratio depositing operation (HARP, High Aspect Ratio Process), and described high-aspect-ratio depositing operation can make the deielectric-coating densification be formed in groove.The parameter of described high-aspect-ratio depositing operation comprises: deposition gases comprises tetraethoxysilane and ozone, the flow of described tetraethoxysilane is 500 milli gram/minute ~ 8000 milli gram/minute, the flow of ozone be 5000 standard milliliters/minute ~ 3000 standard milliliters/minute, air pressure is that 300 holder ~ 600 are held in the palm, and temperature is 400 degrees Celsius ~ 600 degrees Celsius; In addition, described deposition gases can also comprise: nitrogen, oxygen and helium, the flow of nitrogen be 1000 standard milliliters/minute ~ 10000 standard milliliters/minute, the flow of oxygen be 0 standard milliliters/minute ~ 5000 standard milliliters/minute, the flow of helium be 5000 standard milliliters/minute ~ 20000 standard milliliters/minute.
Please refer to Fig. 8, after formation dielectric layer 203, remove the stop-layer 202 at dummy gate layer 211 top, till exposing dummy gate layer 211 top surface.
The technique of described removal dummy gate layer 211 is dry etch process or wet-etching technology.In the present embodiment, the technique removing pseudo-gate dielectric layer 211 is dry etch process, and the material due to described dummy gate layer 211 is polysilicon, and the etching gas of described dry etch process comprises the mixture of chlorine, helium, hydrogen bromide or helium and oxygen.In another embodiment, the technique removing dummy gate layer 211 is wet-etching technology, and etching liquid comprises Tetramethylammonium hydroxide, and the mass percent concentration of described Tetramethylammonium hydroxide in etching liquid is 2% ~ 4%, and etching temperature is 50 DEG C ~ 90 DEG C.
Described in the technique of described removal dummy gate layer 211 can cause pseudo-gate dielectric layer 210, the thickness of described pseudo-gate dielectric layer 210 is made to be difficult to keep evenly accurately; And the formation process of described pseudo-gate dielectric layer 210 is thermal oxidation technology, makes the equivalent oxide thickness of described pseudo-gate dielectric layer 210 comparatively large, the process requirements of high-K metal gate transistor cannot be met.Therefore, after removal dummy gate layer 211, also need to remove described pseudo-gate dielectric layer 210.
Please refer to Fig. 9, after the stop-layer 202 removing dummy gate layer 211 top, remove dummy gate layer 211(as shown in Figure 8) and pseudo-gate dielectric layer 210(is as shown in Figure 8), till exposing substrate 200 surface, in described dielectric layer 203, form opening 204.
The technique removing pseudo-gate dielectric layer 210 is wet-etching technology or dry etch process.In the present embodiment, the technique removing pseudo-gate dielectric layer 210 is dry etch process, and because the material of described pseudo-gate dielectric layer 210 is silica, the gas of described dry etch process comprises CHF 3, CF 4, one or more combinations in HF.In another embodiment, the technique removing pseudo-gate dielectric layer 210 is wet-etching technology, and etching liquid comprises hydrofluoric acid.
Material due to described dielectric layer 203 is also silica, and therefore in the process removing described pseudo-gate dielectric layer 210, described dielectric layer 203 also can be etched, and makes the thickness of described dielectric layer 203 can the position that flushes as stop-layer 202 top of corresponding reduction.Simultaneously, owing to there is Doped ions in described stop-layer 202, the Etch selectivity of described stop-layer 202 is improved, extremely low at the etch rate of technique to described stop-layer 202 of the pseudo-gate dielectric layer of described etching 210, therefore described stop-layer 202 can not be subject to the damage of etching technics, make the pattern of described stop-layer 202 and size keep stable, the height of described stop-layer 202 can not reduce.Therefore, it is possible to ensure that described dielectric layer 203 can flush with stop-layer 202 after removal gate dielectric layer 210, then during follow-up formation grid layer, can not at the material of stop-layer 202 top and dielectric layer 203 remained on surface metal gate.
Please refer to Figure 10, dielectric layer 203 surface and opening 204(as shown in Figure 9) sidewall and lower surface deposition gate dielectric film 205; The gate electrode film 206 of full gate mouth 204 is filled at gate dielectric film 205 surface deposition.
The material of described gate dielectric film 205 is high K dielectric material, and described high K dielectric material comprises hafnium oxide, zirconia, hafnium silicon oxide, lanthana, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium or aluminium oxide.The formation process of described gate dielectric film 205 is chemical vapor deposition method or physical gas-phase deposition.
In order to improve the binding ability between gate dielectric film 205 and substrate 200, before the described gate dielectric film 205 of formation, form cushion oxide layer 207 at dielectric layer 203 surface and the sidewall of opening 204 and lower surface, it is surperficial that described gate dielectric film 205 is formed at described liner oxide film 207.The material of described liner oxidation silicon fiml 207 is silica, and the formation process of described liner oxide film 207 is chemical vapor deposition method.And the liner oxide film 207 adopting chemical vapor deposition method to be formed not only thickness is even, and equivalent electrical thickness is lower, the technical need of compound high-K metal gate transistor.
The material of described gate electrode film 206 is metal, and described metal comprises copper, tungsten or aluminium, and the formation process of described gate electrode film 206 is chemical vapor deposition method, physical gas-phase deposition or electroplating technology.In one embodiment, in order to regulate the threshold voltage of formed transistor, before the described gate electrode film 206 of formation, work-function layer can be formed on described gate dielectric film 205 surface.The material of described work-function layer is electric conducting material, and for regulating the threshold voltage of transistor, and the material of described work-function layer is according to the type selecting of the transistor of required formation, work function value is more suitable for and forms PMOS transistor or nmos pass transistor.
In other embodiments, spread in the gate dielectric film 205 of high K dielectric material to prevent the metal material of gate electrode film 206, before the good gate electrode film 206 of formation work-function layer, barrier layer can be formed on gate dielectric film 205 surface, the material on described barrier layer is one or more combinations in titanium, titanium nitride, tantalum, tantalum nitride, and the formation process on described barrier layer is chemical vapor deposition method.
Please refer to Figure 11, adopt gate electrode film 206(described in CMP (Chemical Mechanical Polishing) process planarization as shown in Figure 9) and gate dielectric film 205(is as shown in Figure 9), till exposing dielectric layer 203 surface, gate dielectric layer 205a and grid layer 206a is formed at described opening 204(as shown in Figure 9), described gate dielectric layer 205a is positioned at sidewall and the lower surface of opening 204, and described grid layer 206a is positioned at gate dielectric layer 205a surface and is formed and fills full described opening 204.
In the present embodiment, owing to also there is liner oxide film 207(as shown in Figure 9 between gate dielectric film 205 and substrate 200), therefore at gate dielectric layer 205a with form liner oxidation layer 207a between opening 204 sidewall and lower surface.
Described CMP (Chemical Mechanical Polishing) process, for removing the liner oxide film 207 on dielectric layer 203 surface, gate dielectric film 205 and gate electrode film 206, makes formed gate dielectric layer 205a and grid layer 206a only be formed in opening 204.Because the surface of described dielectric layer 203 and stop-layer 202 can keep flushing, therefore the surface of described dielectric layer 203 and stop-layer 202 is smooth, in described CMP (Chemical Mechanical Polishing) process, the material of gate dielectric film 205 and gate electrode film 206 can not residue in dielectric layer 203 surface or stop-layer 202 top, can avoid and produce leakage current at grid layer 206a top because metal material is residual, thus ensure that the stable performance of formed transistor.
In the present embodiment, form stop-layer at described substrate and dummy gate structure surface, have Doped ions in described stop-layer, the dielectric layer surface of follow-up formation flushes with the stop-layer surface being positioned at dummy gate layer top.In order to remove dummy gate layer and pseudo-gate dielectric layer, need the stop-layer first removing dummy gate layer top, the stop-layer top being then positioned at dummy gate structure sidewall surfaces flushes with dummy gate layer surface, and described dielectric layer surface is higher than stop-layer top and dummy gate layer surface.After removal dummy gate layer, remove in the process of pseudo-gate dielectric layer, owing to having Doped ions in described stop-layer, the etch rate of stop-layer is reduced, and the top surface of described stop-layer can not be cut down; Meanwhile, surface corresponding reduction in the process removing pseudo-gate dielectric layer of described dielectric layer, until flush with the top surface of described stop-layer.Therefore, after the described pseudo-gate dielectric layer of removal, described stop-layer and dielectric layer surface can keep smooth, and the grid layer of follow-up formation and the material of gate dielectric layer not easily residue in stop-layer and dielectric layer surface, ensure that formed transistor performance is stablized; And, namely can reach without the need to carrying out too much change to the forming process of transistor the effect improving transistor performance.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.

Claims (16)

1. a formation method for transistor, is characterized in that, comprising:
There is provided substrate, described substrate surface has dummy gate structure, and described dummy gate structure comprises: be positioned at the pseudo-gate dielectric layer of substrate surface and be positioned at the dummy gate layer on pseudo-gate dielectric layer surface;
Form stop-layer at described substrate and dummy gate structure surface, in described stop-layer, there is Doped ions;
Form dielectric layer on described stop-layer surface, described dielectric layer surface flushes with the stop-layer surface being positioned at dummy gate layer top;
Remove the stop-layer at dummy gate layer top, dummy gate layer and pseudo-gate dielectric layer, in described dielectric layer, form opening;
In described opening, form gate dielectric layer and grid layer, described gate dielectric layer is positioned at sidewall and the lower surface of opening, and described grid layer is positioned at gate dielectric layer surface and is formed fills full described opening.
2. the formation method of transistor as claimed in claim 1, it is characterized in that, the material of described stop-layer is silicon nitride, and described Doped ions is carbon ion.
3. the formation method of transistor as claimed in claim 1, it is characterized in that, the concentration of the Doped ions in described stop-layer is 0.5E15 atom/square centimeter ~ 12E15 atom/square centimeter.
4. the formation method of transistor as claimed in claim 1, it is characterized in that, the technique of the described Doped ions that adulterates in stop-layer is ion implantation technology or in-situ doped technique.
5. the formation method of transistor as claimed in claim 4, it is characterized in that, when the technique of the described Doped ions that adulterates in stop-layer is ion implantation technology, Implantation Energy is 200 electron-volts ~ 50 kilo electron volts.
6. the formation method of transistor as claimed in claim 1, it is characterized in that, the technique removing the stop-layer at dummy gate layer top, dummy gate layer and pseudo-gate dielectric layer comprises: the stop-layer at etching dummy gate layer top, till exposing dummy gate layer top surface; After the stop-layer at etching dummy gate layer top, etch described dummy gate layer and pseudo-gate dielectric layer, till exposing substrate surface.
7. the formation method of transistor as claimed in claim 1, it is characterized in that, the material of described pseudo-gate dielectric layer is silica, and the material of described dummy gate layer is polysilicon.
8. the formation method of transistor as claimed in claim 7, it is characterized in that, the formation process of described pseudo-gate dielectric layer comprises thermal oxidation technology.
9. the formation method of transistor as claimed in claim 7, it is characterized in that, the technique removing pseudo-gate dielectric layer is wet-etching technology or dry etch process.
10. the formation method of transistor as claimed in claim 1, is characterized in that, also comprise: before forming gate dielectric layer, and in sidewall and the lower surface formation cushion oxide layer of described opening, described gate dielectric layer is formed at described cushion oxide layer surface.
The formation method of 11. transistors as claimed in claim 10, it is characterized in that, the material of described pad silicon oxide layer is silica, the formation process of described cushion oxide layer is chemical vapor deposition method.
The formation method of 12. transistors as claimed in claim 1, it is characterized in that, the formation process of described gate dielectric layer and gate electrode layer comprises: at sidewall and the lower surface deposition gate dielectric film of dielectric layer surface and opening; The gate electrode film of full gate mouth is filled at gate dielectric film surface deposition; Adopt gate electrode film and gate dielectric film described in CMP (Chemical Mechanical Polishing) process planarization, till exposing dielectric layer surface, described gate electrode film forms grid layer, and described gate dielectric film forms gate dielectric layer.
The formation method of 13. transistors as claimed in claim 1, it is characterized in that, the material of described gate dielectric layer is high K dielectric material, the material of described grid layer is metal.
The formation method of 14. transistors as claimed in claim 1, it is characterized in that, described dummy gate structure also comprises: be positioned at described dummy gate layer and the pseudo-sidewall surfaces of gate dielectric layer both sides and the side wall of substrate surface.
The formation method of 15. transistors as claimed in claim 1, is characterized in that, the material of described dielectric layer is silica, and the formation process of described dielectric layer comprises: at stop-layer surface deposition deielectric-coating; Adopt deielectric-coating described in CMP (Chemical Mechanical Polishing) process planarization, until expose the stop-layer of dummy gate layer top surface, form dielectric layer.
The formation method of 16. transistors as claimed in claim 1, is characterized in that, also comprise: before formation stop-layer, form source region and drain region in the substrate of described dummy gate structure both sides.
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