CN107046005A - Improve the method for device performance - Google Patents
Improve the method for device performance Download PDFInfo
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- CN107046005A CN107046005A CN201610083851.6A CN201610083851A CN107046005A CN 107046005 A CN107046005 A CN 107046005A CN 201610083851 A CN201610083851 A CN 201610083851A CN 107046005 A CN107046005 A CN 107046005A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A kind of method of improvement device performance, including：Using the first pseudo- grid as mask, the NMOS area substrate to the first pseudo- grid both sides carries out the first n-type doping processing, forms N-type source-drain area；Using the second pseudo- grid as mask, the PMOS area substrate to the second pseudo- grid both sides carries out the first p-type doping treatment, forms p-type source-drain area；Interlayer dielectric layer is formed on substrate surface, N-type source-drain area surface and p-type source-drain area surface；Second p-type doping treatment is carried out to the first pseudo- grid；Second n-type doping processing is carried out to the second pseudo- grid；After the second p-type doping treatment and the processing of the second n-type doping is carried out, etching removes the described first pseudo- grid and the second pseudo- grid in the processing step with along with.The present invention improves the etching homogeneity that etching removes the first pseudo- grid and the second pseudo- grid so that the first pseudo- grid and the second pseudo- grid are by etching is removed completely simultaneously, it is to avoid the first pseudo- grid residual or the second pseudo- grid residual, so as to improve the electric property of the device of formation.
Description
Technical field
It is more particularly to a kind of to improve the method for device performance the present invention relates to technical field of manufacturing semiconductors.
Background technology
With continuing to develop for semiconductor process technique, semiconductor technology node follows the development of Moore's Law
Trend constantly reduces.In order to adapt to the reduction of process node, it has to constantly shorten MOSFET field-effects
The channel length of pipe.Tube core density of the shortening with increase chip of channel length, increases MOSFET
The benefits such as the switching speed of effect pipe.
However, with the shortening of device channel length, the distance between device source electrode and drain electrode also shortens therewith,
So grid is deteriorated to the control ability of raceway groove, the difficulty of grid voltage pinch off (pinch off) raceway groove
Also it is increasing so that sub-threshold leakage (subthreshold leakage) phenomenon, i.e., so-called short channel
Effect (SCE：Short-channel effects) it is easier to occur.
Therefore, in order to preferably adapt to the requirement that device size is scaled, semiconductor technology is gradually opened
The transistor transient begun from planar MOSFET transistor to the three-dimensional with more high effect, such as fin
Formula FET (FinFET).In FinFET, grid can at least enter from both sides to ultra-thin body (fin)
Row control, can be fine with control ability of the grid more much better than than planar MOSFET devices to raceway groove
Suppression short-channel effect；And FinFET is relative to other devices, with more preferable existing integrated circuit
The compatibility of manufacturing technology.
However, the electric property of the device of prior art formation has much room for improvement.
The content of the invention
The problem of present invention is solved is to provide a kind of method of improvement device performance, it is to avoid etching removes first
After pseudo- grid and the second pseudo- grid, substrate surface still has the first pseudo- grid residual or the second pseudo- grid residual, improves
The performance of the device of formation.
To solve the above problems, the present invention provides a kind of method of improvement device performance, including：Bag is provided
The substrate of NMOS area and PMOS area is included, the NMOS area substrate surface is formed with first
Pseudo- grid, the PMOS area substrate surface is formed with the second pseudo- grid；Using the described first pseudo- grid as mask,
NMOS area substrate to the described first pseudo- grid both sides carries out the first n-type doping processing, forms N-type source
Drain region；Using the described second pseudo- grid as mask, the PMOS area substrate to the described second pseudo- grid both sides is carried out
First p-type doping treatment, forms p-type source-drain area；The substrate surface, N-type source-drain area surface with
And p-type source-drain area surface forms interlayer dielectric layer, the pseudo- grid side wall of interlayer dielectric layer covering first and
Second pseudo- grid side wall；Second p-type doping treatment is carried out to the described first pseudo- grid；Described second pseudo- grid are entered
The processing of the n-type doping of row second；It is handled in progress the second p-type doping treatment and the second n-type doping
Afterwards, etching removes the described first pseudo- grid and the second pseudo- grid in the processing step with along with.
Optionally, etching removes the etch rate of the described first pseudo- grid and etching removes the described second pseudo- grid
Etch rate is identical.
Optionally, the first pseudo- grid and the second pseudo- grid for removing segment thickness are first etched using dry etch process,
Then, the remaining first pseudo- grid and the second pseudo- grid are removed using wet-etching technology etching；Or, use
Wet-etching technology etching removes the described first pseudo- grid and the second pseudo- grid.
Optionally, after the second p-type doping treatment and the processing of the second n-type doping is carried out, to institute
State the first pseudo- grid and the second pseudo- grid are made annealing treatment.
Optionally, carried out in the NMOS area substrate to the described first pseudo- grid both sides at the first n-type doping
While reason, the first n-type doping processing also is carried out to the first pseudo- grid.
Optionally, the Doped ions concentration of the second n-type doping processing is handled with the first n-type doping
Doped ions concentration is identical；The Doped ions and the first n-type doping of the second n-type doping processing are handled
Doped ions it is identical.
Optionally, carried out in the PMOS area substrate to the described second pseudo- grid both sides at the first p-type doping
While reason, the first p-type doping treatment also is carried out to the second pseudo- grid.
Optionally, the Doped ions concentration of the second p-type doping treatment and the first p-type doping treatment
Doped ions concentration is identical；The Doped ions of the second p-type doping treatment and the first p-type doping treatment
Doped ions it is identical.
Optionally, the Doped ions of the first n-type doping processing are P, As or Sb, the first N
The Doped ions concentration of type doping treatment is 2E14atom/cm2To 2E15atom/cm2；Second N-type
The Doped ions of doping treatment are P, As or Sb, the Doped ions concentration of the second n-type doping processing
For 2E14atom/cm2To 2E15atom/cm2。
Optionally, the Doped ions of the first p-type doping treatment are B, BF2, Ga or In, it is described
The Doped ions concentration of first p-type doping treatment is 2E14atom/cm2To 2E15atom/cm2；Described
The Doped ions of two p-type doping treatments are B, BF2, Ga or In, the second p-type doping treatment
Doped ions concentration is 2E14atom/cm2To 2E15atom/cm2。
Optionally, it is described before the first n-type doping processing and the first p-type doping treatment is carried out
The material of first pseudo- grid and the second pseudo- grid is identical.
Optionally, it is described before the first n-type doping processing and the first p-type doping treatment is carried out
The material of first pseudo- grid is polysilicon, non-crystalline silicon or amorphous carbon；Carrying out at first n-type doping
Before reason and the first p-type doping treatment, the materials of the second pseudo- grid is polysilicon, non-crystalline silicon or without fixed
Shape carbon.
Optionally, carrying out the processing step of the second p-type doping treatment includes：In the described second pseudo- grid
Top surface the first graph layer of formation；Using first graph layer as mask, the described first pseudo- grid are carried out
Second p-type doping treatment；Remove first graph layer.
Optionally, carrying out the processing step of the second n-type doping processing includes：In the described first pseudo- grid
Top surface formation second graph layer；With second graph layer for mask, the described second pseudo- grid are carried out
The processing of second n-type doping；Remove the second graph layer.
Optionally, after etching removes the described first pseudo- grid and the second pseudo- grid, in addition to step：
NMOS area substrate surface formation first grid；In PMOS area substrate surface formation second grid.
Optionally, the first stressor layers are also formed with the N-type source-drain area；In the p-type source-drain area also
It is formed with the second stressor layers.
Optionally, the interlayer dielectric layer includes etching stop layer and Jie positioned at etching stopping layer surface
Matter layer；Before the second n-type doping processing and the second p-type doping treatment is carried out, abrasive media layer
Until exposing the etching stop layer at the top of the first pseudo- grid and at the top of the second pseudo- grid；Carrying out described the
After the processing of two n-type dopings and the second p-type doping treatment, grinding is removed higher than at the top of the first pseudo- grid and the
Etching stop layer at the top of two pseudo- grid.
Optionally, the interlayer dielectric layer includes etching stop layer and Jie positioned at etching stopping layer surface
Matter layer；Before the second n-type doping processing and the second p-type doping treatment is carried out, grinding removes high
Dielectric layer at the top of the first pseudo- grid and at the top of the second pseudo- grid, also grinding remove higher than at the top of the first pseudo- grid and
Etching stop layer at the top of second pseudo- grid.
Optionally, the interlayer dielectric layer is single layer structure, carry out second n-type doping processing and
Before second p-type doping treatment, remove higher than the inter-level dielectric at the top of the first pseudo- grid and at the top of the second pseudo- grid
Layer.
Optionally, the substrate includes substrate and the fin positioned at substrate surface, wherein, described first
Pseudo- grid across first area fin, and covering first area fin atop part and side wall, the N
Type source-drain area is located in the fin of NMOS area；The second pseudo- grid across second area fin, and
The atop part and side wall of second area fin are covered, the p-type source-drain area is located at the fin of PMOS area
In portion.
Compared with prior art, technical scheme has advantages below：
In the technical scheme of the method for the improvement device performance that the present invention is provided, using the first pseudo- grid as mask pair
The NMOS area substrate of first pseudo- grid both sides carries out the first n-type doping processing, forms N-type source-drain area,
In this course, also it is mixed with N-type ion in the described first pseudo- grid；By mask of the second pseudo- grid to the
The PMOS area substrate of two pseudo- grid both sides carries out the first p-type doping treatment, forms p-type source-drain area,
During this, p-type ion is also mixed with the described second pseudo- grid；After interlayer dielectric layer is formed, this
Invention also carries out the second p-type doping treatment to the first pseudo- grid so that be also mixed with the first pseudo- grid p-type from
Second pseudo- grid are also carried out the second n-type doping processing by son so that be also mixed with the second pseudo- grid N-type from
Son.Due to, not only doped with p-type ion but also doped with N-type ion, both being mixed in the second pseudo- grid in the first pseudo- grid
It is miscellaneous to have p-type ion again doped with p-type ion so that N-type ion pair etching removes the first pseudo- grid and second
The influence of the etching technics of pseudo- grid is close or identical, and p-type ion pair etching removes the first pseudo- grid and the second pseudo- grid
Etching technics influence close to or it is identical, therefore, etching removes the etching of the first pseudo- grid and the second pseudo- grid
Speed is close or identical, improves the etching homogeneity that etching removes the first pseudo- grid and the second puppet grid, so that
Obtain the first pseudo- grid and the second pseudo- grid removed by etching off in the same time, it is to avoid the first pseudo- grid residual or the second puppet grid residual,
So as to improve the electric property of device, device production yield is improved.
Further, the Doped ions concentration of the second n-type doping processing is handled with the first n-type doping
Doped ions concentration is identical；The Doped ions and the first n-type doping of the second n-type doping processing are handled
Doped ions it is identical.So that N-type ion pair etching removes the influence of the first pseudo- grid etch rate and to carving
Etching off is identical except the influence of the second pseudo- grid etch rate, and the pseudo- grid and second of N-type ion pair first are completely eliminated
The harmful effect that pseudo- grid etch rate difference is caused.
Further, the Doped ions concentration of the second p-type doping treatment and the first p-type doping treatment
Doped ions concentration it is identical；At the Doped ions of the second p-type doping treatment and the first p-type doping
The Doped ions of reason are identical.So that p-type ion pair etching remove the influence of the first pseudo- grid etch rate with it is right
The influence that etching removes the second pseudo- grid etch rate is identical, and the pseudo- grid of p-type ion pair first and the is completely eliminated
The harmful effect that two pseudo- grid etch rate differences are caused.
Brief description of the drawings
The cross-sectional view for the device forming process that Fig. 1 to Figure 13 provides for one embodiment of the invention.
Embodiment
From background technology, the device performance of prior art formation has much room for improvement.
In one embodiment, forming the processing step of device includes：Offer includes NMOS area and PMOS
The substrate in region, the NMOS area substrate surface is formed with the first pseudo- grid, the PMOS area base
Basal surface is formed with the second pseudo- grid；NMOS area substrate progress N-type to the described first pseudo- grid both sides is mixed
It is miscellaneous, N-type source-drain area is formed in NMOS area substrate；To the PMOS of the described second pseudo- grid both sides
Substrate areas carries out p-type doping, and p-type source-drain area is formed in PMOS area substrate；In the substrate
Surface forms interlayer dielectric layer, the pseudo- grid side wall of the interlayer dielectric layer covering first and the second pseudo- grid side wall；
Etching removes the described first pseudo- grid and the second pseudo- grid, and the is formed in the NMOS area interlayer dielectric layer
One opening, forms the second opening in the PMOS area interlayer dielectric layer；In the described first opening
Form first grid；Second grid is formed in the described second opening.
Find after etching removes the described first pseudo- grid and the second pseudo- grid, have in the first opening through analysis
Having in the first pseudo- grid residual (residue) or the second opening has the second pseudo- grid residual, the described first pseudo- grid
It is the one of the main reasons for causing device performance low that residual or the second pseudo- grid, which are remained,.Further study show that,
Causing in the first opening to have in the first pseudo- grid residual or the second opening, there is the reason for the second pseudo- grid are remained to exist
In：
The n-type doping of foregoing progress is also doped to the first pseudo- grid, is had in the described first pseudo- grid
N-type ion, likewise, the p-type doping of foregoing progress is also doped to the second pseudo- grid so that
There is p-type ion in described second pseudo- grid；Due to etching technics to the first pseudo- grid with N-type ion and
It is different to the etch rate of the second pseudo- grid with p-type ion so that etching technics is to the first pseudo- grid and the
The etch rate difference of two pseudo- grid is larger, and etching technics homogeneity (Uniformity) is poor, therefore ought judge
First pseudo- grid stop etching technics when being removed by complete etching, and the actually second pseudo- grid are complete not yet
Etching is removed, and the pseudo- grid residual of second in the second opening will influence device performance；Or, when judging
Two pseudo- grid stop etching technics when being removed by complete etching, and the actually first pseudo- grid are not carved completely yet
Etching off is removed, and the pseudo- grid residual of first in the first opening will influence device performance.
To solve the above problems, the present invention provides a kind of method for improving device performance, there is provided including NMOS
Region and the substrate of PMOS area, the NMOS area substrate surface are formed with the first pseudo- grid, described
PMOS area substrate surface is formed with the second pseudo- grid；Using the described first pseudo- grid as mask, to described first
The NMOS area substrate of pseudo- grid both sides carries out the first n-type doping processing, forms N-type source-drain area；With institute
It is mask to state the second pseudo- grid, and the first p-type of PMOS area substrate progress to the described second pseudo- grid both sides is mixed
Reason is lived together, p-type source-drain area is formed；In the substrate surface, N-type source-drain area surface and p-type source and drain
Area surface forms interlayer dielectric layer, the pseudo- grid side wall of the interlayer dielectric layer covering first and the second pseudo- grid side
Wall；Second p-type doping treatment is carried out to the described first pseudo- grid；Second N-type is carried out to the described second pseudo- grid
Doping treatment；After the second p-type doping treatment and the processing of the second n-type doping is carried out, same
Etching removes the described first pseudo- grid and the second pseudo- grid in road processing step.
In the present invention, etching removes the etching technics of the first pseudo- grid and the second pseudo- grid to the first pseudo- grid and second
Pseudo- grid have etch rate it is poor (that is, etching technics to the etch rates of the first pseudo- grid and etching technics to the
Difference between the etch rate of two pseudo- grid), the etch rate difference is the smaller the better.Using the first pseudo- grid to cover
Film carries out being also doped with N-type ion in the first n-type doping processing, therefore the first pseudo- grid, and the present invention is to the
Two pseudo- grid also carry out the second n-type doping processing so that be also doped with N-type ion in the second pseudo- grid, therefore
The influence of N-type ion pair etch rate difference in first pseudo- grid is partly or entirely offset；With the second pseudo- grid
Carry out being also doped with p-type ion in the first p-type doping treatment, therefore the second pseudo- grid for mask, the present invention
Second p-type doping treatment is also carried out to the first pseudo- grid so that be also doped with p-type ion in the first pseudo- grid,
Therefore, the influence of the p-type ion pair etch rate difference in the second pseudo- grid is partly or entirely offset.Thus,
When etching removes first pseudo- grid and the second pseudo- grid in the etching technics with along with, etching removes the first pseudo- grid
The etch rate that etch rate removes the second pseudo- grid with etching is close or identical, therefore when etching technics is completed
Afterwards, the described first pseudo- grid and the second pseudo- grid are etched removals, it is to avoid the first pseudo- grid residual or the second puppet grid
Residual, so as to improve the electric property of the device of formation, improves device production yield.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
The cross-sectional view for the device forming process that Fig. 1 to Figure 13 provides for one embodiment of the invention.
With reference to Fig. 1, there is provided the substrate including NMOS area I and PMOS area II.
In the present embodiment, so that the semiconductor devices of formation is fin field effect pipe as an example, the substrate includes：
Substrate 101 and the fin 102 positioned at the surface of substrate 101, wherein, the NMOS area I substrates
101 surfaces are formed with discrete fin 102, and the surface of PMOS area II substrates 101 is formed with discrete
Fin 102.
In another embodiment, the semiconductor devices is planar transistor, and the substrate is planar substrates,
The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate
Or germanium substrate on insulator, glass substrate or III-V substrate (such as gallium nitride substrate or arsenic
Gallium substrate etc.), grid structure is formed at the plane.
The material of the substrate 101 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 101；The fin 102
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium.It is described in the present embodiment
Substrate 101 is silicon substrate, and the material of the fin 102 is silicon.
In the present embodiment, forming the substrate 101, the processing step of fin 102 includes：Initial lining is provided
Bottom；Patterned hard mask layer is formed in the initial substrate surface；Carved by mask of the hard mask layer
The initial substrate after the initial substrate, etching is lost as substrate 101, the projection positioned at the surface of substrate 101
It is used as fin 102；Remove the hard mask layer.
In one embodiment, forming the processing step of the hard mask layer includes：It is initially formed initial hard
Mask；Patterned photoresist layer is formed in the initial hard mask surface；With the patterned photoetching
Glue-line is initial hard mask described in mask etching, in initial substrate surface formation hard mask layer；Remove described
Patterned photoresist layer.In other embodiments, the formation process of the hard mask layer can also include：
Self-alignment duplex pattern (SADP, Self-aligned Double Patterned) technique, autoregistration are triple
Graphical graphical (the Self-aligned of (Self-aligned Triple Patterned) technique or autoregistration quadruple
Double Double Patterned) technique.The Dual graphing technique includes LELE
(Litho-Etch-Litho-Etch) technique or LLE (Litho-Litho-Etch) technique.
In the present embodiment, the top dimension of the fin 102 is less than bottom size.In other embodiments,
The side wall of the fin can also be perpendicular with substrate surface, i.e., the top dimension of fin is equal to bottom size.
Also include step：Separation layer 103 is formed on the surface of substrate 101, the separation layer 103 is covered
The partial sidewall surface of fin 102, and the top of the separation layer 103 is less than the top of fin 102.Institute
State separation layer 103 to play a part of being electrically isolated adjacent fin 102, the material of the separation layer 103 is oxygen
SiClx, silicon nitride or silicon oxynitride.In the present embodiment, the material of the separation layer 103 is silica.
With reference to Fig. 2, pseudo- grid film 104 is formed in the substrate surface.
The pseudo- grid film 104 provides Process ba- sis, subsequent figure to be subsequently formed the first pseudo- grid and the second pseudo- grid
The shape NMOS area I pseudo- grid of pseudo- grid film 104 formation first, graphical PMOS area II pseudo- grid
The pseudo- grid of the formation of film 104 second.
In the present embodiment, the pseudo- top of the covering of grid film 104 fin 102 and sidewall surfaces and isolation
103 surface of layer, the pseudo- top of grid film 104 is higher than the top of fin 102.According to follow-up to be formed the
One top portions of gates position and second grid tip position, determine the thickness of the pseudo- grid film 104.
The material of the pseudo- grid film 104 is polysilicon, non-crystalline silicon or amorphous carbon；Using chemical vapor deposition
Product technique, physical gas-phase deposition or atom layer deposition process form the pseudo- grid film 104.The present embodiment
In, the material of the pseudo- grid film 104 is polysilicon, and the pseudo- grid are formed using chemical vapor deposition method
Film 104.
In other embodiments, additionally it is possible to pseudo- oxide layer, the pseudo- oxygen are formed between substrate and pseudo- grid film
Changing layer can play a part of protecting substrate surface, prevent subsequent etching from removing the first pseudo- grid and the second pseudo- grid
Technique etching injury is caused to substrate；The material of the pseudo- oxide layer is silica.
With reference to Fig. 3, the graphical pseudo- grid film 104 (referring to Fig. 2), in the NMOS area I portions
Divide substrate surface formation first pseudo- grid 114, second is formed on the PMOS area II part of substrate surface
Pseudo- grid 124.
Described first pseudo- grid 114 occupy the locus for the first grid being subsequently formed；Described second pseudo- grid
124 occupy the locus for the second grid being subsequently formed.In the present embodiment, the described first pseudo- grid 114
In the surface of NMOS area I parts separation layer 103, and across NMOS area I fin 102, cover
The lid NMOS area I atop part of fin 102 and side wall；Described second pseudo- grid 124 are located at PMOS
The surface of region II parts separation layer 103, and across PMOS area II fin 102, cover PMOS
The region II atop part of fin 102 and side wall.
Specifically, forming the processing step of the described first pseudo- pseudo- grid 124 of grid 114 and second includes：Institute
State the pseudo- surface of grid film 104 and form patterned mask layer (not indicating), the patterned mask layer definition
Go out the positions and dimensions of the first pseudo- pseudo- grid 124 of grid 114 and second；Using the patterned mask layer to cover
Film, etches the pseudo- grid film 104 until exposing the surface of separation layer 103, forms the described first pseudo- grid 114
With the second pseudo- grid 124.
The material of described first pseudo- grid 114 is identical with the material of the second pseudo- grid 124.Described first pseudo- grid 114
Material be polysilicon, non-crystalline silicon or amorphous carbon；The material of the second pseudo- grid 124 is polysilicon,
Non-crystalline silicon or amorphous carbon.In the present embodiment, the material of the described first pseudo- grid 114 is polysilicon；It is described
The material of second pseudo- grid 124 is polysilicon.
In the present embodiment, the described first pseudo- sidewall surfaces of grid 114 and the second pseudo- sidewall surfaces of grid 124 are also
Side wall 100 is formed with, the material of the side wall 100 is silica or silicon nitride.It is described in the present embodiment
The material of side wall 100 is silicon nitride, in other embodiments, and the side wall is ONO
(Oxide-Nitride-Oxide) laminated construction.It should be noted that in other embodiments of the present invention,
First pseudo- grid sidewall surfaces and the second pseudo- grid sidewall surfaces can not also form side wall.
In the present embodiment, after the described first pseudo- pseudo- grid 124 of grid 114 and second are formed, reservation is located at
The patterned mask layer of the first pseudo- top surface of grid 114 and the second pseudo- top surface of grid 124, rear
During the first stressor layers of continuous formation, patterned the covering for being located at the first pseudo- top surface of grid 114
Film layer plays a part of being blocked in the first pseudo- grown on top the first stress layer material of grid 114；It is being subsequently formed
During second stressor layers, the patterned mask layer for being located at the second pseudo- top surface of grid 124 rises
To the effect for being blocked in the second pseudo- grown on top the second stress layer material of grid 124.
It is mask with the described first pseudo- grid 114 with reference to Fig. 4, to the NMOS of the described first pseudo- both sides of grid 114
Region I substrates carry out the first n-type doping processing, and N-type source is formed in the NMOS area I substrates
Drain region 106.
In the present embodiment, the N-type source-drain area 106 is located at the NMOS area of the first pseudo- both sides of grid 114
In I fins 102.
The Doped ions of the first n-type doping processing are P, As or Sb, first n-type doping
The Doped ions concentration of processing is 2E14atom/cm2To 2E15atom/cm2.In the present embodiment, described
The Doped ions of one n-type doping processing are P or As.
In one embodiment, carrying out the processing step of the first n-type doping processing includes：Institute
PMOS area II substrate surfaces and the second pseudo- top surface of grid 124 the first mask layer 105 of formation are stated,
Specific in the present embodiment, first mask layer 105 covers the surface of PMOS area II separation layers 103
And the second pseudo- top surface of grid 124；To the NMOS area I substrates of the described first pseudo- both sides of grid 114
Carry out the first n-type doping processing；Remove first mask layer 105.
In the environment that the first pseudo- grid 114 are handled exposed to the first n-type doping so as to described the
While the NMOS area I substrates of the one pseudo- both sides of grid 114 carry out the processing of the first n-type doping, also to the
One pseudo- grid 114 carry out the N-type ion concentration in the first n-type doping processing, and the described first pseudo- grid 114
It is identical with the N-type ion concentration in N-type source-drain area 106, i.e. the N-type ion in the first pseudo- grid 114
It is identical with the Doped ions of the first n-type doping processing, and N-type ion concentration in the first pseudo- grid 114 with
The Doped ions concentration of first n-type doping processing is identical, and the N-type ion in the described first pseudo- grid 114 is dense
Spend for 2E14atom/cm2To 2E15atom/cm2。
In the present embodiment, the first stressor layers are also formed with the N-type source-drain area 106.Specifically,
Before carrying out first n-type doping processing, in addition to step：To the described first pseudo- both sides of grid 114
Substrate performs etching to form the first groove；The first stressor layers of full first groove of filling are formed, it is described
First stressor layers are suitable to improve the stress for putting on NMOS tube channel region.First stressor layers
Material is SiC or SiCP.After first stressor layers are formed, first stressor layers are carried out with the
The processing of one n-type doping, forms the N-type source-drain area 106.
Then, the N-type source-drain area 106 is made annealing treatment, the annealing is suitable to activation N
Doped ions in type source-drain area 106, and repair the lattice damage that the processing of the first n-type doping is caused to substrate
Wound.In other embodiments, additionally it is possible to after p-type source-drain area is subsequently formed, while to N-type source-drain area
Made annealing treatment with p-type source-drain area.
It is mask with the described second pseudo- grid 124 with reference to Fig. 5, to the PMOS of the described second pseudo- both sides of grid 124
Region II substrates carry out the first p-type doping treatment, form p-type source-drain area 107.
In the present embodiment, the p-type source-drain area 107 is located at the PMOS area of the second pseudo- both sides of grid 124
In II fins 102.
The Doped ions of the first p-type doping treatment are B, BF2, Ga or In, second p-type
The Doped ions concentration of doping treatment is 2E14atom/cm2To 2E15atom/cm2.In the present embodiment, institute
The Doped ions for stating the first p-type doping treatment are B or BF2.
In one embodiment, carrying out the processing step of the first p-type doping treatment includes：Institute
NMOS area I substrate surfaces and the first pseudo- top surface of grid 114 the second mask layer 108 of formation are stated,
Specific in the present embodiment, second mask layer 108 covers the surface of NMOS area I separation layers 103
And the first pseudo- top surface of grid 114；PMOS area II substrates to the described second pseudo- both sides of grid 14 are entered
Row the first p-type doping treatment；Remove second mask layer 108.
The second pseudo- grid 124 are in the environment of the first p-type doping treatment so as to described the
While the PMOS area I substrates of the two pseudo- both sides of grid 124 carry out the first p-type doping treatment, also to the
Two pseudo- grid 124 carry out the p-type ion concentration in the first p-type doping treatment, and the described second pseudo- grid 124
It is identical with the p-type ion concentration in p-type source-drain area 107, i.e. the p-type in the described second pseudo- grid 124
Ion is identical with the Doped ions of the first p-type doping treatment, and the p-type ion in the second pseudo- grid 124 is dense
Degree it is identical with the Doped ions concentration of the first p-type doping treatment, it is described second puppet grid 124 in p-type from
Sub- concentration is 2E14atom/cm2To 2E15atom/cm2。
In the present embodiment, the second stressor layers are also formed with the p-type source-drain area 107.Specifically,
Before carrying out the first p-type doping treatment, in addition to step：To the described second pseudo- both sides of grid 124
Substrate performs etching to form the second groove；The second stressor layers of full second groove of filling are formed, it is described
Second stressor layers are suitable to improve the stress for putting on PMOS channel region.Second stressor layers
Material is SiGe or SiGeB.After second stressor layers are formed, second stressor layers are carried out
First p-type doping treatment, forms the p-type source-drain area 107.
Then, the p-type source-drain area 107 is made annealing treatment, the annealing is suitable to activation P
Doped ions in type source-drain area 107, and repair the lattice damage that the first p-type doping treatment is caused to substrate
Wound.In other embodiments, additionally it is possible to subsequently carrying out the processing of the second n-type doping and the doping of the second p-type
After processing, while being annealed to N-type source-drain area, p-type source-drain area, the first pseudo- grid and the second pseudo- grid
Processing.
It should be noted that in an alternative embodiment of the invention, additionally it is possible to first in the base of the first pseudo- grid both sides
The first stressor layers are formed in bottom, the second stressor layers are formed in the substrate of the second pseudo- grid both sides；Forming institute
State after the first stressor layers and the second stressor layers, the first n-type doping processing carried out to first stressor layers,
Form N-type source-drain area；First p-type doping treatment is carried out to second stressor layers, p-type source and drain is formed
Area.
With reference to Fig. 6, in the substrate surface, the surface of N-type source-drain area 106 and the table of p-type source-drain area 107
Face forms interlayer dielectric layer, the pseudo- side wall of grid 114 of the interlayer dielectric layer covering first and the second pseudo- grid 124
Side wall.
In the present embodiment, the interlayer dielectric layer also covers the first pseudo- top surface of grid 114 and the second puppet
The top surface of grid 124.The interlayer dielectric layer includes etching stop layer 201 and positioned at etching stop layer
The dielectric layer 202 on 201 surfaces, because rear extended meeting is performed etching to interlayer dielectric layer, formation exposes N-type
The contact hole of source-drain area 106 or p-type source-drain area 107, the etching stop layer 201 can play etching
The effect of stopping, it is to avoid etching injury is caused to N-type source-drain area 106 or p-type source-drain area 107.
The material of the etching stop layer 201 is different from the material of dielectric layer 202；Using chemical vapor deposition
Product technique, physical gas-phase deposition or atom layer deposition process form the etching stop layer 201.This reality
Apply in example, the material of the etching stop layer 201 is silicon nitride, and the material of the dielectric layer 202 is oxygen
SiClx.In other embodiments, the interlayer dielectric layer can also be the single layer structure of dielectric layer, and described
At the top of the pseudo- grid of interlayer dielectric layer covering first and at the top of the second pseudo- grid.
With reference to Fig. 7, abrasive media layer 202 is until expose positioned at the first pseudo- top of grid 114 and the second pseudo- grid
The etching stop layer 201 at 124 tops.
In the present embodiment, using chemical mechanical milling tech, grinding removes the dielectric layer 202 of segment thickness,
Until the etching stop layer 201 at the first pseudo- top of grid 114 and the second pseudo- top of grid 124 is exposed, it is described to carve
It is grinding stop position to lose the top surface of stop-layer 201.
Due to being only etched at the top of the first pseudo- top of grid 114 and the second pseudo- grid 124, stop-layer 201 is covered,
So that the Doped ions of the second follow-up p-type doping treatment are easily doped into the first pseudo- grid 114 so that after
The Doped ions of continuous the second n-type doping processing formed are easily doped into the second pseudo- grid 124.
With reference to Fig. 8, the second p-type doping treatment 210 is carried out to the described first pseudo- grid 114.
In the present embodiment, the processing step of the second p-type doping treatment 210 includes：Described second
In the first graph layer 211 of the pseudo- top surface of grid 124 formation, the present embodiment, first graph layer of formation
211 are located at the surface of etching stop layer 201 at the first pseudo- top of grid 124, and the first graph layer is formed in order to reduce
211 technology difficulty, first graph layer 211 is also located at the PMOS area II table of dielectric layer 202
Face；It is mask with first graph layer 211, the second p-type doping is carried out to the described first pseudo- grid 114
Processing 210；Then, first graph layer 211 is removed.
In the present embodiment, the material of first graph layer 211 is Other substrate materials.Positioned at nmos area
Domain I dielectric layer 202 plays the second p-type doping treatment 210 of stop and N-type source-drain area 106 is mixed
Miscellaneous effect.
The effect of the second p-type doping treatment 210 is：Extended meeting etching removes the first pseudo- grid 114 afterwards
With the second pseudo- grid 124, the etching technics is to the first pseudo- grid 114 and the etch rate to the second pseudo- grid 124
Difference should be smaller by even zero so that the etching that etching removes the first pseudo- pseudo- grid 124 of grid 114 and second is equal
One property is good, it is to avoid the first pseudo- grid 114 are remained or the second pseudo- grid 124 are remained.First p-type of foregoing progress
Doping treatment is adulterated to the second pseudo- grid 124 so that doped with p-type ion in the second pseudo- grid 124；
After the second p-type doping treatment 210 is carried out to the first pseudo- grid 114 so that also mixed in the first pseudo- grid 114
It is miscellaneous to have p-type ion, and then reduce etch rate described in p-type ion pair in the pseudo- grid 124 of even elimination second
Difference influence, improve the etching homogeneity that subsequent etching removes the first pseudo- pseudo- grid 124 of grid 114 and second.
If not carrying out the second p-type doping treatment to the first pseudo- grid, the first pseudo- grid and the are removed in subsequent etching
In the technical process of two pseudo- grid, the p-type ion of doping can change etching technics to the second puppet in the second pseudo- grid
The etch rate of grid, and undoped with there is p-type ion in the first pseudo- grid, therefore etching technics is to the first pseudo- grid
Difference with the etch rate to the second pseudo- grid is larger, and etching technics homogeneity is poor.
In order that obtaining influence and the second pseudo- grid 124 of the p-type ion pair etch rate in the first pseudo- grid 114
The influence of interior p-type ion pair etch rate is identical, further improves subsequent etching processes to the first pseudo- grid
114 and second pseudo- grid 124 etching homogeneity, in the present embodiment, the second p-type doping treatment 210
Doped ions concentration it is identical with the Doped ions concentration of the first p-type doping treatment；Also, the 2nd P
The Doped ions of type doping treatment 210 are identical with the Doped ions of the first p-type doping treatment.
It should be noted that in other embodiments, the Doped ions of the second p-type doping treatment are dense
Degree can also be more than or less than the Doped ions concentration of the first p-type doping treatment, with not entering to the first pseudo- grid
Row the second p-type doping treatment is compared, and the second p-type doping treatment is carried out still in certain journey to the first pseudo- grid
The influence of the difference of p-type ion pair etch rate in the second pseudo- grid can be reduced on degree, subsequent etching is improved and go
Except the etching homogeneity of the first pseudo- grid and the second pseudo- grid.Explanation is needed further exist for, when the second p-type is mixed
When the Doped ions concentration for living together reason is more than the Doped ions concentration of the first p-type doping treatment, both mixes
The difference of heteroion concentration should be less than the Doped ions concentration of the first p-type doping treatment.
Specifically, the Doped ions of the second p-type doping treatment 210 are B, BF2, Ga or In,
The Doped ions concentration of the second p-type doping treatment 210 is 2E14atom/cm2To 2E15atom/cm2。
In the present embodiment, the second p-type doping treatment 210 is carried out using ion implantation technology.It is described from
The Implantation Energy of sub- injection technology is unsuitable too small, otherwise reaches in the first pseudo- grid 114 close to substrate surface area
P-type ion concentration in domain is few；The Implantation Energy of the ion implantation technology is also unsuitable excessive, and otherwise the
The p-type ion of two p-type doping treatments 210 is easily injected into substrate or in N-type source-drain area 106.
With reference to Fig. 9, the second n-type doping processing 220 is carried out to the described second pseudo- grid 124.
Specifically, carrying out the processing step of the second n-type doping processing 220 includes：Described first
In the pseudo- top surface of grid 114 formation second graph layer 221, the present embodiment, 221 shape of the second graph layer
Into in the surface of etching stop layer 201 of the second pseudo- top surface of grid 114, and second graph layer 221
It is also located at the NMOS area I surface of dielectric layer 202；It is mask with second graph layer 221, it is right
Described second pseudo- grid 124 carry out the second n-type doping processing 220；Then, the second graph layer is removed
221。
In the present embodiment, the material of the second graph layer 221 is Other substrate materials.Positioned at PMOS areas
Domain II dielectric layer 202 plays stop the second n-type doping 220 pairs of p-type source-drain areas 107 of processing and mixed
Miscellaneous effect.
The effect of the second n-type doping processing 220 is：Extended meeting etching removes the first pseudo- grid 114 afterwards
With the second pseudo- grid 124, the etching technics to the etch rates of the first pseudo- pseudo- grid 124 of grid 114 and second it
Difference should be smaller by even zero so that the etching that etching removes the first pseudo- pseudo- grid 124 of grid 114 and second is homogeneous
Property it is good, it is to avoid the first pseudo- grid 114 are remained or the second pseudo- grid 124 are remained.First N-type of foregoing progress is mixed
Live together reason to adulterate to the first pseudo- grid 114 so that doped with N-type ion in the first pseudo- grid 114；
After the second n-type doping processing 220 is carried out to the second pseudo- grid 124 so that also mixed in the second pseudo- grid 124
It is miscellaneous to have N-type ion, and then reduce etch rate described in N-type ion pair in the pseudo- grid 114 of even elimination first
Difference influence, improve the etching homogeneity that subsequent etching removes the first pseudo- pseudo- grid 124 of grid 114 and second.
If not carrying out the second n-type doping processing to the second pseudo- grid, the first pseudo- grid and the are removed in subsequent etching
In the technical process of two pseudo- grid, the N-type ion or change etching technics of doping are pseudo- to first in the first pseudo- grid
The etch rate of grid, and undoped with there is N-type ion in the second pseudo- grid, therefore etching technics is to the first pseudo- grid
Difference with the etch rate of the second pseudo- grid is larger, and etching homogeneity is poor.
In order that obtaining influence and the first pseudo- grid 114 of the N-type ion pair etch rate in the second pseudo- grid 124
The influence of interior N-type ion pair etch rate is identical, further improves subsequent etching processes to the first pseudo- grid
114 and second pseudo- grid 124 etching homogeneity, in the present embodiment, the second n-type doping processing 220
Doped ions concentration it is identical with the Doped ions concentration that the first n-type doping is handled；Also, described second
The Doped ions of n-type doping processing 220 are identical with the Doped ions that the first n-type doping is handled.
It should be noted that in other embodiments, the Doped ions of the second n-type doping processing are dense
Degree can also be more than or less than the Doped ions concentration that the first n-type doping is handled, with not entering to the second pseudo- grid
The processing of the n-type doping of row second is compared, and the second n-type doping processing is carried out still in certain journey to the second pseudo- grid
The influence of the difference of N-type ion pair etch rate in the first pseudo- grid can be reduced on degree, subsequent etching is improved and go
Except the etching homogeneity of the first pseudo- grid and the second pseudo- grid.Explanation is needed further exist for, when the second N-type is mixed
When the Doped ions concentration for living together reason is more than the Doped ions concentration that the first n-type doping is handled, both mixes
The difference of heteroion concentration should be less than the Doped ions concentration of the first n-type doping processing.
Specifically, the Doped ions of second n-type doping processing 220 are P, As or Sb, described the
The Doped ions concentration of two n-type dopings processing 220 is 2E14atom/cm2To 2E15atom/cm2。
In the present embodiment, the second n-type doping processing 220 is carried out using ion implantation technology.It is described
The Implantation Energy of ion implantation technology is unsuitable too small, otherwise reaches in the second pseudo- grid 124 close to substrate surface
N-type ion concentration in region is few；The Implantation Energy of the ion implantation technology is also unsuitable excessive, otherwise
The N-type ion of second n-type doping processing 220 is easily injected into substrate or in p-type source-drain area 107.
With reference to Figure 10, the second p-type doping treatment 210 (referring to Fig. 8) and the second N-type are being carried out
After doping treatment 220 (referring to Fig. 9), the described first pseudo- pseudo- grid 124 of grid 114 and second are moved back
Fire processing 230.
The annealing 230 is suitable to Doped ions and the second pseudo- grid 124 in the pseudo- grid 114 of activation first
Interior Doped ions so that the Doped ions in the first pseudo- grid 114 carry out concentration redistribution, are conducive to carrying
High follow-up etching technics is to the etch rate homogeneity of the first pseudo- grid 114, mixing in the second pseudo- grid 124
Heteroion carries out concentration redistribution, is conducive to raising etching technics equal to the etch rate of the second pseudo- grid 124
One property.
The annealing 230 is laser annealing, rapid thermal annealing or spike annealing.The annealing
230 annealing temperature is unsuitable too high, otherwise the doping in N-type source-drain area 106 or p-type source-drain area 107
Ion can be spread again, cause the Doped ions in N-type source-drain area 106 or p-type source-drain area 107 dense
Spend changes in distribution.
In the present embodiment, the technique of the annealing 230 is spike annealing, and temperature is 1000 DEG C
-1100℃。
With reference to Figure 11, after the second n-type doping processing and the second p-type doping treatment is carried out, grind
Grind off except the etching stop layer 201 higher than the first pseudo- top of grid 114 and the second pseudo- top of grid 124, also continue to
Grinding removes the dielectric layer 202 higher than the first pseudo- top of grid 114 and the second pseudo- top of grid 124.
In the present embodiment, using chemical mechanical milling tech, grinding is removed higher than the first pseudo- top of grid 114
With the etching stop layer 201 and dielectric layer 202 at the second pseudo- top of grid 124.
In other embodiments, additionally it is possible to carried out to the first pseudo- pseudo- grid 124 of grid 114 and second at annealing
Before reason, grinding is removed higher than the etching stop layer and dielectric layer at the top of the first pseudo- grid and at the top of the second pseudo- grid.
It should be noted that in other embodiments, additionally it is possible to carrying out the processing of the second n-type doping and the
Before two p-type doping treatments, grinding removes good higher than at the top of the first pseudo- grid and at the top of the second pseudo- grid media
Layer, also grinding are removed higher than the etching stop layer at the top of the first pseudo- grid and at the top of the second pseudo- grid so that first
It is exposed at the top of pseudo- grid and at the top of the second pseudo- grid.Or, the interlayer dielectric layer is single layer structure,
Before the second n-type doping processing and the second p-type doping treatment is carried out, remove higher than the first pseudo- grid
Interlayer dielectric layer at the top of top and the second pseudo- grid.
With reference to Figure 12, etching removes the described first pseudo- grid 114 (referring to Figure 11) in the processing step with along with
With the second pseudo- grid 124 (referring to Figure 11).
In one embodiment, the first pseudo- grid 114 for removing segment thickness are first etched using dry etch process
With the second pseudo- grid 124；Then, the remaining first pseudo- grid 114 and the are removed using wet-etching technology etching
Two pseudo- grid 124.
Specifically, the solution of the wet-etching technology is TMAH.
In another embodiment, the described first pseudo- grid 114 and second are removed using wet-etching technology etching
Pseudo- grid 124.Specifically, the solution of the wet-etching technology is TMAH..
It should be noted that the present embodiment is before the pseudo- grid 124 of the pseudo- grid 114 and second of etching first, also
Etching removes the patterned mask layer for being located at the first pseudo- top of grid 114 and the second pseudo- top of grid 124.
The etching technics has etch rate poor the first pseudo- pseudo- grid 124 of grid 114 and second.Forming N
During type source-drain area 106, N-type ion is doped with the first pseudo- grid 114；And to the second pseudo- grid 124
The processing of the second n-type doping is carried out so that be also doped with N-type ion in the second pseudo- grid 124.Therefore,
In the technical process that etching removes the first pseudo- pseudo- grid 124 of grid 114 and second, the N in the first pseudo- grid 114
The influence of the difference of type ion pair etch rate is by the N-type ionic portions in the second pseudo- grid 124 or all offsets,
Therefore the influence very little even zero of the difference of the N-type ion pair etch rate in the first pseudo- grid 114.
During p-type source-drain area 107 is formed, p-type ion is doped with the described second pseudo- grid 124；
And the second p-type doping treatment has been carried out to the first pseudo- grid 114 so that also it is doped with P in the first pseudo- grid 114
Type ion.Therefore, in the technical process that etching removes the first pseudo- pseudo- grid 124 of grid 114 and second, institute
The influence of difference of p-type ion pair etch rate in the second pseudo- grid 124 is stated by the P in the first pseudo- grid 114
Type ionic portions are all offset, therefore the difference of the p-type ion pair etch rate in the second pseudo- grid 124
Influence very little even zero.
As the above analysis, etching of the etching technics to the first pseudo- pseudo- grid 124 of grid 114 and second
The difference very little even zero of speed, etching technics etching removes the first pseudo- pseudo- grid 124 of grid 114 and second
Homogeneity is improved, so as to prevent that the first pseudo- grid 114 from being remained or the second pseudo- grid 124 are remained.
In the present embodiment, because the Doped ions concentration of second n-type doping processing is mixed with the first N-type
The Doped ions concentration for living together reason is identical, and the Doped ions of the second n-type doping processing are mixed with the first N-type
The Doped ions for living together reason are identical, Doped ions concentration and the first p-type of the second p-type doping treatment
The Doped ions concentration of doping treatment is identical, and the Doped ions and the first p-type of the second p-type doping treatment
The Doped ions of doping treatment are identical, therefore the etch rate of the pseudo- grid 114 of N-type ion pair first and to the
The influence of the etch rate of two pseudo- grid 124 is identical, the etch rate of the pseudo- grid 114 of p-type ion pair first and right
The influence of the etch rate of second pseudo- grid 124 is identical so that etching removes the etching speed of the first pseudo- grid 114
Rate is identical with the etch rate that etching removes the second pseudo- grid 124, when the etching removes the first pseudo- grid 114
At the end of the technique of the second pseudo- grid 124, the first pseudo- pseudo- grid 124 of grid 114 and second are by etching off in the same time
Remove, it is to avoid the first pseudo- grid 114 are remained or the second pseudo- grid 124 are remained.
Etching removes the first pseudo- grid 114, exposes NMOS area I part of substrate surface, the present embodiment
In, the NMOS area I atop part of fin 102 and side wall is exposed, NMOS area is also exposed
The I surface of part separation layer 103.Etching removes the second pseudo- grid 124, exposes PMOS area II parts
In substrate surface, the present embodiment, the PMOS area II atop part of fin 102 and side wall is exposed,
Also expose the PMOS area II surface of part separation layer 103.
With reference to Figure 13, follow-up processing step also includes：In the NMOS area I substrates exposed
Surface forms first grid 301, and the top of first grid 301 is flushed with interlayer dielectric layer top surface；
In the PMOS area II substrate surfaces formation second grid 302 exposed, the second grid 302
Top at the top of interlayer dielectric layer with flushing.
In the present embodiment, the first grid 301 covers NMOS across NMOS area I fins 102
The atop part of region I fins 102 and sidewall surfaces；The second grid 302 is across PMOS area II
Fin 102, and the atop part of covering PMOS area II fins 102 and sidewall surfaces.
The first grid 301 include the first gate dielectric layer and positioned at first grid dielectric layer surface first
Gate electrode layer, additionally it is possible to including the N-type work content between the first gate dielectric layer and first gate electrode layer
Several layers.The second grid 302 include the second gate dielectric layer and positioned at second gate dielectric layer surface the
Two gate electrode layer, additionally it is possible to including the p-type work(between the second gate dielectric layer and the second gate electrode layer
Function layer.Wherein, the material of the first gate dielectric layer be silica or one kind in high-k gate dielectric material or
A variety of, the material of the second gate dielectric layer is the one or more in silica or high-k gate dielectric material, institute
State high-k gate dielectric material including LaO, AlO, BaZrO, HfZrO, HfZrON, HfLaO, HfSiO,
HfSiON、LaSiO、AlSiO、HfTaO、HfTiO、Al2O3Or Si3N4.The first gate electrode layer
Material be Al, Cu, Ag, Au, Pt, Ni, T or W；The material of second gate electrode layer is
Al, Cu, Ag, Au, Pt, Ni, T or W.The material of the N-type workfunction layer be TiAl, TiAlC,
One or more in TaAlN, TiAlN, MoN, TaCN or AlN；The P-type workfunction layer
Material is the one or more in Ta, TiN, TaSiN or TiSiN.
Because before first grid 301 and second grid 302 is formed, described first is pseudo- in the present embodiment
The pseudo- grid 124 of grid 114 and second are removed by complete etching so that the first grid 301 and second gate of formation
Pole 302 has better quality, interface characteristics between the first grid 301 and NMOS area I substrates
Can be good, the interface performance between the second grid 302 and PMOS area II substrates is good, so that
The device performance of formation is improved.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of improve the method for device performance, it is characterised in that including：
Offer includes the substrate of NMOS area and PMOS area, the NMOS area substrate surface
The first pseudo- grid are formed with, the PMOS area substrate surface is formed with the second pseudo- grid；
Using the described first pseudo- grid as mask, the is carried out to the NMOS area substrates of the described first pseudo- grid both sides
The processing of one n-type doping, forms N-type source-drain area；
Using the described second pseudo- grid as mask, the is carried out to the PMOS area substrates of the described second pseudo- grid both sides
One p-type doping treatment, forms p-type source-drain area；
Interlayer dielectric layer is formed on the substrate surface, N-type source-drain area surface and p-type source-drain area surface,
The pseudo- grid side wall of the interlayer dielectric layer covering first and the second pseudo- grid side wall；
Second p-type doping treatment is carried out to the described first pseudo- grid；
Second n-type doping processing is carried out to the described second pseudo- grid；
After the second p-type doping treatment and the processing of the second n-type doping is carried out, in the technique with along with
Etching removes the described first pseudo- grid and the second pseudo- grid in step.
2. improve the method for device performance as claimed in claim 1, it is characterised in that etching removes described first
The etch rate of pseudo- grid is identical with the etch rate that etching removes the described second pseudo- grid.
3. improve the method for device performance as claimed in claim 1, it is characterised in that first using dry etching work
Skill etching removes the first pseudo- grid and the second pseudo- grid of segment thickness, then, is etched using wet-etching technology
Remove the remaining first pseudo- grid and the second pseudo- grid；Or, remove described the using wet-etching technology etching
One pseudo- grid and the second pseudo- grid.
4. improve the method for device performance as claimed in claim 1, it is characterised in that carrying out the 2nd P
After type doping treatment and the processing of the second n-type doping, the described first pseudo- grid and the second pseudo- grid are annealed
Processing.
5. improve the method for device performance as claimed in claim 1, it is characterised in that to the described first pseudo- grid
While the NMOS area substrates of both sides carries out the processing of the first n-type doping, also the first pseudo- grid are carried out with the
The processing of one n-type doping.
6. improve the method for device performance as claimed in claim 5, it is characterised in that second n-type doping
The Doped ions concentration of processing is identical with the Doped ions concentration that the first n-type doping is handled；2nd N
The Doped ions of type doping treatment are identical with the Doped ions that the first n-type doping is handled.
7. improve the method for device performance as claimed in claim 1, it is characterised in that to the described second pseudo- grid
While the PMOS area substrates of both sides carries out the first p-type doping treatment, also the second pseudo- grid are carried out with the
One p-type doping treatment.
8. improve the method for device performance as claimed in claim 7, it is characterised in that the second p-type doping
The Doped ions concentration of processing is identical with the Doped ions concentration of the first p-type doping treatment；2nd P
The Doped ions of type doping treatment are identical with the Doped ions of the first p-type doping treatment.
9. improve the method for device performance as claimed in claim 1, it is characterised in that first n-type doping
The Doped ions of processing are P, As or Sb, and the Doped ions concentration of the first n-type doping processing is
2E14atom/cm2To 2E15atom/cm2；The Doped ions of the second n-type doping processing are P, As
Or Sb, the Doped ions concentration of the second n-type doping processing is 2E14atom/cm2Extremely
2E15atom/cm2。
10. improve the method for device performance as claimed in claim 1, it is characterised in that the first p-type doping
The Doped ions of processing are B, BF2, Ga or In, the Doped ions of the first p-type doping treatment are dense
Spend for 2E14atom/cm2To 2E15atom/cm2；The Doped ions of the second p-type doping treatment be B,
BF2, Ga or In, the Doped ions concentration of the second p-type doping treatment is 2E14atom/cm2Extremely
2E15atom/cm2。
11. improve the method for device performance as claimed in claim 1, it is characterised in that carrying out the first N
Before type doping treatment and the first p-type doping treatment, the material of the described first pseudo- grid and the second pseudo- grid is identical.
12. improve the method for device performance as claimed in claim 11, it is characterised in that carrying out the first N
Before type doping treatment and the first p-type doping treatment, the material of the described first pseudo- grid is polysilicon, amorphous
Silicon or amorphous carbon；Before the first n-type doping processing and the first p-type doping treatment is carried out, institute
The material for stating the second pseudo- grid is polysilicon, non-crystalline silicon or amorphous carbon.
13. improve the method for device performance as claimed in claim 1, it is characterised in that carry out second p-type
The processing step of doping treatment includes：In described second pseudo- grid top surface the first graph layer of formation；With institute
The first graph layer is stated for mask, the second p-type doping treatment is carried out to the described first pseudo- grid；Remove described
One graph layer.
14. improve the method for device performance as claimed in claim 1, it is characterised in that carry out second N-type
The processing step of doping treatment includes：In the described first pseudo- grid top surface formation second graph layer；With institute
It is mask to state second graph layer, and the second n-type doping processing is carried out to the described second pseudo- grid；Remove described
Two graph layers.
15. improve the method for device performance as claimed in claim 1, it is characterised in that remove described the in etching
After one pseudo- grid and the second pseudo- grid, in addition to step：In NMOS area substrate surface formation first grid；
In PMOS area substrate surface formation second grid.
16. improve the method for device performance as claimed in claim 1, it is characterised in that in the N-type source-drain area
It is also formed with the first stressor layers；The second stressor layers are also formed with the p-type source-drain area.
17. improve the method for device performance as claimed in claim 1, it is characterised in that the interlayer dielectric layer bag
Include etching stop layer and the dielectric layer positioned at etching stopping layer surface；Carrying out second n-type doping
Before processing and the second p-type doping treatment, abrasive media layer until expose at the top of the first pseudo- grid and
Etching stop layer at the top of second pseudo- grid；Carrying out the second n-type doping processing and the doping of the second p-type
After processing, grinding is removed higher than the etching stop layer at the top of the first pseudo- grid and at the top of the second pseudo- grid.
18. improve the method for device performance as claimed in claim 1, it is characterised in that the interlayer dielectric layer bag
Include etching stop layer and the dielectric layer positioned at etching stopping layer surface；Carrying out second n-type doping
Before processing and the second p-type doping treatment, grinding is removed higher than at the top of the first pseudo- grid and at the top of the second pseudo- grid
Dielectric layer, also grinding removed higher than the etching stop layer at the top of the first pseudo- grid and at the top of the second pseudo- grid.
19. improve the method for device performance as claimed in claim 1, it is characterised in that the interlayer dielectric layer is
Single layer structure, before the second n-type doping processing and the second p-type doping treatment is carried out, is removed high
Interlayer dielectric layer at the top of the first pseudo- grid and at the top of the second pseudo- grid.
20. improve the method for device performance as claimed in claim 1, it is characterised in that the substrate includes substrate
And positioned at the fin of substrate surface, wherein, the first pseudo- grid and cover across the fin of first area
The atop part and side wall of lid first area fin, the N-type source-drain area are located at the fin of NMOS area
It is interior；The second pseudo- grid across second area fin, and the atop part of covering second area fin and
Side wall, the p-type source-drain area is located in the fin of PMOS area.
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