CN106847755A - The method for improving SRAM performances - Google Patents
The method for improving SRAM performances Download PDFInfo
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- CN106847755A CN106847755A CN201510896857.0A CN201510896857A CN106847755A CN 106847755 A CN106847755 A CN 106847755A CN 201510896857 A CN201510896857 A CN 201510896857A CN 106847755 A CN106847755 A CN 106847755A
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- 238000000034 method Methods 0.000 title claims abstract description 67
- 230000005540 biological transmission Effects 0.000 claims abstract description 120
- 239000000758 substrate Substances 0.000 claims abstract description 85
- 239000000463 material Substances 0.000 claims abstract description 59
- 230000006872 improvement Effects 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims description 46
- 150000002500 ions Chemical class 0.000 claims description 36
- 230000015572 biosynthetic process Effects 0.000 claims description 16
- 238000012545 processing Methods 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
- 229910052718 tin Inorganic materials 0.000 claims description 4
- 229910010041 TiAlC Inorganic materials 0.000 claims description 3
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 claims description 2
- 229910015345 MOn Inorganic materials 0.000 claims description 2
- 229910004491 TaAlN Inorganic materials 0.000 claims description 2
- 229910004200 TaSiN Inorganic materials 0.000 claims description 2
- 229910010038 TiAl Inorganic materials 0.000 claims description 2
- 229910010037 TiAlN Inorganic materials 0.000 claims description 2
- 229910008482 TiSiN Inorganic materials 0.000 claims description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 2
- 239000013039 cover film Substances 0.000 claims 2
- 230000006870 function Effects 0.000 abstract description 50
- 239000004065 semiconductor Substances 0.000 abstract description 21
- 239000010410 layer Substances 0.000 description 380
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 18
- 230000004888 barrier function Effects 0.000 description 14
- 238000005516 engineering process Methods 0.000 description 12
- 230000008569 process Effects 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000000926 separation method Methods 0.000 description 10
- 239000000377 silicon dioxide Substances 0.000 description 9
- 230000003647 oxidation Effects 0.000 description 8
- 238000007254 oxidation reaction Methods 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 230000005611 electricity Effects 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000005137 deposition process Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 238000002513 implantation Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 3
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910010271 silicon carbide Inorganic materials 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 208000027418 Wounds and injury Diseases 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052593 corundum Inorganic materials 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 208000014674 injury Diseases 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000007334 memory performance Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000000101 transmission high energy electron diffraction Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
Abstract
A kind of method of improvement SRAM performances, including：P-type workfunction layer is formed on p-type logic device area gate dielectric layer surface, the maximum P-type workfunction layer of equivalent work function value is the first P-type workfunction layer；Pull-up work-function layer is formed on the gate dielectric layer surface in the area that pulls up transistor, the material and thickness for pulling up work-function layer are identical with the material and thickness of the first P-type workfunction layer；Substrate to the area that pulls up transistor carries out first threshold voltage regulation doping treatment；N-type workfunction layer is formed on N-type logic device area gate dielectric layer surface, and the maximum N-type workfunction layer of equivalent work function value is the first N-type workfunction layer；Transmission gate work-function layer is formed on the gate dielectric layer surface of transmission gate transistor area, transmission gate work-function layer is identical with the material and thickness of the first N-type workfunction layer；Substrate to transmission gate transistor area carries out second threshold voltage regulation doping treatment.The present invention improves the write-in redundancy of memory, improves the overall performance of semiconductor devices.
Description
Technical field
The present invention relates to semiconductor fabrication techniques field, more particularly to a kind of method of improvement SRAM performances.
Background technology
In current semiconductor industry, IC products can be divided mainly into three major types type：Logic, deposit
Reservoir and analog circuit, wherein memory device account for sizable ratio in IC products.With
Semiconductor technology develop, memory device is more widely applied, it is necessary to by the memory device with
Other device regions are formed on a single die, to form embedded semiconductor storing equipment simultaneously.For example will
Central processing unit is embedded in the memory device, then it is required that the memory device and embedded center
Processor platform carries out compatibility, and keeps the specification and corresponding electric property of original memory device.
Usually, it is necessary to the memory device and embedded standard logical devices be carried out compatible.For embedding
Enter for formula semiconductor devices, it is generally divided into logic area and memory block, logic area generally includes logic device
Part, memory block then includes memory device.With the development of memory technology, occur in that and various types of partly lead
Body memory, such as static random random access memory (SRAM, Static Random Access Memory),
Dynamic RAM (DRAM, Dynamic Random Access Memory), erasable compile
Journey read-only storage (EPROM, Erasable Programmable Read-Only Memory), electricity can
Erasable programmable read-only memory (EPROM) (EEPROM, Electrically Erasable Programmable
) and flash memory (Flash) Read-Only.Because SRAM has low-power consumption and very fast work speed
The advantages of spending so that SRAM and forming method thereof is received more and more attention.
However, the performance of SRAM needs further in the semiconductor devices of prior art formation
Improve so that the overall performance of semiconductor devices is poor.
The content of the invention
The problem that the present invention is solved is to provide a kind of method of improvement SRAM performances, improves writing for memory
Enter redundancy, so as to improve the overall performance of the semiconductor devices of formation.
To solve the above problems, the present invention provides a kind of method of improvement SRAM performances, including：There is provided
Substrate, the substrate include N-type logic device area, p-type logic device area, pull up transistor area and
Transmission gate transistor area, wherein, the N-type logic device area includes several N-type threshold voltage areas,
The p-type logic device area includes several p-type threshold voltage areas, the N-type logic device area, P
Type logic device area, the part of substrate surface of pull up transistor area and transmission gate transistor area are formed with grid
Dielectric layer；P-type workfunction layer is formed on the p-type logic device area gate dielectric layer surface, and if described
The equivalent work function value of the corresponding P-type workfunction layer in Gan GePXing threshold voltages area is different, wherein, it is equivalent
The maximum P-type workfunction layer of work function value is the first P-type workfunction layer；In the area that pulls up transistor
Gate dielectric layer surface forms pull-up work-function layer, and the material and thickness and a P for pulling up work-function layer
The material of type work-function layer is identical with thickness；Substrate to the area that pulls up transistor carries out first threshold electricity
Pressure regulation doping treatment；N-type workfunction layer is formed on the N-type logic device area gate dielectric layer surface,
And the equivalent work function value of several corresponding N-type workfunction layers in N-type threshold voltage area is different, its
In, the maximum N-type workfunction layer of equivalent work function value is the first N-type workfunction layer；In the transmission gate
The gate dielectric layer surface of transistor area forms transmission gate work-function layer, and the transmission gate work-function layer material
Material and thickness are identical with the material and thickness of the first N-type workfunction layer；To the transmission gate transistor area
Substrate carries out second threshold voltage regulation doping treatment；In the N-type workfunction layer surface, p-type work content
Number layer surface, transmission gate work-function layer surface and pull-up work-function layer surface form gate electrode layer.
Optionally, in described several corresponding P-type workfunction layers in p-type threshold voltage area, described
The thickness of one P-type workfunction layer is most thick；In described several corresponding N-type work contents in N-type threshold voltage area
In several layers, the thickness of first N-type workfunction layer is most thin.
Optionally, in the processing step along with, pull-up work-function layer and the first p-type work content are formed
Several layers；In the processing step along with, the transmission gate work-function layer and the first N-type workfunction layer are formed.
Optionally, the Doped ions of the second threshold voltage regulation doping treatment are B, and doping concentration is
1E12atom/cm3To 1E14atom/cm3。
Optionally, the Doped ions of the first threshold voltage doping treatment are As, and doping concentration is
1E12atom/cm3To 1E14atom/cm3。
Compared with prior art, technical scheme has advantages below：
In the technical scheme of the method for the improvement SRAM performances that the present invention is provided, in p-type logic device area
Gate dielectric layer surface forms P-type workfunction layer, and described several corresponding p-types in p-type threshold voltage area
The equivalent work function value of work-function layer is different, wherein, the maximum P-type workfunction layer of equivalent work function value is
First P-type workfunction layer；Pull-up work-function layer is formed on the gate dielectric layer surface in the area that pulls up transistor, and
The material and thickness of the pull-up work-function layer are identical with the material and thickness of the first P-type workfunction layer.
That is, equivalent work function value and some P-type workfunction layers of the pull-up work-function layer in the area that pulls up transistor
Equivalent work function value in maximum equivalent work function value it is identical, fixed for the holding that makes to pull up transistor has
Threshold voltage numerical value, the substrate in the area that pulls up transistor is carried out at first threshold voltage regulation doping
The Doped ions concentration of reason is higher, and then causes the saturation current for pulling up transistor and ON state current that are formed
It is smaller.N-type workfunction layer, and described several N are formed on N-type logic device area gate dielectric layer surface
The equivalent work function value of the corresponding N-type workfunction layer in type threshold voltage area is different, wherein, equivalent work function
It is the first N-type workfunction layer to be worth maximum N-type workfunction layer；In the gate dielectric layer of transmission gate transistor area
Surface formed transmission gate work-function layer, and the transmission gate work-function layer material and thickness and the first N-type
The material of work-function layer is identical with thickness.That is, the transmission gate work-function layer of transmission gate transistor area
Equivalent work function value and the equivalent work function value of some N-type workfunction layers in maximum equivalent work function value
It is identical, in order that transmission gate transistor keeps having fixed threshold voltage numerical value, it is brilliant to the transmission gate
The Doped ions concentration of the second threshold voltage regulation doping treatment that the substrate in body area under control is carried out is relatively low, and then
So that the saturation current and ON state current of the transmission gate transistor for being formed are larger.Therefore the half of present invention formation
The gamma ratio of memory is improved in conductor device, so that the write-in redundancy of memory is changed
It is apt to, and then improves the electric property of the memory for being formed, improves the overall performance of semiconductor devices.
Brief description of the drawings
Fig. 1 to Figure 15 shows for the cross-section structure of the semiconductor devices forming process that one embodiment of the invention is provided
It is intended to.
Specific embodiment
From background technology, the property of SRAM in the semiconductor devices for being formed in the prior art
Can have much room for improvement.
For SRAM, its mainly include pull-up (PU, Pull Up) transistor, it is drop-down (PD,
Pull Down) transistor and transmission gate (PG, Pass Gate) transistor, and the write-in of memory is superfluous
Remaining (write margin) plays a key effect to memory performance, if the write-in of memory can be improved
Redundancy performance, then the yield of memory will be enhanced, the overall performance of semiconductor devices is accordingly obtained
Improve.Research discovery, write-in redundancy and gamma ratio (gamma ratio) pass in direct ratio of memory
System, gamma is than the ratio between the ON state current for transmission gate transistor and the ON state current for pulling up transistor.
The ON state current of transmission gate transistor is relevant with the Doped ions concentration of transmission gate transistor channel region, transmission
The Doped ions concentration of door transistor channel region is lower, then the ON state current of transmission gate transistor is bigger；On
The ON state current of pull transistor is relevant with the Doped ions concentration of the channel region that pulls up transistor, and pulls up transistor
The Doped ions concentration of channel region is higher, then the ON state current for pulling up transistor is smaller.Therefore, reduce and pass
Send the Doped ions concentration of a transistor channel region, or the Doped ions for improving the channel region that pulls up transistor
Concentration, enables to the gamma of memory than increasing, and then improves the write-in redundancy of memory, improves
The yield of memory.
Further study show that, for transmission gate transistor, transmission gate transistor is NMOS tube,
The transmission gate transistor typically has fixed threshold voltage value (Vt), if forming transmission gate transistor
When employ equivalent work function value (equal work function) work-function layer higher, in order that transmission
Door transistor keeps fixed threshold voltage, then the threshold voltage adjustments of corresponding transmission gate transistor channel region
Doped ions concentration is relatively low so that the ON state current of transmission gate transistor increases.For pulling up transistor and
Speech, it is PMOS to pull up transistor, and described pulling up transistor typically also has fixed threshold voltage, if
Equivalent work function value work-function layer higher is employed when being formed and being pulled up transistor, then in order that upper crystal pulling
Body pipe keeps fixed threshold voltage, the threshold voltage adjustments Doped ions of the channel region that pulls up transistor
Concentration should be higher so that the ON state current for pulling up transistor reduces.
Therefore, the present invention provides a kind of method of improvement SRAM performances, pull up transistor area in the present invention
The equivalent work function value of pull-up work-function layer be：In p-type logic device area some P-type workfunction layers etc.
Maximum equivalent work function value in effect work function value, keeps having fixed threshold value electricity to make to pull up transistor
Pressure numerical value, the substrate to the area that pulls up transistor carries out the doping that first threshold voltage adjusts doping treatment
Ion concentration is higher, and then causes that the saturation current for pulling up transistor and ON state current of formation are smaller；Pass
The equivalent work function value for sending the transmission gate work-function layer of a transistor area is：Some N in N-type logic device area
Maximum equivalent work function value in the equivalent work function value of type work-function layer, in order that transmission gate transistor is protected
Hold with fixed threshold voltage numerical value, the Second Threshold carried out to the substrate of the transmission gate transistor area
The Doped ions concentration of voltage-regulation doping treatment is relatively low, and then causes satisfying for the transmission gate transistor for being formed
It is larger with electric current and ON state current.Therefore the gamma of memory is compared in the semiconductor devices that the present invention is formed
To raising, so that the write-in redundancy of memory is improved, and then the memory for being formed is improved
Electric property, improves the overall performance of semiconductor devices.
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
Specific embodiment of the invention is described in detail.
Fig. 1 to Figure 15 shows for the cross-section structure of the semiconductor devices forming process that one embodiment of the invention is provided
It is intended to.
With reference to Fig. 1, there is provided substrate, the substrate includes that N-type logic device area (sign), p-type are patrolled
Collect device region (sign), pull up transistor area I and transmission gate transistor area II.
The semiconductor devices that the present embodiment is formed includes logical device and SRAM device.The N-type is patrolled
Collect device region and provide technique platform to be subsequently formed N-type logical device, after the p-type logic device area is
The continuous p-type logical device that formed provides technique platform, described to pull up transistor area I to be subsequently formed crystal pulling
Pipe provides technique platform, and the transmission gate transistor area II provides technique to be subsequently formed transmission gate transistor
Platform.For PMOS area, the transmission gate transistor area II is NMOS to the area I that pulls up transistor
Region.
The substrate also includes pull-down transistor area III, and the pull-down transistor area III is drop-down to be subsequently formed
Transistor provides technique platform, and the pull-down transistor area III is NMOS area.Wherein, the pull-up
Transistor area I, transmission gate transistor area II and pull-down transistor area III are memory block, to be subsequently formed
SRAM provides technique platform.
The p-type logic device area includes several p-type threshold voltage areas, wherein, the p-type threshold value
Voltage zone includes p-type ultralow threshold value voltage zone (ULVT, Ultra-low VT) 11, p-type level threshold value electricity
Nip (Standard VT) 12 and p-type high threshold voltage (High VT) area 13, each region is formed
P-type logical device threshold voltage being ordered as from low to high：P-type ultralow threshold value voltage zone 11, P
Type standard threshold voltage area 12, p-type high threshold voltage area 13.The p-type logic device area can also be wrapped
Include p-type low-threshold power nip (not shown), p-type input and output device area (IO, Input Output) (not
Diagram).
The N-type logic device area includes several N-type threshold voltage areas, wherein, the N-type threshold value
Voltage includes N-type ultralow threshold value voltage zone 21, N-type standard threshold voltage area 22 and N-type high threshold
Voltage zone 23, the threshold voltage of the N-type logical device that each region is formed being ordered as from low to high：N-type
Ultralow threshold value voltage zone 21, N-type standard threshold voltage area 22, N-type high threshold voltage area 23.The N
Type logic device area can also include N-type low-threshold power nip (not shown), N-type input and output device area
(not shown).
So that the semiconductor devices for being formed is fin field effect pipe as an example, the substrate includes substrate to the present embodiment
101st, positioned at the discrete fin 102 on the surface of substrate 101.
In another embodiment, the semiconductor devices is planar transistor, and the substrate is planar substrates,
The planar substrates are silicon substrate, germanium substrate, silicon-Germanium substrate or silicon carbide substrates, silicon-on-insulator substrate
Or germanium substrate on insulator, glass substrate or III-V substrate (such as gallium nitride substrate or arsenic
Gallium substrate etc.), grid structure is formed at the plane.
The material of the substrate 101 is silicon, germanium, SiGe, carborundum, GaAs or gallium indium, institute
It can also be the silicon substrate on insulator or the germanium substrate on insulator to state substrate 101；The fin 102
Material include silicon, germanium, SiGe, carborundum, GaAs or gallium indium.It is described in the present embodiment
Substrate 101 is silicon substrate, and the material of the fin 102 is silicon.
In the present embodiment, forming the substrate 101, the processing step of fin 102 includes：Initial lining is provided
Bottom；Patterned hard mask layer 103 is formed in the initial substrate surface；It is with the hard mask layer 103
Initial substrate described in mask etching, the initial substrate after etching as substrate 101, positioned at the surface of substrate 101
Projection as fin 102.
In one embodiment, the processing step for forming the hard mask layer 103 includes：It is initially formed just
Begin hard mask；Patterned photoresist layer is formed in the initial hard mask surface；With described patterned
Photoresist layer is initial hard mask described in mask etching, and hard mask layer 103 is formed in initial substrate surface；Go
Except the patterned photoresist layer.
In other embodiments, the formation process of the hard mask layer can also include：Autoregistration double picture
Shape (SADP, Self-aligned Double Patterned) technique, autoregistration are triple graphical
(Self-aligned Triple Patterned) technique or graphical (the Self-aligned Double of autoregistration quadruple
Double Patterned) technique.The Dual graphing technique includes LELE
(Litho-Etch-Litho-Etch) technique or LLE (Litho-Litho-Etch) technique.
In the present embodiment, after the fin 102 is formed, retain positioned at the top surface of fin 102
Hard mask layer 103.The material of the hard mask layer 103 is silicon nitride, subsequently when flatening process is carried out,
The top surface of the hard mask layer 103 can play protection fin as the stop position of flatening process
The effect at 102 tops.In the present embodiment, the top dimension of the fin 102 is less than bottom size.At it
In his embodiment, the side wall of the fin can also be perpendicular with substrate surface, i.e. the top dimension of fin
Equal to bottom size.
With reference to Fig. 2, the barrier film 104 on the covering surface of substrate 101 and the surface of fin 102 is formed,
The top of the barrier film 104 is higher than the top of hard mask layer 103.
Before the barrier film 104 is formed, also including step：To the substrate 101 and fin 102
Oxidation processes are carried out, liner oxidation layer is formed on the surface of the substrate 101 and the surface of fin 102.
The barrier film 104 provides Process ba- sis to be subsequently formed separation layer；The material of the barrier film 104
Expect to be insulating materials, for example, silica, silicon nitride or silicon oxynitride.In the present embodiment, the isolation
The material of film 104 is silica.
Filling perforation (gap-filling) ability that the technique of barrier film 104 is formed to improve, using mobility
Vapour deposition (FCVD, Flowable CVD) or vertical width high are learned than chemical vapor deposition method (HARP
CVD), the barrier film 104 is formed.
After the barrier film 104 is formed, also including step：The barrier film 104 is annealed
Treatment, improves the consistency of the barrier film 104.
With reference to Fig. 3, the barrier film 104 (referring to Fig. 2) for removing segment thickness forms separation layer 114, institute
Separation layer 114 is stated positioned at the surface of substrate 101 and covering fin 102 partial sidewall surface, the separation layer
114 tops are less than the top of fin 102.
The material of the separation layer 114 is silica, silicon nitride or silicon oxynitride.In the present embodiment, institute
The material for stating separation layer 114 is silica.
In one embodiment, using dry etch process, the barrier film 104 of etching removal segment thickness.
In another embodiment, using wet-etching technology, the barrier film 104 of etching removal segment thickness.
Also include step：The etching removal hard mask layer 103 (referring to Fig. 2).Step can also be included：
Screen layer, the screen are formed at the top of the fin 102 and sidewall surfaces and the surface of separation layer 114
The material of layer is covered for silica or silicon oxynitride, its role is to：During follow-up doping treatment,
The screen layer can reduce the lattice damage that doping treatment is caused to fin 102.
Also include step：N-type well region is carried out to the p-type logic device area and the area I that pulls up transistor
Doping treatment, N-type trap is formed in the p-type logic device area and the substrate for pulling up transistor area I
Area；P is carried out to the N-type logic device area, transmission gate transistor area II and pull-down transistor area III
Type well region doping treatment, in the N-type logic device area, transmission gate transistor area II and lower crystal pulling
P type trap zone is formed in the substrate of area under control III.
With reference to Fig. 4, the substrate to the area I that pulls up transistor carries out first threshold voltage regulation doping treatment.
In the present embodiment, the area I that pulls up transistor for PMOS area, adjust by the first threshold voltage
The Doped ions for saving doping treatment are N-type ion, and N-type ion is P, As or Sb.The first threshold
Voltage-regulation doping treatment is actually to the channel region below the grid structure that pulls up transistor that is subsequently formed
The doping for carrying out, in the present embodiment, the fin 102 to the area I that pulls up transistor carries out first threshold voltage tune
Section doping treatment.
Substrate to the area I that pulls up transistor carries out the technique step of first threshold voltage regulation doping treatment
Suddenly include：The first graph layer 105 is formed on the surface of the separation layer 114 and the surface of fin 102, it is described
First graph layer 105 exposes the area's I substrate surfaces that pull up transistor；It is to cover with first graph layer 105
Film, the fin 102 to the area I that pulls up transistor carries out N-type ion implanting；Then, remove described
First graph layer 105.
In the present embodiment, subsequently pull up transistor in area's I substrates formed the equivalent work content of pull-up work-function layer
Numerical value is higher, specifically, rear extended meeting forms the different P of equivalent work function value in GePXing threshold voltages area
Type work-function layer, wherein, the maximum P-type workfunction layer of equivalent work function value is the first P-type workfunction layer,
And the pull-up work-function layer being subsequently formed in the present embodiment is equal with the material and thickness of the first P-type workfunction layer
It is identical.Therefore for pulling up transistor, the equivalent work function of the middle pull-up work-function layer that pulls up transistor
Value is larger, in order that what is formed pulls up transistor with fixed threshold voltage, to pull-up in the present embodiment
The Doped ions concentration of the first threshold voltage regulation doping treatment that transistor area I substrates are carried out should be higher.This
In embodiment, the Doped ions of the first threshold voltage doping treatment are As, and doping concentration is
1E12atom/cm3To 1E14atom/cm3。
With mixing for the threshold voltage adjustments doping treatment for being carried out to the substrate in the area that pulls up transistor in the prior art
Miscellaneous concentration is compared, and the first threshold voltage regulation carried out to the area I substrates that pull up transistor in the present embodiment is mixed
The Doped ions concentration for living together reason is higher, it is also possible to think, pull up transistor area's I channel regions in the present embodiment
Doped ions concentration it is higher, therefore the saturation current for pulling up transistor that is correspondingly formed of the present embodiment and open
State electric current is lower so that pulling up transistor for formation has lower operating current.
In a specific embodiment, the first threshold voltage regulation is carried out using ion implantation technology to mix
Reason is lived together, the technological parameter of the first threshold voltage regulation doping treatment includes：Injection ion is As,
Implantation Energy is 5kev to 15kev, and implantation dosage is 1E12atom/cm2To 1E14atom/cm2, injection
Angle is 0 degree to 15 degree, and twist angles are 23 degree, and injection number of times is 4 times.
Also include step：The p-type logic device area substrate is carried out at N-type threshold voltage adjustments doping
Reason.Specifically, to the p-type ultralow threshold value voltage zone 11, p-type standard threshold voltage area 12 and P
The substrate in type high threshold voltage area 13 carries out N-type threshold voltage adjustments doping treatment.According to several p-types
Threshold voltage ranges needed for the device that threshold voltage area is formed, it is determined that carrying out N to GePXing threshold voltages area
The doping concentration of type threshold voltage adjustments doping treatment.In the present embodiment, to p-type ultralow threshold value electricity
The N-type threshold value that nip 11, p-type standard threshold voltage area 12 and p-type high threshold voltage area 13 are carried out
The doping concentration of voltage-regulation doping treatment is differed.
With reference to Fig. 5, the substrate to the transmission gate transistor area II carries out second threshold voltage regulation doping
Treatment.
In the present embodiment, the transmission gate transistor area II is NMOS area, the second threshold voltage
The Doped ions for adjusting doping treatment are p-type ion, and p-type ion is B, Ga or In.Second threshold
Value regulation doping treatment is actually to the channel region below the transmission gate transistor grid structure that is subsequently formed
The doping for carrying out, in the present embodiment, the fin 102 to transmission gate transistor area II carries out Second Threshold electricity
Pressure regulation doping treatment.
Substrate to the transmission gate transistor area II carries out the technique that second threshold voltage adjusts doping treatment
Step includes：Second graph layer 106, institute are formed on the surface of the separation layer 114 and the surface of fin 102
State the substrate surface that second graph layer 106 exposes transmission gate transistor area II；With second graph layer
106 is mask, and the fin 102 to the transmission gate transistor area II carries out p-type ion implanting；Then,
Remove the second graph layer 106.
In the present embodiment, the transmission gate work content for subsequently being formed on transmission gate transistor area II gate dielectric layers surface
Several layers of equivalent work function value are higher, specifically, rear extended meeting forms equivalent work content in GeNXing threshold voltages area
The different N-type workfunction layer of numerical value, wherein, the maximum N-type workfunction layer of equivalent work function value is first
N-type workfunction layer, and the transmission gate work-function layer being subsequently formed in the present embodiment and the first N-type work function
The material and thickness all same of layer.
Therefore for transmission gate transistor, transmission gate work-function layer is equivalent in transmission gate transistor
Work function value is larger, in order that the transmission gate transistor for being formed has fixed threshold voltage, the present embodiment
In transmission gate transistor area II substrates are carried out second threshold voltage regulation doping treatment Doped ions it is dense
Degree should be relatively low.In the present embodiment, the Doped ions of the second threshold voltage regulation doping treatment are B,
Doping concentration is 1E12atom/cm3To 1E14atom/cm3。
With the threshold voltage adjustments doping treatment for being carried out to the substrate of transmission gate transistor area in the prior art
Doping concentration compares, the second threshold voltage carried out to transmission gate transistor area II substrates in the present embodiment
The Doped ions concentration for adjusting doping treatment is lower, it is also possible to think, transmission gate transistor in the present embodiment
The Doped ions concentration of area's II channel regions is lower, therefore the transmission gate transistor that is correspondingly formed of the present embodiment
Saturation current and ON state current are lower so that the transmission gate transistor of formation has lower operating current.
In a specific embodiment, the second threshold voltage regulation is carried out using ion implantation technology to mix
Reason is lived together, the technological parameter of the second threshold voltage regulation doping treatment includes：Injection ion is B,
Implantation Energy is 2kev to 5kev, and implantation dosage is 1E12atom/cm2To 1E14atom/cm2, injection
Angle is 0 degree to 15 degree, and injection twist angles are 23 degree, and injection number of times is 4 times.
Also include step：Substrate to the pull-down transistor area III carries out the doping of the 3rd threshold voltage adjustments
Treatment, the Doped ions of the 3rd threshold voltage adjustments doping treatment are p-type ion；To the N-type
Logic device area substrate carries out p-type threshold voltage adjustments doping treatment.Specifically, ultralow to the N-type
The base in threshold voltage adjustments area 21, N-type standard threshold voltage area 22 and N-type high threshold voltage area 23
Bottom carries out p-type threshold voltage adjustments doping treatment.According to the device that several N-type threshold voltage areas are formed
Required threshold voltage ranges, it is determined that carrying out p-type threshold voltage adjustments doping to GeNXing threshold voltages area
The doping concentration for the treatment of.In the present embodiment, to the N-type ultralow threshold value voltage zone 21, N-type standard threshold
The p-type threshold voltage adjustments doping treatment that threshold voltage area 22 and N-type high threshold voltage area 23 are carried out
Doping concentration is differed.
Extended meeting afterwards forms grid structure in substrate surface, in this implementation, with using rear grid technique (gate last)
Grid structure is formed as an example, forming grid after source-drain area (S/D, Source/Drain) is formed
Structure.In other embodiments, additionally it is possible to which grid structure is formed using first grid technique (gate first), exist
Grid structure is formed before forming source-drain area.
With reference to Fig. 6, the area I that pulls up transistor, p-type logic device area, N-type logic device area,
Transmission gate transistor area II and pull-down transistor area II substrate surfaces form pseudo- oxide-film；In the pseudo- oxygen
Change film surface and form pseudo- grid film；The graphical pseudo- grid film and pseudo- oxide-film, form and are located at N-type logic
Device region, p-type logic device area, the area I that pulls up transistor, transmission gate transistor area II and lower crystal pulling
The pseudo- oxide layer 201 on area under control III part of substrate surface, forms the pseudo- gate layer 202 positioned at the surface of oxide layer 201.
The pseudo- gate layer 202 occupies the locus of the grid structure being subsequently formed.The pseudo- oxide layer 201
Material be silica or silicon oxynitride, the material of the pseudo- gate layer 202 is polysilicon, non-crystalline silicon or nothing
Setting carbon.In the present embodiment, the material of the pseudo- oxide layer 201 is silica, the pseudo- gate layer 202
Material be polysilicon.
Also include step：Offset side wall is formed in the sidewall surfaces of pseudo- gate layer 202；To the pseudo- gate layer
The N-type logic device area fin 102 of 202 both sides carries out that treatment is lightly doped, and forms N-type LDD region domain,
In the present embodiment, including the fin 102 in N-type logic device area Zhong GeNXing threshold voltages area is carried out gently
Doping treatment；P-type logic device area fin 102 to the both sides of pseudo- gate layer 202 carries out that place is lightly doped
Reason, forms p-type LDD region domain, in the present embodiment, including to each p-type threshold value in p-type logic device area
The fin 102 of voltage zone carries out that treatment is lightly doped；To the area I that pulls up transistor of the both sides of pseudo- gate layer 202
Fin 102 carries out that treatment is lightly doped, and forms pull-up LDD region domain；To the biography of the both sides of pseudo- gate layer 202
Sending transistor area II fin 102 carries out that treatment is lightly doped, and forms transmission gate LDD region domain；To the puppet
The pull-down transistor area III fins 102 of the both sides of gate layer 202 carry out that treatment is lightly doped, and form drop-down LDD
Region.
Also include step：Master wall is formed in the offset side wall sidewall surfaces；To the pseudo- gate layer 202
The N-type logic device area fin 102 of both sides carries out heavy doping treatment, forms N-type S/D regions, this reality
In applying example, including heavy doping is carried out to the fin 102 in N-type logic device area Zhong GeNXing threshold voltages area
Treatment；P-type logic device area fin 102 to the both sides of pseudo- gate layer 202 carries out heavy doping treatment,
P-type S/D regions are formed, in the present embodiment, including to each p-type threshold voltage in p-type logic device area
The fin 102 in area carries out heavy doping treatment；To the area's I fins that pull up transistor of the both sides of pseudo- gate layer 202
102 carry out heavy doping treatment, form pull-up S/D regions；Transmission gate to the both sides of pseudo- gate layer 202 is brilliant
Body area under control domain II fin 102 carries out heavy doping treatment, forms transmission gate S/D regions；To the pseudo- gate layer
The pull-down transistor area III fins 102 of 202 both sides carry out heavy doping treatment, form drop-down S/D regions.
With reference to Fig. 7, the pseudo- gate layer 202 (referring to Fig. 6) and pseudo- oxide layer 201 (referring to Fig. 6) are removed.
Before the pseudo- gate layer 202 is removed, also including step：Interlayer is formed in the substrate surface to be situated between
Matter layer (not shown), the sidewall surfaces of the pseudo- gate layer 202 of interlayer dielectric layer covering.
Using dry etch process, wet-etching technology or SiCoNi etching systems, the etching removal puppet
Gate layer 202 and pseudo- oxide layer 201.In the technical process for removing the pseudo- gate layer 202, the pseudo- oxidation
Layer 201 plays a part of to protect fin 102.
Then, with reference to Fig. 8, in the N-type logic device area, p-type logic device area, pull up transistor
Area I, transmission gate transistor area II and pull-down transistor area III substrate surfaces form boundary layer 204.
The boundary layer 204 as the gate dielectric layer being subsequently formed a part, the boundary layer 204
Material is silica or silicon oxynitride.In the present embodiment, the boundary layer 204 is formed using oxidation technology,
The oxidation technology is dry-oxygen oxidation, wet-oxygen oxidation or steam oxidation, and the boundary layer 204 of formation is only located at
The top surface of fin 102 and sidewall surfaces for exposing.
In other embodiments, the boundary layer is formed using depositing operation, the depositing operation is chemistry
Vapour deposition, physical vapour deposition (PVD) or ald, the boundary layer of formation are also located at insulation surface.
With continued reference to Fig. 8, high-k gate dielectric layer 205 is formed on the surface of the boundary layer 204.
In the present embodiment, the high-k gate dielectric layer 205 is also located at the surface of separation layer 114 and interlayer is situated between
Matter layer (not shown) sidewall surfaces.The material of the high-k gate dielectric layer 205 is high-k gate dielectric material,
Wherein, high-k gate dielectric material refers to grid of the relative dielectric constant more than silica relative dielectric constant
Dielectric material, the material of the high-k gate dielectric layer 205 is HfO2、HfSiO、HfSiON、HfTaO、
HfTiO、HfZrO、ZrO2Or Al2O3。
The k grid high are formed using chemical vapor deposition, physical vapour deposition (PVD) or atom layer deposition process to be situated between
Matter layer 205.In the present embodiment, the material of the high-k gate dielectric layer 205 is HfO2, the k grid high
The thickness of dielectric layer 205 is 5 angstroms to 15 angstroms, and the high-k gate dielectric is formed using atom layer deposition process
Layer 205.
The lamination knot of the boundary layer 204 and the high-k gate dielectric layer 205 positioned at the surface of boundary layer 204
Structure the N-type logic device area, p-type logic device area, pulls up transistor as gate dielectric layer
Area I, transmission gate transistor area II and pull-down transistor area III substrate surfaces are formed with gate dielectric layer.Tool
, in the present embodiment, the gate dielectric layer is across fin 102, and covering fin 102 atop part surface for body
And sidewall surfaces.
It is follow-up also to form N-type workfunction layer on N-type logic device area gate dielectric layer surface, patrolled in p-type
Collect device region gate dielectric layer surface and form P-type workfunction layer.The present embodiment will be being initially formed p-type logic device
The P-type workfunction layer in part area, the rear N-type workfunction layer for forming N-type logic device area are carried out as an example
Describe in detail.In other embodiments, additionally it is possible to be initially formed N-type logic device area N-type workfunction layer,
The P-type workfunction layer of p-type logic device area is formed afterwards.
With reference to Fig. 9, P-type workfunction layer 208 is formed on the p-type logic device area gate dielectric layer surface.
In the present embodiment, the P-type workfunction layer of formation is also located at the area I gate dielectric layer tables that pull up transistor
Face, the P-type workfunction layer 208 be also located at N-type logic device area, transmission gate transistor area II and
The gate dielectric layer surface of pull-down transistor area III.
Before the P-type workfunction layer 208 is formed, also including step：In the high-k gate dielectric layer
205 surfaces form cap (not shown)；Etching stop layer (not shown) is formed in the block layer surface.
The cap plays a part of to protect high-k gate dielectric layer 205, prevents follow-up etching technics pair
High-k gate dielectric layer 205 causes unnecessary etching to lose, the cap also help barrier metal from
Son spreads in high-k gate dielectric layer 205.The material of the cap is TiN；Using chemical vapor deposition
Technique, physical gas-phase deposition or atom layer deposition process form the cap.
The etching stop layer and the P-type workfunction layer 208 for being formed and the N-type work function being subsequently formed
The material of layer is different, so that the etching technics of subsequent etching P-type workfunction layer 208 is to etching stopping
The etch rate of layer is small, and the etching technics of subsequent etching N-type workfunction layer is fast to the etching of etching stop layer
Rate is small, so as to avoid causing etching injury to high-k gate dielectric layer 205.In the present embodiment, the etching
The material of stop-layer is TaN, and the etching stop layer is formed using atom layer deposition process.
The material of the P-type workfunction layer 208 is the one kind or several in Ta, TiN, TaSiN or TiSiN
Kind.The P is formed using chemical vapor deposition method, physical gas-phase deposition or atom layer deposition process
Type work-function layer 208.
In the present embodiment, the material of the P-type workfunction layer 208 is TiN, the P-type workfunction layer
208 have the 3rd thickness, and the 3rd thickness is 45 angstroms to 55 angstroms, for example, 50 angstroms.
In the present embodiment, because p-type logic device area includes p-type ultralow threshold value voltage zone 11, p-type mark
Quasi- threshold voltage area 12 and p-type high threshold voltage area, in order to meet device requirement, p-type logical device
Difference between the threshold voltage of the device that each region in area is formed is larger, only relies on the foregoing p-type threshold for carrying out
Threshold voltage regulation doping treatment is difficult to obtain the threshold voltage of larger difference.Therefore, the present embodiment subsequently enters
One step is performed etching to the P-type workfunction layer 208 in p-type high threshold voltage area 13, thinning p-type high threshold
The P-type workfunction layer 208 of voltage zone 13, so that the p-type work content in p-type high threshold voltage area 13
Several layers of equivalent work function value reduces, and then further increases the device that p-type high threshold voltage area 13 is formed
Threshold voltage numerical value, so that between the threshold voltage of the device of each region formation of p-type logic device area
Difference it is larger.
With reference to Figure 10, the second mask layer 209 is formed on the surface of the P-type workfunction layer 208, described the
Two mask layers expose the surface of P-type workfunction layer 208 in p-type high threshold voltage area 13；With described second
Mask layer 209 is mask, p-type work(of the etching removal positioned at the second thickness in p-type high threshold voltage area 13
Function layer 208.
Second mask layer 209 also covers the surface of P-type workfunction layer 208 of the area I that pulls up transistor, also
Positioned at the p-type work function of transmission gate transistor area II, N-type logic device area and pull-down transistor area III
208 surface of layer.In other embodiments, second mask layer also exposes transmission gate transistor, N
Type logic device area and the P-type workfunction layer surface in pull-down transistor area so that subsequently remove transmission gate
The technique duration of the P-type workfunction layer of transistor, N-type logic device area and pull-down transistor area is shorter.
In the present embodiment, the material of second mask layer 209 is Other substrate materials.In other embodiment
In, the material of second mask layer can also be silicon nitride or boron nitride.
Using dry etch process, wet-etching technology or SiCoNi etching systems, etching removal p-type is high
The P-type workfunction layer 208 of the second thickness in threshold voltage area 13.
After the completion of etching technics, described several corresponding P-type workfunction layers 208 in p-type threshold voltage area
Equivalent work function value it is different, wherein, the maximum P-type workfunction layer 208 of equivalent work function value is a P
Type work-function layer 218, therefore, the P-type workfunction layer 208 not being etched in p-type logic device area is the
One P-type workfunction layer 218, specific to the present embodiment in, the correspondence of p-type ultralow threshold value voltage zone 11
P-type workfunction layer 208 be the first P-type workfunction layer 218.In described several p-type threshold voltages
In the corresponding P-type workfunction layer 208 in area, the thickness of first P-type workfunction layer 218 is most thick.
The surface of P-type workfunction layer 208 of the area I that pulls up transistor also is covered due to the second mask layer 209, is made
The P-type workfunction layer 208 of area I of must pulling up transistor is not etched yet, and the area I that pulls up transistor is not etched
P-type workfunction layer 208 for pull-up work-function layer 228.Therefore, in the present embodiment, the crystal pulling on described
The gate dielectric layer surface of body area under control I forms pull-up work-function layer 228, and the pull-up work-function layer 228 with
The material of the first P-type workfunction layer 218 is identical with thickness.And the present embodiment is in the processing step along with
The pull-up P-type workfunction layer 218 of work-function layer 228 and first is formed, without to form the pull-up
Work-function layer 228 and use extra light shield.
In the present embodiment, the thickness of first P-type workfunction layer 218 is 45 angstroms to 55 angstroms, for example
It is 50 angstroms；The thickness of the pull-up work-function layer 228 of the area I that pulls up transistor is 45 angstroms to 55 angstroms,
For example, 50 angstroms；The thickness of the P-type workfunction layer 208 after being etched is 25 angstroms to 35 angstroms, for example,
30 angstroms, i.e. in the p-type logic device area, in addition to first P-type workfunction layer 218
The thickness of P-type workfunction layer 208 is 25 angstroms to 35 angstroms.
In the present embodiment, due to the equivalent work function value choosing of the pull-up work-function layer 228 of the area I that pulls up transistor
What is taken is：The maximum equivalent work function value of corresponding several P-type workfunction layers in p-type logic device area,
Therefore, in order that pulling up transistor with fixed threshold voltage for the area I formation that pulls up transistor, foregoing right
The doping concentration of the first threshold voltage regulation doping treatment that the area I substrates that pull up transistor are carried out is high so that shape
Into the channel region that pulls up transistor doping concentration it is high, therefore the saturation current that pulls up transistor and ON state electricity
Stream is small.
In other embodiments, additionally it is possible to in p-type logic device area except p-type high threshold voltage area its
The P-type workfunction layer in his p-type threshold voltage area perform etching it is thinning, and to other p-type threshold voltage areas
P-type workfunction layer perform etching thinning thickness and can also differ, it is ensured that in p-type logic device area
The maximum P-type workfunction layer of equivalent work function value is the first P-type workfunction layer, and pulls up work-function layer
Material and thickness are identical with the material and thickness of the first P-type workfunction layer, it is also possible to think, for
For material identical P-type workfunction layer, the most thick P-type workfunction layer of thickness in p-type logic device area
It is the first P-type workfunction layer.
Then, with reference to Figure 11, second mask layer 209 (referring to Figure 10) is removed；Etching removal is located at
The P-type workfunction layer of N-type logic device area, transmission gate transistor area II and pull-down transistor area III
208。
Specifically, in the surface of P-type workfunction layer 208 of the p-type logic device area and upper crystal pulling
The surface of pull-up work-function layer 228 of area under control I forms the 3rd mask layer (not shown), and the 3rd mask is sudden and violent
Expose the p-type work content of N-type logic device area, transmission gate transistor area II and pull-down transistor area III
Several layers of 208 surface；With the 3rd mask layer as mask, etching removal be located at N-type logic device area,
The P-type workfunction layer 208 of transmission gate transistor area II and pull-down transistor area III；Then, institute is removed
State the 3rd mask layer.
In other embodiments, additionally it is possible to which first removal is located at N-type logic device area, transmission gate transistor area
And the P-type workfunction layer in pull-down transistor area, after to the p-type work function of the p-type logic device area
Layer is performed etching.
With reference to Figure 12, N-type workfunction layer 211 is formed on the N-type logic device area gate dielectric layer surface.
In the present embodiment, the N-type workfunction layer 211 of formation is also located at transmission gate transistor area II grid
Dielectric layer surface, the N-type workfunction layer 211 is also located at the surface of P-type workfunction layer 208, a P
The gate medium on the surface of type work-function layer 218, the pull-up surface of work-function layer 228 and pull-down transistor area III
Layer surface.
The material of the N-type workfunction layer 211 be TiAl, TiAlC, TaAlN, TiAlN, MoN,
One or more in TaCN or AlN.Using chemical vapor deposition method, physical gas-phase deposition or
Atom layer deposition process forms the N-type workfunction layer 211.
In the present embodiment, the material of the N-type workfunction layer 211 is TiAlC, the N-type work function
Layer 211 has the 4th thickness, and the 4th thickness is 45 angstroms to 55 angstroms, for example, 50 angstroms.
Because N-type logic device area includes N-type ultralow threshold value voltage zone 21, N-type standard threshold voltage area
22 and N-type high threshold voltage area 23, in order to meet device requirement, each region shape of N-type logic device area
Into device threshold voltage between difference it is larger, only rely on the foregoing N-type threshold voltage adjustments for carrying out and mix
Live together the threshold voltage that reason is difficult to obtain larger difference.
Therefore, the present embodiment is follow-up further to the N-type workfunction layer of N-type high threshold region 23
211 perform etching, the N-type workfunction layer 211 in thinning N-type high threshold voltage area 23, and then further
Increase the device threshold voltage numerical value that N-type high threshold voltage area 23 is formed, so that N-type logic device
Difference between the threshold voltage of the device that each region in part area is formed is larger.
With reference to Figure 13, the first mask layer 212 is formed on the surface of the N-type workfunction layer 211, described the
One mask layer 212 exposes the surface of N-type workfunction layer 211 in N-type high threshold voltage area 23；With institute
It is mask to state the first mask layer 212, and etching removal is positioned at the second thickness in N-type high threshold voltage area 23
N-type workfunction layer 211.
First mask layer 212 also exposes the table of N-type workfunction layer 211 of transmission gate transistor area II
Face, and also cover the N-type of pull up transistor area I, pull-down transistor area III and p-type logic device area
The surface of work-function layer 211.In other embodiments, first mask layer can also expose crystal pulling
The N-type workfunction layer surface in body area under control, pull-down transistor area or p-type logic device area.
In the present embodiment, the material of first mask layer 212 is Other substrate materials.In other embodiment
In, the material of first mask layer can also be silicon nitride or boron nitride.
Using dry etch process, wet-etching technology or SiCoNi etching systems, etching removal N-type is high
The N-type workfunction layer 211 of the first thickness in threshold voltage area 23.
After the completion of etching, several corresponding N-type workfunction layers 211 in N-type threshold voltage area
Equivalent work function value is different, wherein, the maximum N-type workfunction layer 211 of equivalent work function value is a N
Type work-function layer 221, therefore, the N-type workfunction layer 211 after being etched in N-type logic device area is the
One N-type workfunction layer 221.In specific to the present embodiment, the N-type high threshold voltage area 23 is corresponding
N-type workfunction layer 211 is the first N-type workfunction layer 221.In described several N-type threshold voltage areas
In corresponding N-type workfunction layer 211, the thickness of first N-type workfunction layer 221 is most thin.
The table of N-type workfunction layer 211 of transmission gate transistor area II is also exposed due to the first mask layer 212
Face, the N-type workfunction layer 211 of the first thickness in N-type high threshold voltage area 23 is located in etching removal
While, also etching removal is located at the N-type of the first thickness on transmission gate transistor area II gate dielectric layers surface
Work-function layer 211, the N-type workfunction layer 211 after being etched in the II of transmission gate transistor area is transmission gate work(
Function layer 231.
Therefore, in the present embodiment, transmission gate is formed on the transmission gate transistor area II gate dielectric layers surface
Work-function layer 231, and the N-type workfunction layer 221 of the transmission gate work-function layer 231 and first material
It is identical with thickness.And in the present embodiment in the processing step along with, form the transmission gate work-function layer
231 and first N-type workfunction layer 221, without being used to form the transmission gate work-function layer 231
Extra light shield.
In the N-type logic device area, the N-type work(in addition to first N-type workfunction layer 221
The thickness of function layer 211 is 45 angstroms to 55 angstroms, for example, 50 angstroms；First N-type workfunction layer
221 thickness is 25 angstroms to 35 angstroms, for example, 30 angstroms；The thickness of the transmission gate work-function layer 231
It is 25 angstroms to 35 angstroms, for example, 30 angstroms.
In the present embodiment, due to the equivalent work content of the transmission gate work-function layer 231 of transmission gate transistor area II
Numerical value choose be：The maximum equivalent work(of corresponding several N-type workfunction layers in N-type logic device area
Functional value, therefore, in order that the transmission gate transistor that transmission gate transistor area II is formed has fixed threshold
Threshold voltage, the foregoing second threshold voltage regulation doping treatment carried out to transmission gate transistor area II substrates
Doping concentration is low so that the doping concentration of the transmission gate transistor channel region of formation is low, follows transmission gate brilliant
The saturation current and ON state current of body pipe are big.
In other embodiments, additionally it is possible to the N in other N-type threshold voltage areas in N-type logic device area
Type work-function layer performs etching thinning, and N-type workfunction layer to other N-type threshold voltage areas carves
The thinning thickness of erosion can also be differed, it is ensured that the maximum N-type of the equivalent work function value of N-type logic device area
Work-function layer be the first N-type workfunction layer, and transmission gate work-function layer material and thickness and the first N-type
The material of work-function layer is identical with thickness, it is also possible to think, for material identical N-type work function
For layer, the most thin N-type workfunction layer of thickness is the first N-type workfunction layer in N-type logic device area.
Then, with reference to Figure 14, first mask layer 212 (referring to Figure 13) is removed；Removal is located at pull-up
The N-type workfunction layer 211 of transistor area I and p-type logic device area.
Specifically, forming the 4th on the surface of transmission gate work-function layer 231 of the transmission gate transistor area II
Mask layer (not shown), the 4th mask layer also covers the N-type workfunction layer of pull-down transistor area III
211 and the N-type workfunction layer 211 of N-type logic device area；With the 4th mask layer as mask, carve
Etching off is except the N-type workfunction layer 211 for being located at pull up transistor area I and p-type logic device area；Then,
Remove the 4th mask layer.
In other embodiments, moreover it is possible to first remove the N-type work(of pull up transistor area and p-type logic device area
Function layer, then performs etching thinning to the N-type workfunction layer in N-type high threshold voltage area.
In another embodiment, because N-type workfunction layer is to pulling up transistor and p-type logical device
Threshold voltage influence is smaller, therefore can also retain the N in pull up transistor area and p-type logic device area
Type work-function layer.
With reference to Figure 15, on the surface of the N-type workfunction layer 211, the surface of P-type workfunction layer 208, pass
The surface of a work-function layer 231 and pull-up work-function layer 228 surface is sent to form gate electrode layer 301.
In the present embodiment, the P-type workfunction layer 208 is included positioned at p-type ultralow threshold value voltage zone 11
First P-type workfunction layer 218, the N-type workfunction layer 211 includes being located at N-type high threshold voltage area
23 the first N-type workfunction layer 221.The gate electrode layer 301 is also located at the N of pull-down transistor area III
The surface of type work-function layer 211.
Positioned at the surface of N-type workfunction layer 211, the surface of P-type workfunction layer 208, transmission gate work-function layer
The gate electrode layer 301 on 231 surfaces and pull-up work-function layer 228 surface is connected with each other.In other embodiment
In, positioned at N-type workfunction layer surface, P-type workfunction layer surface, transmission gate work-function layer surface and
The gate electrode layer on pull-up work-function layer surface can also be separate.
The material of the gate electrode layer 301 is included in Al, Cu, Ag, Au, Pt, Ni, Ti or W
One or more.
In one embodiment, the processing step for forming the first gate electrode layer 301 includes：Institute
State the surface of N-type workfunction layer 211, the surface of P-type workfunction layer 208, the table of transmission gate work-function layer 231
Face and pull-up work-function layer 228 surface form gate electrode film, and the gate electrode film top is situated between higher than interlayer
Matter layer top；Grinding removal forms the gate electrode layer 301 higher than the gate electrode film at the top of interlayer dielectric layer.
From Such analysis, the present embodiment formed the saturation current for pulling up transistor and ON state current compared with
It is low, and the saturation current and ON state current of the transmission gate transistor for being formed are higher, due to the gamma of memory
Than the ratio pass in direct ratio between transmission gate transistor ON state current and the ON state current that pulls up transistor
System, therefore the gamma of memory that the present embodiment is formed is than larger, and then cause the write-in redundancy of memory
Degree is improved, and the performance of corresponding memory is improved, and the yield of such as memory is improved,
And then improve the performance of the semiconductor devices to be formed.
Also, the present embodiment formed logical device while form memory in pull up transistor,
Pull-down transistor and transmission gate transistor so that the memory of formation is with larger write-in redundancy
Meanwhile, the technique for forming memory is mutually compatible with the technique for forming logical device, saves processing step,
Without introducing extra light shield to improve the write-in redundancy of memory, save semiconductor production into
This.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore guarantor of the invention
Shield scope should be defined by claim limited range.
Claims (20)
1. a kind of method of improvement SRAM performances, it is characterised in that including：
Substrate is provided, the substrate includes N-type logic device area, p-type logic device area, upper crystal pulling
Area under control and transmission gate transistor area, wherein, the N-type logic device area includes several N-type threshold values
Voltage zone, the p-type logic device area includes several p-type threshold voltage areas, the N-type logic device
Part area, p-type logic device area, the part of substrate surface shape of pull up transistor area and transmission gate transistor area
Into there is gate dielectric layer；
P-type workfunction layer, and described several P are formed on the p-type logic device area gate dielectric layer surface
The equivalent work function value of the corresponding P-type workfunction layer in type threshold voltage area is different, wherein, equivalent work function
It is the first P-type workfunction layer to be worth maximum P-type workfunction layer；
Pull-up work-function layer, and the pull-up work(are formed on the gate dielectric layer surface in the area that pulls up transistor
The material and thickness of function layer are identical with the material and thickness of the first P-type workfunction layer；
Substrate to the area that pulls up transistor carries out first threshold voltage regulation doping treatment；
The N-type logic device area gate dielectric layer surface formed N-type workfunction layer, and it is described several
The equivalent work function value of the corresponding N-type workfunction layer in N-type threshold voltage area is different, wherein, equivalent work content
The maximum N-type workfunction layer of numerical value is the first N-type workfunction layer；
Transmission gate work-function layer, and the biography are formed on the gate dielectric layer surface of the transmission gate transistor area
Send the material and thickness of a work-function layer identical with the material and thickness of the first N-type workfunction layer；
Substrate to the transmission gate transistor area carries out second threshold voltage regulation doping treatment；
The N-type workfunction layer surface, P-type workfunction layer surface, transmission gate work-function layer surface with
And pull-up work-function layer surface forms gate electrode layer.
2. the method for improving SRAM performances as claimed in claim 1, it is characterised in that the transmission gate crystal
Area under control is NMOS area；The area that pulls up transistor is for PMOS area.
3. the method for improving SRAM performances as claimed in claim 1, it is characterised in that in described several P
In the corresponding P-type workfunction layer in type threshold voltage area, the thickness of first P-type workfunction layer is most thick；
In described several corresponding N-type workfunction layers in N-type threshold voltage area, the first N-type work(
The thickness of function layer is most thin.
4. the method for improving SRAM performances as claimed in claim 1, it is characterised in that walked in the technique along with
In rapid, pull-up work-function layer and first P-type workfunction layer are formed；In the processing step along with,
Form the transmission gate work-function layer and the first N-type workfunction layer.
5. the method for improving SRAM performances as claimed in claim 1, it is characterised in that the p-type work function
The material of layer is one or more in Ta, TiN, TaSiN or TiSiN；The N-type work function
The material of layer is the one kind in TiAl, TiAlC, TaAlN, TiAlN, MoN, TaCN or AlN
Or it is several.
6. the method for improving SRAM performances as claimed in claim 1, it is characterised in that described several N-types
Threshold voltage area includes N-type ultralow threshold value voltage zone, N-type standard threshold voltage area and N-type threshold high
Threshold voltage area, wherein, the corresponding N-type workfunction layer in the N-type high threshold voltage area is a N
Type work-function layer.
7. the method for improving SRAM performances as claimed in claim 6, it is characterised in that formation includes described the
The processing step of the N-type workfunction layer of one N-type workfunction layer includes：In the N-type logical device
Area gate dielectric layer surface forms N-type workfunction layer；First is formed on the N-type workfunction layer surface to cover
Film layer, first mask layer exposes the N-type workfunction layer surface in N-type high threshold voltage area；With
First mask layer is mask, N of the etching removal positioned at the first thickness in N-type high threshold voltage area
Type work-function layer, the N-type workfunction layer after being etched in N-type logic device area is the first N-type work function
Layer.
8. the method for improving SRAM performances as claimed in claim 6, it is characterised in that the N-type work function
Layer is also located at transmission gate transistor area gate dielectric layer surface；And first mask layer also exposes transmission
The N-type workfunction layer surface of door transistor area, in etching removal positioned at the of N-type high threshold voltage area
While the N-type workfunction layer of one thickness, also etching removal is located at transmission gate transistor area gate dielectric layer
The N-type workfunction layer of the first thickness on surface, forms the transmission gate work-function layer.
9. the method for improving SRAM performances as claimed in claim 6, it is characterised in that also including step：It is right
The N-type logic device area substrate carries out N-type threshold value regulation doping treatment.
10. the method for improving SRAM performances as claimed in claim 1, it is characterised in that in the N-type logic
In device region, the thickness of the N-type workfunction layer in addition to first N-type workfunction layer is 45 angstroms
To 55 angstroms.
11. methods for improving SRAM performances as described in claim 1 or 10, it is characterised in that the transmission
The thickness of door work-function layer is 25 angstroms to 35 angstroms.
12. methods for improving SRAM performances as claimed in claim 11, it is characterised in that the Second Threshold
The Doped ions of voltage-regulation doping treatment are B, and doping concentration is 1E12atom/cm3Extremely
1E14atom/cm3。
13. methods for improving SRAM performances as claimed in claim 1, it is characterised in that described several p-types
Threshold voltage area includes p-type ultralow threshold value voltage zone, p-type standard threshold voltage area and p-type threshold high
Threshold voltage area, wherein, the corresponding P-type workfunction layer in the p-type ultralow threshold value voltage zone is a P
Type work-function layer.
14. methods for improving SRAM performances as claimed in claim 13, it is characterised in that formed described in including
The processing step of the P-type workfunction layer of the first P-type workfunction layer includes：In the p-type logical device
Area gate dielectric layer surface forms P-type workfunction layer；Second is formed on the P-type workfunction layer surface to cover
Film layer, second mask layer exposes the P-type workfunction layer surface in p-type high threshold voltage area；With
Second mask layer is mask, P of the etching removal positioned at the second thickness in p-type high threshold voltage area
Type work-function layer, the P-type workfunction layer not being etched in p-type logic device area is the first p-type work content
Several layers.
15. methods for improving SRAM performances as claimed in claim 14, it is characterised in that the p-type work content
Several floor are also located at the area gate dielectric layer surface that pulls up transistor, and second mask layer also covers crystal pulling
The P-type workfunction layer surface in body area under control, the P-type workfunction layer that the area that pulls up transistor is not etched is upper
Draw work-function layer.
16. methods for improving SRAM performances as claimed in claim 1, it is characterised in that in the p-type logic
In device region, the thickness of the P-type workfunction layer in addition to first P-type workfunction layer for 25 angstroms extremely
35 angstroms.
17. methods for improving SRAM performances as described in claim 1 or 16, it is characterised in that the pull-up
The thickness of work-function layer is 45 angstroms to 55 angstroms.
18. methods for improving SRAM performances as claimed in claim 17, it is characterised in that the first threshold
The Doped ions of voltage doping treatment are As, and doping concentration is 1E12atom/cm3Extremely
1E14atom/cm3。
19. methods for improving SRAM performances as claimed in claim 1, it is characterised in that the gate dielectric layer bag
Include boundary layer and the high-k gate dielectric layer positioned at interface layer surfaces.
20. methods for improving SRAM performances as claimed in claim 1, it is characterised in that the substrate includes lining
Bottom and the fin positioned at substrate surface, wherein, the gate dielectric layer is across fin, and covering fin
The atop part surface in portion and sidewall surfaces.
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