CN108573862B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN108573862B CN108573862B CN201710131028.2A CN201710131028A CN108573862B CN 108573862 B CN108573862 B CN 108573862B CN 201710131028 A CN201710131028 A CN 201710131028A CN 108573862 B CN108573862 B CN 108573862B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates
Abstract
A semiconductor structure and a method of forming the same, the method comprising: the device comprises a substrate, a first electrode, a second electrode and a third electrode, wherein the substrate is provided with a device structure which comprises an initial side wall structure; forming an initial first dielectric layer on the substrate, the device structure and the initial side wall structure; flattening the initial first dielectric layer to form a first dielectric layer; removing part of the initial side wall structure to form a side wall structure, wherein the top surface of the side wall structure is lower than or level to the lowest point of the top surface of the first medium layer; after the side wall structure is formed, densifying the first medium layer to form an initial second medium layer, wherein the bottom surface of the initial second medium layer is lower than the top surface of the side wall structure, and the density of the initial second medium layer is greater than that of the first medium layer; after the initial second dielectric layer is formed, the device removing structure forms an opening structure, and a material layer is formed in the opening structure and on the initial second dielectric layer; and flattening the material layer and the initial second dielectric layer until the top surface of the side wall structure is exposed to form a grid structure and a second dielectric layer. The second dielectric layer has good isolation performance.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a semiconductor structure and a method for forming the same.
Background
With the reduction of technical nodes, the traditional gate dielectric layer is continuously thinned, the leakage amount of a transistor is increased, and the problems of power consumption waste of a semiconductor device and the like are caused. To solve the above problems, the prior art provides a solution to replace the polysilicon gate with a metal gate. Wherein, the gate last process is a main process for forming the metal gate.
However, in the gate-last process, the metal material of the metal gate deteriorates the isolation performance of the dielectric layer in the semiconductor structure, thereby affecting the performance of the semiconductor structure.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which can improve the performance of the semiconductor structure.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a device structure, and the device structure comprises an initial side wall structure; forming an initial first dielectric layer on the top surfaces of the substrate, the device structure and the initial side wall structure; flattening the initial first dielectric layer until the top surface of the initial side wall structure is exposed to form a first dielectric layer; removing part of the initial side wall structure to form a side wall structure, wherein the top surface of the side wall structure is lower than or flush with the lowest point of the top surface of the first medium layer; after the side wall structure is formed, performing densification treatment on part of the first dielectric layer to form an initial second dielectric layer, wherein the bottom surface of the initial second dielectric layer is lower than the top surface of the side wall structure, and the density of the initial second dielectric layer is greater than that of the first dielectric layer; after the initial second dielectric layer is formed, forming an opening structure by removing the device structure; forming a material layer in the opening structure and on the initial second dielectric layer; and flattening the material layer and the initial second dielectric layer until the top surface of the side wall structure is exposed to form a grid structure and a second dielectric layer.
Optionally, the substrate comprises: a first region and a second region.
Optionally, the device structure includes a first dummy gate structure located in the first region and a second dummy gate structure located in the second region; the first dummy gate structure includes: the first dummy gate layer is positioned on the first dummy gate dielectric layer; the second dummy gate structure includes: the second dummy gate dielectric layer and a second dummy gate layer are positioned on the second dummy gate dielectric layer.
Optionally, a size of the first dummy gate structure along the channel length direction is smaller than a size of the second dummy gate structure along the channel length direction.
Optionally, a first mask layer is disposed on a top surface of the first dummy gate layer; the top surface of the second pseudo gate layer is provided with a second mask layer; the thickness of the first mask layer is thinner than that of the second mask layer.
Optionally, the initial sidewall spacer structure includes an initial first sidewall spacer and an initial second sidewall spacer, the initial first sidewall spacer is located on sidewalls of the first dummy gate dielectric layer and the first dummy gate layer, and the initial second sidewall spacer is located on sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.
Optionally, in the process of planarizing the initial first dielectric layer, the method further includes: and removing the first mask layer and the second mask layer.
Optionally, the material of the initial first dielectric layer includes: silicon oxide.
Optionally, the forming process of the initial first dielectric layer includes: a fluid chemical vapor deposition process.
Optionally, the process for planarizing the initial first dielectric layer includes: and (5) carrying out a chemical mechanical polishing process.
Optionally, the process for removing part of the initial sidewall structure includes: isotropic dry etching process or wet etching process.
Optionally, the process parameters of the isotropic dry etching process include: the etching gas includes: CH (CH)3F、CH2F2And O2In which CH3The flow rate of F is: 10-500 ml/min, CH2F2The flow rate of (A) is as follows: 10-200 ml/min, O2The flow rate of (A) is as follows: 10-300 standard ml/min, pressure: 2 mtorr to 50 mtorr, power: 100-200 watts.
Optionally, the removal amount of the initial sidewall structure in the direction perpendicular to the top surface of the substrate is: 3 to 10 nanometers.
Optionally, the process of performing densification processing on the first dielectric layer to form an initial second dielectric layer includes: high-temperature plasma treatment; the technological parameters of the high-temperature plasma treatment process comprise: the gas comprises: helium, the flow rate of helium is: 100-1000 ml/min, temperature: 300-500 ℃, 100-1000W of power, pressure: 0.2 to 5 torr.
Optionally, the minimum thickness of the second dielectric layer is: 5 to 20 nanometers.
Optionally, the process for planarizing the material layer and the initial second dielectric layer includes: and (3) a chemical mechanical polishing process.
Correspondingly, the invention also provides a semiconductor structure formed by adopting the method, which comprises the following steps: the grid structure comprises a side wall structure, and the top surface of the side wall structure is flush with the top surface of the grid structure; the first dielectric layer is positioned on the substrate, and the top surface of the first dielectric layer is lower than that of the side wall structure; and the top surface of the second dielectric layer is flush with the top surface of the side wall structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the top surface of the formed side wall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer by removing part of the initial side wall structure. And subsequently, carrying out densification treatment on part of the first dielectric layer to form an initial second dielectric layer, wherein the top surface of the formed initial second dielectric layer is higher than or flush with the top surface of the side wall. Even if the surface of the initial second dielectric layer is provided with a recess, the surface of the formed second dielectric layer is still flat after subsequent planarization. And the bottom surface of the initial second dielectric layer is lower than the top surface of the side wall structure, so that when the material layer is flattened subsequently until the top surface of the side wall structure is exposed, the top surface of the first dielectric layer is still completely covered by the second dielectric layer. And the density of the initial second dielectric layer is higher than that of the first dielectric layer, so that the top surface of the second dielectric layer formed after planarization is more beneficial to flattening, the performance of the second dielectric layer for isolating different devices of the semiconductor is better, and the performance of the semiconductor structure is improved.
In the semiconductor structure provided by the technical scheme of the invention, the density of the second dielectric layer positioned on the first dielectric layer is higher than that of the first dielectric layer, the top surface of the second dielectric layer is flat, and the performance of the second dielectric layer for isolating different devices of a semiconductor is better, so that the performance of the semiconductor structure is improved.
Drawings
FIGS. 1-2 are schematic structural diagrams illustrating steps of a method for forming a semiconductor structure;
fig. 3 to 8 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As mentioned in the background, the isolation performance of the dielectric layer in the semiconductor structure is not good.
Fig. 1 to 2 are schematic structural diagrams of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate is provided, where the substrate includes a first region a and a second region B, the first region a has a first dummy gate structure 101 thereon, the first dummy gate structure 101 includes a first dummy gate sidewall 102 and a first dummy gate layer (not shown), a first mask layer (not shown) is disposed on a top surface of the first dummy gate structure 101, the second region B has a second dummy gate structure 103 thereon, the second dummy gate structure 103 includes a second dummy gate sidewall 104 and a second dummy gate layer (not shown), a second mask layer (not shown) is disposed on a top surface of the second dummy gate structure 103, and the substrate, the first dummy gate structure 101, and the second dummy gate structure 103 have an initial first dielectric layer thereon; and flattening the initial first dielectric layer until the top surfaces of the first pseudo gate side wall 102 and the second pseudo gate side wall 104 are exposed to form a first dielectric layer 105, wherein the top surface of the first dielectric layer 105 is lower than the top surfaces of the first pseudo gate side wall 102 and the second pseudo gate side wall 104.
Referring to fig. 2, the first dummy gate structure 101 is removed to form a first opening, and a first gate structure 107 is formed in the first opening; the second dummy gate structure 103 is removed to form a second opening, and a second gate structure 108 is formed in the second opening.
The material of the initial first dielectric layer comprises: silicon oxide; the process for forming the initial first dielectric layer comprises the following steps: a fluid chemical vapor deposition process.
The materials of the first mask layer and the second mask layer comprise: silicon nitride.
However, the semiconductor structure prepared by the above method has poor performance because:
in the method, the first region a is used for forming a short channel region, the second region B is used for forming a long channel region, and the device pitch of the short channel region is longer than that of the long channel region. In order to form a first dummy gate structure 101 and a second dummy gate structure 103 with good topography, the thickness of the first mask layer on the first dummy gate structure 101 is thinner than the thickness of the second mask layer on the second dummy gate structure 103.
And subsequently, flattening the initial first dielectric layer by using a chemical mechanical polishing process until the top surfaces of the first pseudo gate sidewall 102 and the second pseudo gate sidewall 104 are exposed to form the first dielectric layer 105. And in the process of flattening the initial first dielectric layer, removing the first mask layer and the second mask layer. Because the density of the first mask layer and the second mask layer is higher than that of the initial first medium layer, in the process of removing the initial first medium layer, the first mask layer and the second mask layer in a planarization manner, the mechanical grinding rate of the planarization process to the initial first medium layer is higher than that to the first mask layer and the second mask layer, and therefore the top surface of the first medium layer 105 formed by the planarization process is provided with a depression.
Specifically, in the process of removing part of the initial first dielectric layer, the first mask layer and the second mask layer by planarization, since the thickness of the first mask layer is thinner than that of the second mask layer, the second mask layer still remains when the first mask layer is completely removed. When the first mask layer is completely removed, recesses are generated on the top surface of the first dielectric layer 105 in both the first region a and the second region B. After the first mask layer is removed, in order to remove the second mask layer, planarization is continuously performed on part of the initial first dielectric layer and the second mask layer, so that the depression of the surface of the first dielectric layer in the second region B is deepened. Therefore, when the second mask layer is completely removed, the top surface of the first dielectric layer 105 in the first region a has a first recess, the top surface of the first dielectric layer 105 in the second region B has a second recess, and the maximum depth of the first recess is smaller than the maximum depth of the second recess.
A first gate structure 107 is subsequently formed in the first opening and a second gate structure 108 is formed in the second opening. The forming steps of the first gate structure 107 and the second gate structure 108 include: forming a material layer in the first opening, the second opening and on the first dielectric layer 105; the material layer is planarized until the top surfaces of the first dummy gate sidewall 102 and the second dummy gate sidewall 104 are exposed. When the material layer is planarized, the material layer is easily deposited at the first recess and the second recess, so that the performance of the first dielectric layer 105 for isolating different devices of the semiconductor is poor, and the performance of the semiconductor structure is affected.
To solve the above technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a device structure, and the device structure comprises an initial side wall structure; forming an initial first dielectric layer on the top surfaces of the substrate, the device structure and the initial side wall structure; flattening the initial first dielectric layer until the top surface of the initial side wall structure is exposed to form a first dielectric layer; removing part of the initial side wall structure to form a side wall structure, wherein the top surface of the side wall structure is lower than or flush with the lowest point of the top surface of the first medium layer; after the side wall structure is formed, performing densification treatment on part of the first dielectric layer to form an initial second dielectric layer, wherein the bottom surface of the initial second dielectric layer is lower than the top surface of the side wall structure, and the density of the initial second dielectric layer is greater than that of the first dielectric layer; after the initial second dielectric layer is formed, forming an opening structure by removing the device structure; forming a material layer in the opening structure and on the initial second dielectric layer; and flattening the material layer and the initial second dielectric layer until the top surface of the side wall structure is exposed to form a grid structure and a second dielectric layer.
In the method, the top surface of the formed side wall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer by removing part of the initial side wall structure. And subsequently, carrying out densification treatment on part of the first dielectric layer to form an initial second dielectric layer, wherein the top surface of the formed initial second dielectric layer is higher than or flush with the top surface of the side wall. Even if the surface of the initial second dielectric layer is provided with a recess, the surface of the formed second dielectric layer is still flat after subsequent planarization. And the bottom surface of the initial second dielectric layer is lower than the top surface of the side wall structure, so that when the material layer is flattened subsequently until the top surface of the side wall structure is exposed, the top surface of the first dielectric layer is completely covered by the second dielectric layer. And the density of the initial second dielectric layer is higher than that of the first dielectric layer, so that the top surface of the second dielectric layer formed after planarization is more beneficial to flattening, the performance of the second dielectric layer for isolating different devices of the semiconductor is better, and the performance of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 8 are schematic structural diagrams of steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 3, a substrate 200 is provided, where the substrate 200 has a device structure (not shown), and the device structure includes an initial sidewall structure (not shown); and forming an initial first dielectric layer 201 on the substrate 200, the device structure and the initial sidewall spacer structure.
In this embodiment, the substrate 200 includes: a substrate 202 and a fin 203 on the substrate 202. In other embodiments, the base is a planar substrate.
The forming step of the substrate 200 includes: providing an initial substrate; the initial substrate is patterned to form a substrate 202 and a fin 203 on the substrate 202.
In this embodiment, the initial substrate is made of silicon. In other embodiments, the initial substrate may also be a semiconductor substrate such as a germanium substrate, a silicon-on-insulator or a germanium-on-insulator.
The substrate 200 further comprises isolation structures (not shown) for electrically isolating the different devices of the semiconductor.
In this embodiment, the substrate 200 includes a first region i for forming a short channel device and a second region ii for forming a long channel device.
In this embodiment, the device structure includes: the first dummy gate structure 204 is located in the first region i, and the second dummy gate structure 205 is located in the second region ii, and a dimension of the first dummy gate structure 204 along the channel length direction is smaller than a dimension of the second dummy gate structure 205 along the channel length direction.
In this embodiment, the method further includes: forming first source-drain doped regions 208 in the fin portion 203 on two sides of the first dummy gate structure 204; second source-drain doped regions 209 are formed in the fin portion 203 on two sides of the second dummy gate structure 205.
The dimension of the first dummy gate structure 204 along the channel length direction refers to: the first dummy gate structure 204 has a dimension along the direction of the connection line of the first source-drain doped regions 208 on both sides.
The dimension of the second dummy gate structure 205 in the channel length direction refers to: the second dummy gate structure 205 has a dimension along the direction of the connection line of the second source-drain doped regions 209 on both sides.
In this embodiment, the initial sidewall structure includes: an initial first sidewall 206 and an initial second sidewall 207.
The first dummy gate structure 204 includes: the gate structure includes a first dummy gate dielectric layer, a first dummy gate layer on the first dummy gate dielectric layer, and an initial first sidewall 206 on a sidewall of the first dummy gate dielectric layer and a sidewall of the first dummy gate layer.
The second dummy gate structure 205 includes: the second dummy gate dielectric layer, a second dummy gate layer on the second dummy gate dielectric layer, and an initial second sidewall 207 on a sidewall of the second dummy gate dielectric layer and a sidewall of the second dummy gate layer.
The initial first sidewall 206 and the initial second sidewall 207 have the same thickness.
In this embodiment, the top surface of the first dummy gate structure 204 has a first mask layer (not shown), and the first mask layer is used as a mask for forming the first dummy gate layer by etching. The top surface of the second dummy gate structure 205 has a second mask layer (not shown), the second mask layer is used as a mask for forming the second dummy gate layer by etching, and the thickness of the first mask layer is thinner than that of the second mask layer.
The reasons why the first mask layer is thinner than the second mask layer include: the first region I is used for forming a short channel region, the second region II is used for forming a long channel region, and the device pitch of the short channel region is longer than that of the channel region and is smaller than that of the short channel region. In order to form the first dummy gate structure 204 and the second dummy gate structure 205 with good topography, the thickness of the first mask layer on the first dummy gate structure 204 is thinner than the thickness of the second mask layer on the second dummy gate structure 205.
The materials of the first mask layer and the second mask layer comprise: silicon nitride.
Before forming the initial first dielectric layer 201, the method further comprises: performing light doping ion implantation on the fin portion 203 at two sides of the first dummy gate structure 204 and the second dummy gate structure 205; after the lightly doped ions are implanted, forming first source-drain doped regions 208 in the fin portion 203 on two sides of the first dummy gate structure 204; forming second source-drain doped regions 209 in the fin portion 203 on two sides of the second dummy gate structure 205; after the first source-drain doping region 208 and the second source-drain doping region 209 are formed, a stop layer 210 is formed on the substrate 200, the first source-drain doping region 208, the second source-drain doping region 209, the first mask layer, and the second mask layer.
The forming step of the first source-drain doped region 208 includes: forming openings in the fin portions 203 on two sides of the first dummy gate structure 204 by using an etching process; forming an epitaxial layer in the opening by adopting a selective epitaxial deposition process; p-type ions or N-type ions are doped in the epitaxial layer to form the first source-drain doped region 208.
The forming step of the second source-drain doped region 209 includes: forming openings in the fin portions 203 on two sides of the second dummy gate structure 205 by using an etching process; forming an epitaxial layer in the opening by adopting a selective epitaxial deposition process; and doping P-type ions or N-type ions in the epitaxial layer to form the second source drain doping region 209.
The material of the stop layer 210 includes: silicon nitride.
The material of the initial first dielectric layer 201 includes: silicon oxide. The formation process of the initial first dielectric layer 201 includes: a fluid chemical vapor deposition process. The initial first dielectric layer 201 serves to electrically insulate the different devices of the semiconductor.
Referring to fig. 4, the initial first dielectric layer 201 is planarized until the top surface of the initial sidewall spacer structure is exposed, thereby forming a first dielectric layer 211.
In the process of planarizing the initial first dielectric layer 201, the method further includes: and removing the first mask layer and the second mask layer.
The planarization process includes: and (5) carrying out a chemical mechanical polishing process. Because the density of the first mask layer and the second mask layer is greater than that of the initial first medium layer 201, in the process of removing part of the initial first medium layer 201, the first mask layer and the second mask layer by planarization, the mechanical grinding rate of the planarization process on the initial first medium layer 201 is greater than that on the first mask layer and the second mask layer, so that the top surface of the first medium layer 211 formed by the planarization process has a recess.
The first region i has a first recess in the top surface of the first dielectric layer 211, and the second region ii has a second recess in the top surface of the first dielectric layer 211. The maximum depth of the first recess is: h1, the maximum depth of the second recess being: h2, and H1 is less than H2.
The maximum depth H1 of the first recess refers to: the maximum dimension from the top surface of the first dielectric layer 211 to the top surface of the first dummy gate structure 204 in the first region i.
The maximum depth H2 of the second recess refers to: and the maximum dimension from the top surface of the first dielectric layer 211 to the top surface of the second dummy gate structure 205 in the second region ii.
Reasons for H1 being less than H2 and H1 being less than H2 include: when the first mask layer is completely removed, the top surfaces of the first dielectric layers 211 in the first region i and the second region ii are recessed. After the first mask layer is removed, in order to completely remove the second mask layer, the initial first dielectric layer 201 and the second mask layer are continuously planarized, so that the recess of the top surface of the first dielectric layer 211 in the second region ii is deepened. Therefore, when the second mask layer is completely removed, the maximum depth H1 of the first recess is made smaller than the maximum depth H2 of the second recess.
The depth of the maximum depth H2 of the second recess is: 3 to 10 nanometers.
The maximum depth H2 of the second recess determines the amount of subsequent removal of the initial sidewall structure in a direction perpendicular to the top surface of the fin 203.
Referring to fig. 5, a portion of the initial sidewall structure is removed to form a sidewall structure, where a top surface of the sidewall structure is lower than or flush with a lowest point of a top surface of the first dielectric layer 211.
The process for removing part of the initial side wall structure comprises the following steps: isotropic dry etching process or wet etching process.
The technological parameters of the isotropic dry etching process comprise: the etching gas includes: CH (CH)3F、CH2F2And O2In which CH3The flow rate of F is: 10-500 ml/min, CH2F2The flow rate of (A) is as follows: 10-200 ml/min, O2The flow rate of (A) is as follows: 10-300 standard ml/min, pressure: 2 mtorr to 50 mtorr, power: 100-200 watts.
The lowest point of the top surface of the first dielectric layer 211 is located at the maximum depth H2 of the second recess.
The amount of removal of the initial sidewall structure in a direction perpendicular to the top surface of the fin 203 is determined by the maximum depth H2 of the second recess.
In the process of removing part of the initial sidewall structure, the removal amount of the initial sidewall structure in the direction perpendicular to the top surface of the fin 203 is: 3 to 10 nanometers. The significance of selecting the removal amount of the initial sidewall structure in the direction perpendicular to the top surface of the fin 203 is: the removal amount of the initial side wall structure in the direction perpendicular to the top surface of the fin portion 203 is less than 3 nanometers, a second dielectric layer is formed on the first dielectric layer 211, and a part of material layer still remains on the top surface of the second dielectric layer when a gate structure is formed, so that the isolation performance of the second dielectric layer is influenced, and the performance of the semiconductor structure is further influenced; if the removal amount of the initial sidewall structure in the direction perpendicular to the top surface of the fin portion 203 is greater than 10 nm, the height of the subsequently formed gate structure is too low, which is not favorable for the performance of the semiconductor structure.
The side wall structure includes: a first sidewall 212 and a second sidewall 213.
The forming step of the first side wall 212 includes: and removing part of the initial first side wall 206 to form a first side wall 212, wherein the top surface of the first side wall 212 is lower than or flush with the lowest point of the top surface of the first dielectric layer 211.
The forming step of the second side wall 213 includes: and removing part of the initial second side wall 207 to form a second side wall 213, wherein the top surface of the second side wall 213 is lower than or flush with the lowest point of the top surface of the first dielectric layer 211.
The top surface of the sidewall structure is lower than or level with the lowest point of the top surface of the first dielectric layer 211, for the purpose of: in order to ensure that no material layer remains on the top surface of the second dielectric layer when the gate structure is formed during the subsequent formation of the second dielectric layer on the first dielectric layer 211, the isolation performance of the second dielectric layer is improved, and the performance of the semiconductor structure is further improved.
Referring to fig. 6, after the sidewall structure is formed, a densification process is performed on a portion of the first dielectric layer 211 to form an initial second dielectric layer 214, a bottom surface of the initial second dielectric layer 214 is lower than a top surface of the sidewall structure, and a density of the initial second dielectric layer 214 is greater than a density of the first dielectric layer 211.
The process for densifying the first dielectric layer 211 to form the initial second dielectric layer 214 includes: a high-temperature plasma treatment process; the technological parameters of the high-temperature plasma treatment process comprise: the gas comprises: helium, the flow rate of helium is: 100-1000 ml/min, temperature: 300-500 ℃, 100-1000W of power, pressure: 0.2 to 5 torr.
The principle that the density of the initial second dielectric 214 is greater than the density of the first dielectric layer 211 includes: under the high-temperature plasma treatment process, part of the first dielectric layer 211 is reformed at high temperature to form an initial second dielectric layer 214 with higher density.
The minimum thickness of the initial second dielectric layer 214 is: 5 nm to 20 nm, the minimum thickness of the initial second dielectric layer 214 is selected to have the following meaning: if the minimum thickness of the initial second dielectric layer 214 is less than 5 nm, the thickness of the initial second dielectric layer 214 is too thin when the material layer on the initial second dielectric layer 214 is planarized during the subsequent formation of the gate structure, so that the protection of the initial second dielectric layer 214 on the first dielectric layer 211 is not sufficient. That is, after the initial second dielectric layer is removed by planarization, a portion of the first dielectric layer 211 is also removed by planarization. Since the first dielectric layer 211 is formed by a fluid chemical vapor deposition process, the first dielectric layer 211 is soft in texture. In the process of removing part of the first dielectric layer 211 in a planarization manner, the first dielectric layer 211 is prone to generating depressions on two sides of a subsequently formed gate structure, and the first dielectric layer 211 with the depressions has poor isolation performance and is not beneficial to improving the performance of the semiconductor structure; if the minimum thickness of the initial second dielectric layer 214 is greater than 20 nm, the process difficulty of densifying a portion of the first dielectric layer 211 is increased.
The bottom surface of the initial second dielectric layer 214 is lower than the top surface of the sidewall structure, and the density of the initial second dielectric layer 214 is greater than the density of the first dielectric layer 211, so that the flatness of the top surface of the second dielectric layer 214 formed by subsequent planarization material layers is good, the electrical isolation performance of the second dielectric layer 214 is good, and the performance of the semiconductor structure is improved.
Referring to fig. 7, the device structure is removed to form an opening structure.
The opening structure includes: a first opening 215 and a second opening 216, the forming steps of the first opening 215 and the second opening 216 including: removing the first dummy gate structure 204 to form a first opening 215; the second dummy gate structure 205 is removed to form a second opening 216.
The process of removing the first dummy gate structure 204 and the second dummy gate structure 205 includes: anisotropic dry etching process or combination of dry etching process and wet etching process.
The technological parameters of the anisotropic dry etching process and the wet etching process combined comprise: the etching gas includes: hydrogen bromide, chlorine and oxygen, wherein the flow of the hydrogen bromide is as follows: 10-500 standard ml/min, the flow rate of chlorine gas is as follows: 10-500 standard ml/min, the flow rate of oxygen is: 2-100 ml/min, power: 100-1000W, the etching agent comprises: dilute hydrofluoric acid, the concentration ratio of hydrofluoric acid to water being: 50: 1-2000: 1, the mass fraction of the tetramethylammonium hydroxide is as follows: 0.5 to 5 percent.
Referring to fig. 8, after the opening structure is formed, a material layer is deposited in the opening structure, and the material layer and a portion of the initial second dielectric layer 214 are planarized until the top surface of the sidewall structure is exposed, so as to form a gate structure and a second dielectric layer 219.
The gate structure includes: a first gate structure 217 and a second gate structure 218, the forming steps of the first gate structure 217 and the second gate structure 218 comprising: forming a material layer within the first opening 215, the second opening 216, and on the initial second dielectric layer 214; the material layer is planarized until the top surface of the sidewall structures is exposed, a first gate structure 217 is formed in the first opening 215, and a second gate structure 218 is formed in the second opening 216.
The material of the material layer comprises: a metal layer, a material of the metal layer comprising: tungsten.
The process of planarizing the material layer includes: and (5) carrying out a chemical mechanical polishing process.
The top surface of the second dielectric layer 219 has good flatness, so that the isolation performance of the second dielectric layer is good, thereby improving the performance of the semiconductor structure.
In summary, in the present embodiment, by removing a portion of the initial sidewall structure, the top surface of the formed sidewall structure is lower than or flush with the lowest point of the top surface of the first dielectric layer. And subsequently, carrying out densification treatment on part of the first dielectric layer to form an initial second dielectric layer, wherein the top surface of the formed initial second dielectric layer is higher than or flush with the top surface of the side wall. Even if the surface of the initial second dielectric layer is provided with a recess, the surface of the formed second dielectric layer is still flat after subsequent planarization. And the bottom surface of the initial second dielectric layer is lower than the top surface of the side wall structure, so that when the material layer is flattened subsequently until the top surface of the side wall structure is exposed, the top surface of the first dielectric layer is still completely covered by the second dielectric layer. And the density of the initial second dielectric layer is higher than that of the first dielectric layer, so that the top surface of the second dielectric layer formed after planarization is more beneficial to flattening, the performance of the second dielectric layer for isolating different devices of the semiconductor is better, and the performance of the semiconductor structure is improved.
An embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 8, including:
the semiconductor device comprises a substrate 200, wherein a grid structure is arranged on the substrate 200, the grid structure is provided with a side wall structure, and the top surface of the side wall structure is flush with the top surface of the grid structure;
a first dielectric layer 211 (see fig. 5) on the substrate 200, a top surface of the first dielectric layer 211 being lower than a top surface of the gate structure;
and a second dielectric layer 219 located on the first dielectric layer 211, wherein a top surface of the second dielectric layer 219 is flush with a top surface of the gate structure.
In summary, in this embodiment, the density of the second dielectric layer on the first dielectric layer is greater than that of the first dielectric layer, and the top surface of the second dielectric layer is flat, so that the second dielectric layer has better performance in isolating different devices of the semiconductor, thereby improving the performance of the semiconductor structure.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (17)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a device structure, and the device structure comprises an initial side wall structure;
forming an initial first dielectric layer on the top surfaces of the substrate, the device structure and the initial side wall structure;
flattening the initial first dielectric layer until the top surface of the initial side wall structure is exposed to form a first dielectric layer;
removing part of the initial side wall structure to form a side wall structure, wherein the top surface of the side wall structure is lower than or flush with the lowest point of the top surface of the first medium layer;
after the side wall structure is formed, performing densification treatment on part of the first dielectric layer to form an initial second dielectric layer, wherein the bottom surface of the initial second dielectric layer is lower than the top surface of the side wall structure, and the density of the initial second dielectric layer is greater than that of the first dielectric layer;
after the initial second dielectric layer is formed, forming an opening structure by removing the device structure;
forming a material layer in the opening structure and on the initial second dielectric layer;
and flattening the material layer and the initial second dielectric layer until the top surface of the side wall structure is exposed to form a grid structure and a second dielectric layer.
2. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: a first region and a second region.
3. The method of forming a semiconductor structure of claim 2, wherein the device structure comprises a first dummy gate structure in the first region and a second dummy gate structure in the second region; the first dummy gate structure includes: the first dummy gate layer is positioned on the first dummy gate dielectric layer; the second dummy gate structure includes: the second dummy gate dielectric layer and a second dummy gate layer are positioned on the second dummy gate dielectric layer.
4. The method of forming a semiconductor structure of claim 3, wherein a dimension of the first dummy gate structure in a channel length direction is smaller than a dimension of the second dummy gate structure in the channel length direction.
5. The method for forming a semiconductor structure according to claim 4, wherein a top surface of the first dummy gate layer has a first mask layer; the top surface of the second pseudo gate layer is provided with a second mask layer; the thickness of the first mask layer is thinner than that of the second mask layer.
6. The method for forming the semiconductor structure according to claim 3, wherein the initial sidewall structure comprises an initial first sidewall and an initial second sidewall, the initial first sidewall is located on sidewalls of the first dummy gate dielectric layer and the first dummy gate layer, and the initial second sidewall is located on sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.
7. The method of forming a semiconductor structure of claim 5, wherein planarizing the initial first dielectric layer further comprises: and removing the first mask layer and the second mask layer.
8. The method of forming a semiconductor structure of claim 1, wherein a material of the initial first dielectric layer comprises: silicon oxide.
9. The method of forming a semiconductor structure of claim 1, wherein the forming of the initial first dielectric layer comprises: a fluid chemical vapor deposition process.
10. The method of forming a semiconductor structure of claim 1, wherein planarizing the initial first dielectric layer comprises: and (5) carrying out a chemical mechanical polishing process.
11. The method of claim 1, wherein the step of removing a portion of the initial sidewall spacer structure comprises: an isotropic dry etching process or a wet etching process.
12. The method of forming a semiconductor structure of claim 11, wherein the process parameters of the isotropic dry etch process comprise: the etching gas includes: CH (CH)3F、CH2F2And O2In which CH3The flow rate of F is: 10-500 ml/min, CH2F2The flow rate of (A) is as follows: 10-200 ml/min, O2The flow rate of (A) is as follows: 10-300 standard ml/min, pressure: 2 mtorr to 50 mtorr, power: 100-200 watts.
13. The method for forming a semiconductor structure of claim 1, wherein the removal amount of the initial sidewall structure in a direction perpendicular to the top surface of the substrate is: 3 to 10 nanometers.
14. The method of claim 1, wherein the densifying the first dielectric layer to form an initial second dielectric layer comprises: a high-temperature plasma treatment process; the technological parameters of the high-temperature plasma treatment process comprise: the gas comprises: helium, the flow rate of helium is: 100-1000 ml/min, temperature: 300-500 ℃, 100-1000W of power, pressure: 0.2 to 5 torr.
15. The method of forming a semiconductor structure of claim 1, wherein the minimum thickness of the second dielectric layer is: 5 to 20 nanometers.
16. The method of claim 1, wherein planarizing the material layer and the initial second dielectric layer comprises: and (3) a chemical mechanical polishing process.
17. A semiconductor structure formed by the method of any of claims 1 to 16, comprising:
the grid structure comprises a side wall structure, and the top surface of the side wall structure is flush with the top surface of the grid structure;
the first dielectric layer is positioned on the substrate, and the top surface of the first dielectric layer is lower than that of the side wall structure;
and the top surface of the second dielectric layer is flush with the top surface of the side wall structure.
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