CN107170685B - Method for forming fin type transistor - Google Patents

Method for forming fin type transistor Download PDF

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Publication number
CN107170685B
CN107170685B CN201610130608.5A CN201610130608A CN107170685B CN 107170685 B CN107170685 B CN 107170685B CN 201610130608 A CN201610130608 A CN 201610130608A CN 107170685 B CN107170685 B CN 107170685B
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layer
gate
forming
oxide layer
fin
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CN107170685A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A method of forming a fin transistor, comprising: providing a substrate comprising an N-type core area and a P-type core area, wherein the surface of the substrate is provided with a fin part and an isolation layer; forming a first gate oxide layer on the side walls and the top surfaces of the fin parts of the N-type core area and the P-type core area; forming a pseudo gate layer respectively crossing the fin parts of the N-type core region and the P-type core region on the surfaces of the isolation layer and the first gate oxide layer; forming a dielectric layer on the isolation layer and the fin portion, wherein the dielectric layer is exposed out of the top of the pseudo gate layer; removing the pseudo gate layer, forming a first groove in the dielectric layer of the N-type core region, and forming a second groove in the dielectric layer of the P-type core region; removing the first gate oxide layer at the bottom of the first trench; forming a second gate oxide layer on the side wall of the fin part exposed out of the N-type core region and the surface of the top of the fin part; forming a first grid structure which is filled in the first groove on the surface of the second grid oxide layer; and forming a second grid structure filled in the second groove on the surface of the first grid oxide layer. The performance of the formed fin transistor is improved.

Description

Method for forming fin type transistor
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin type transistor.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. As the transistor is currently widely used as the most basic semiconductor device, as the element density and the integration degree of the semiconductor device are improved, the gate size of the planar transistor is shorter and shorter, and the conventional planar transistor has weak control capability on channel current, generates a short channel effect, generates leakage current, and finally affects the electrical performance of the semiconductor device.
In order to overcome the short channel effect of the transistor and suppress the leakage current, a Fin field effect transistor (Fin FET) is proposed in the prior art, and the Fin FET is a common multi-gate device. The structure of the fin field effect transistor comprises: the semiconductor device comprises a fin part and a dielectric layer, wherein the fin part and the dielectric layer are positioned on the surface of a semiconductor substrate, the dielectric layer covers a part of the side wall of the fin part, and the surface of the dielectric layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the dielectric layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, as the density and size of semiconductor devices increase, the performance and reliability of the formed fin field effect transistor deteriorate.
Disclosure of Invention
The invention provides a method for forming a fin transistor, and the formed fin transistor is improved in performance.
To solve the above problems, the present invention provides a method for forming a fin transistor, including: providing a substrate, wherein the substrate comprises an N-type core area and a P-type core area, the substrate surfaces of the N-type core area and the P-type core area are respectively provided with a fin part, the substrate surface is provided with an isolation layer, the isolation layer covers partial side walls of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part; forming a first gate oxide layer on the side walls and the top surfaces of the fin parts of the N-type core region and the P-type core region by adopting a first oxidation process; forming a pseudo gate layer respectively crossing the fin parts of the N-type core region and the P-type core region on the surfaces of the isolation layer and the first gate oxide layer, wherein the pseudo gate layer covers the side wall and the top of part of the fin parts; forming a dielectric layer on the isolation layer and the fin portion, wherein the dielectric layer covers the side wall of the pseudo gate layer and is exposed out of the top of the pseudo gate layer; removing the pseudo gate layer, forming a first groove in the dielectric layer of the N-type core region, forming a second groove in the dielectric layer of the P-type core region, and exposing the first gate oxide layer from the first groove and the second groove; removing the first gate oxide layer at the bottom of the first groove, and exposing the side wall of the fin part and the top surface of the N-type core region; forming a second gate oxide layer on the side wall and the top surface of the fin part exposed out of the N-type core region by adopting a second oxidation process, wherein the equivalent oxide thickness of the second gate oxide layer is smaller than that of the first gate oxide layer; forming a first grid structure which is filled in the first groove on the surface of the first grid oxide layer; and forming a second grid structure filled in the second groove on the surface of the second grid oxide layer.
Optionally, the first oxidation process is an in-situ steam generation process.
Optionally, the thickness of the first gate oxide layer is 5 to 15 angstroms.
Optionally, the second oxidation process is a chemical oxidation process.
Optionally, the thickness of the second gate oxide layer is 5 to 15 angstroms.
Optionally, the substrate further includes: the substrate surfaces of the N-type peripheral area and the P-type peripheral area are respectively provided with a fin part; and before the first gate oxide layer is formed, a third gate oxide layer is formed on the side walls and the top surfaces of the fins of the N-type peripheral region and the P-type peripheral region by adopting a third oxidation process.
Optionally, the dummy gate layer further spans the fin portions of the N-type peripheral region and the P-type peripheral region.
Optionally, after removing the dummy gate layer, a third trench is formed in the dielectric layer of the N-type peripheral region, a fourth trench is formed in the dielectric layer of the P-type peripheral region, and the third gate oxide layer is exposed from the first trench and the second trench.
Optionally, the method further includes: and forming a third gate structure filled in the third groove and a fourth gate structure filled in the fourth groove on the surface of the third gate oxide layer.
Optionally, the forming process of the third gate oxide layer includes an in-situ steam generation process; the thickness of the third gate oxide layer is 15-25 angstroms.
Optionally, the step of removing the first gate oxide layer at the bottom of the first trench includes: forming a first patterned layer on the surface of the first gate oxide layer, wherein the first patterned layer exposes the first gate oxide layer at the bottom of the first trench; and etching the first gate oxide layer by taking the first patterning layer as a mask until the side wall of the fin part and the top surface of the N-type core region are exposed.
Optionally, the process for etching the first gate oxide layer is a wet etching process or an isotropic dry etching process.
Optionally, after the second gate oxide layer is formed and before the first gate structure and the second gate structure are formed, a first annealing process is performed.
Optionally, the first annealing process is spike annealing or laser annealing.
Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, and the first trench is filled with the first gate layer; the second gate structure comprises a second gate dielectric layer and a second gate layer positioned on the second gate dielectric layer, and the second trench is filled with the second gate layer.
Optionally, the forming steps of the first gate structure and the second gate structure include: forming a gate dielectric film on the surface of the dielectric layer, the surface of the inner wall of the first groove and the surface of the inner wall of the second groove; after forming the gate dielectric film, forming a gate film which is filled in the first groove and the second groove; and flattening the gate film and the gate dielectric film until the surface of the dielectric layer is exposed, forming a first gate dielectric layer and a first gate layer in the first groove, and forming a second gate dielectric layer and a second gate layer in the second groove.
Optionally, the method further includes: and after the gate dielectric film is formed, carrying out a second annealing process.
Optionally, the top surface of the fin portion further has a mask layer.
Optionally, the forming step of the isolation layer includes: forming isolation films on the surfaces of the substrate and the fin part; planarizing the isolation film; after the isolation film is flattened, etching back the isolation film until part of the side wall of the fin part is exposed; and removing the mask layer while or after the isolating film is etched back.
Optionally, before forming the isolation layer, forming a liner oxide layer on the surface of the substrate and the surface of the fin portion; after the isolation layer is formed, the exposed pad oxide layer is removed.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method, after the pseudo gate layer is removed, a first groove exposing the first gate oxide layer is formed in the N-type core region, and a second groove exposing the first gate oxide layer is formed in the P-type core region. And the first gate oxide layer is formed on the side wall and the top surface of the fin part by adopting a first oxidation process before the pseudo gate layer is formed. And after removing the pseudo gate layer, removing the first gate oxide layer at the bottom of the first trench, and forming a second oxide layer on the side wall and the top surface of the fin part exposed by the first trench by using a second oxidation process. The second oxide layer is located in a first trench, the first trench is located in an N-type core region, and the first trench is used for forming a fin transistor of the N-type core region. Because the equivalent oxide layer thickness of the formed second oxide layer is smaller than that of the first gate oxide layer, when the second gate oxide layer is used as the gate oxide layer in the fin transistor of the N-type core region, the performance of the fin transistor formed by the N-type core region can be improved, and meanwhile, the influence of defects or impurities in the second gate oxide layer on the bias temperature instability effect of the fin transistor of the N-type core region is small. Thus, the performance of the fin transistor formed in the N-type core region is improved. Meanwhile, the first gate oxide layer formed by the first oxidation process is used as the gate oxide layer of the fin type transistor formed in the P-type core region, and the defects or impurities in the first gate oxide layer formed by the first oxidation process are less, so that the bias temperature instability effect of the fin type transistor in the P-type core region can be improved, and the performance of the fin type transistor in the P-type core region is improved.
Drawings
Fig. 1 to 9 are schematic cross-sectional views illustrating a formation process of a fin transistor according to an embodiment of the invention.
Detailed Description
As described in the background, as the density and the size of semiconductor devices increase, the performance and the reliability of the formed fin field effect transistor deteriorate.
Research shows that in order to further reduce the size of a device and improve the density of the device, a high-K metal gate transistor is introduced on the basis of a fin field effect transistor, namely, a high-K dielectric material is used as a gate dielectric layer, and a metal material is used as a gate electrode. In addition, in order to improve the bonding state between the gate dielectric layer of the high-K dielectric material and the fin portion, a gate oxide layer needs to be formed between the gate dielectric layer of the high-K dielectric material and the fin portion for bonding. The high-K metal gate transistor is formed by adopting a gate last (Gate last) process, wherein in the gate last process, a gate dielectric layer made of a high-K dielectric material is formed on the surface of the inner wall of a gate groove after a pseudo gate layer made of polycrystalline silicon is removed and the gate groove is formed.
For the fin field effect transistor in the peripheral region, because the requirement on the quality of the gate oxide layer is low and the thickness of the gate oxide layer is required to be high, the gate oxide layer in the peripheral region can be formed before the pseudo gate layer is formed, damage to the gate oxide layer caused by the process of removing the pseudo gate layer is removed, and the influence on the performance of the transistor in the peripheral region is small.
For the fin field effect transistor in the core region, the requirement on the quality of the gate oxide layer is high, and the damaged gate oxide layer is not only prone to cause Time Dependent Dielectric Breakdown (TDDB), short channel effect, reduction of driving current, and improvement of power consumption, but also prone to cause Bias Temperature Instability (BTI), and the performance of the formed fin field effect transistor is poor.
In order to avoid damage to the gate oxide layer of the core region caused by the etching process for removing the dummy gate layer, the gate oxide layer of the core region needs to be formed after removing the dummy gate layer. And after removing the pseudo gate layer, forming a gate oxide layer of a core region on the exposed top and sidewall surfaces of the fin portion by using an oxidation process, wherein the process for forming the gate oxide layer of the core region can be an In-Situ Steam Generation (ISSG) process.
The core region gate oxide layer formed by the in-situ steam generation process has fewer defects or impurities and is uniform in density distribution. However, the gate Oxide layer of the core region formed by the in-situ steam generation process has a relatively thick Equivalent Oxide Thickness (EOT), and is liable to have an adverse effect on the finfet. For the P-type finfet in the core region, the bias temperature instability effect is mainly caused by defects or impurities in the gate oxide layer, so the gate oxide layer in the core region of the P-type finfet needs to be formed by the in-situ steam generation process.
However, for the N-type finfet in the core region, the bias temperature instability effect is mainly determined by the quality of the gate dielectric layer of the high-K dielectric material, and the influence factor of the quality of the gate oxide layer in the core region is small. The gate oxide layer of the core region of the N-type fin field effect transistor is formed by the in-situ steam generation process, but the equivalent oxide layer thickness of the gate oxide layer is easily increased, so that the bias temperature instability effect cannot be improved, and the performance of the formed N-type fin field effect transistor is easily deteriorated.
In order to solve the above problems, the present invention provides a method for forming a fin transistor, including: providing a substrate, wherein the substrate comprises an N-type core area and a P-type core area, the substrate surfaces of the N-type core area and the P-type core area are respectively provided with a fin part, the substrate surface is provided with an isolation layer, the isolation layer covers partial side walls of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part; forming a first gate oxide layer on the side walls and the top surfaces of the fin parts of the N-type core region and the P-type core region by adopting a first oxidation process; forming a pseudo gate layer respectively crossing the fin parts of the N-type core region and the P-type core region on the surfaces of the isolation layer and the first gate oxide layer, wherein the pseudo gate layer covers the side wall and the top of part of the fin parts; forming a dielectric layer on the isolation layer and the fin portion, wherein the dielectric layer covers the side wall of the pseudo gate layer and is exposed out of the top of the pseudo gate layer; removing the pseudo gate layer, forming a first groove in the dielectric layer of the N-type core region, forming a second groove in the dielectric layer of the P-type core region, and exposing the first gate oxide layer from the first groove and the second groove; removing the first gate oxide layer at the bottom of the first groove, and exposing the side wall of the fin part and the top surface of the N-type core region; forming a second gate oxide layer on the side wall and the top surface of the fin part exposed out of the N-type core region by adopting a second oxidation process, wherein the equivalent oxide thickness of the second gate oxide layer is smaller than that of the first gate oxide layer; forming a first grid structure which is filled in the first groove on the surface of the first grid oxide layer; and forming a second grid structure filled in the second groove on the surface of the second grid oxide layer.
After removing the pseudo gate layer, a first groove exposing the first gate oxide layer is formed in the N-type core region, and a second groove exposing the first gate oxide layer is formed in the P-type core region. And the first gate oxide layer is formed on the side wall and the top surface of the fin part by adopting a first oxidation process before the pseudo gate layer is formed. And after removing the pseudo gate layer, removing the first gate oxide layer at the bottom of the first trench, and forming a second oxide layer on the side wall and the top surface of the fin part exposed by the first trench by using a second oxidation process. The second oxide layer is located in a first trench, the first trench is located in an N-type core region, and the first trench is used for forming a fin transistor of the N-type core region. Because the equivalent oxide layer thickness of the formed second oxide layer is smaller than that of the first gate oxide layer, when the second gate oxide layer is used as the gate oxide layer in the fin transistor of the N-type core region, the performance of the fin transistor formed by the N-type core region can be improved, and meanwhile, the influence of defects or impurities in the second gate oxide layer on the bias temperature instability effect of the fin transistor of the N-type core region is small. Thus, the performance of the fin transistor formed in the N-type core region is improved. Meanwhile, the first gate oxide layer formed by the first oxidation process is used as the gate oxide layer of the fin type transistor formed in the P-type core region, and the defects or impurities in the first gate oxide layer formed by the first oxidation process are less, so that the bias temperature instability effect of the fin type transistor in the P-type core region can be improved, and the performance of the fin type transistor in the P-type core region is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 9 are schematic cross-sectional views illustrating a formation process of a fin transistor according to an embodiment of the invention.
Referring to fig. 1, a substrate 200 is provided, where the substrate 200 includes an N-type core region 210 and a P-type core region 220, the surfaces of the substrate 200 of the N-type core region 210 and the P-type core region 220 are respectively provided with a fin 201, the surface of the substrate 200 is provided with an isolation layer 202, the isolation layer 202 covers a portion of the sidewall of the fin 201, and the surface of the isolation layer 202 is lower than the top surface of the fin 201.
In this embodiment, the substrate 200 further includes: an N-type peripheral region 230 and a P-type peripheral region 240, wherein the surface of the substrate 200 of the N-type peripheral region 230 and the P-type peripheral region 240 respectively has a fin 201.
The N-type core region 210 is used to form an N-type core device; the P-type core region 220 is used to form a P-type core device; the N-type peripheral region 230 is used to form an N-type peripheral device; the P-type peripheral region 240 is used to form a P-type peripheral device.
The density of the core device is greater than that of the peripheral device, and the characteristic dimension (CD for short) of the core device is smaller than that of the peripheral device. The working current or working voltage of the core device is less than that of the peripheral device.
The top surface of the fin 201 can also have a mask layer. The mask layer is used as a mask for forming the fin portion 201 through etching, and the mask layer can be further used for protecting the top surface of the fin portion 201 in a subsequent process.
In this embodiment, the steps of forming the substrate 200 and the fin 201 include: providing a semiconductor substrate; forming a mask layer on a part of the surface of the semiconductor substrate, wherein the mask layer covers the corresponding position and shape of the fin part 201 to be formed; and etching the semiconductor substrate by taking the mask layer as a mask to form the substrate 200 and the fin part 201.
The semiconductor base is a silicon substrate, a germanium substrate and a silicon-germanium substrate. In this embodiment, the semiconductor base is a single crystal silicon substrate, that is, the material of the fin 201 and the substrate 200 is single crystal silicon.
The forming step of the mask layer comprises the following steps: forming a mask material film on the surface of the semiconductor substrate; forming a second patterning layer on the surface of the mask material film; and etching the mask material film by taking the second patterning layer as a mask until the surface of the semiconductor substrate is exposed to form the mask layer.
In one embodiment, the second patterned layer is a patterned photoresist layer, and the second patterned layer is formed by a coating process and a photolithography process. In another embodiment, in order to reduce the feature size of the fins 201 and the distance between adjacent fins 201, the second patterning layer is formed by a multiple patterning mask process. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
The process for etching the semiconductor substrate is an anisotropic dry etching process. The sidewalls of the fin 201 are perpendicular or inclined with respect to the surface of the substrate 200, and when the sidewalls of the fin 201 are inclined with respect to the surface of the substrate 200, the bottom dimension of the fin 201 is larger than the top dimension. In the present embodiment, the sidewalls of the fin 201 are inclined with respect to the surface of the substrate 200.
The substrate 200 and the fin 201 of the N-type peripheral region 230 and the N-type core region 210 further have a first well region therein, and the substrate 200 and the fin 201 of the P-type peripheral region 240 and the P-type core region 220 further have a second well region therein. The first well region and the second well region are formed by adopting an ion implantation process; the first well region and the second well region can be formed before the semiconductor substrate is etched to form the fin portion 201; alternatively, the first well region and the second well region can be formed after the fin 201 is formed.
In another embodiment, the fin portion is formed by etching a semiconductor layer formed on the surface of the substrate; the semiconductor layer is formed on the surface of the substrate by adopting a selective epitaxial deposition process. The substrate is a silicon substrate, a silicon germanium substrate, a silicon carbide substrate, a silicon-on-insulator substrate, a germanium-on-insulator substrate, a glass substrate, or a group III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate, or the like. The semiconductor layer is made of silicon, germanium, silicon carbide or silicon germanium.
The step of forming the isolation layer 202 includes: forming an isolation film on the surfaces of the substrate 200 and the fin portion 201; planarizing the isolation film; after the isolation film is planarized, etching back the isolation film until part of the side wall of the fin portion 201 is exposed; and removing the mask layer while or after the isolating film is etched back.
In this embodiment, before forming the isolation layer 202, a liner oxide layer is formed on the surfaces of the substrate 200 and the fin 201; after the isolation layer 202 is formed, the exposed pad oxide layer is removed.
In this embodiment, the material of the isolation layer 202 is silicon oxide; the thickness of the isolation layer 202 is 1/4-1/2 of the height of the fin 201. The formation process of the isolation film is a Fluid Chemical Vapor Deposition (FCVD) process. In other embodiments, the isolation film can also be formed using other chemical vapor deposition processes or physical vapor deposition processes; the other chemical vapor deposition processes include a plasma enhanced chemical vapor deposition Process (PECVD) or a high aspect ratio chemical vapor deposition process (HARP).
In this embodiment, the fluid chemical vapor deposition process comprises the steps of: forming a precursor dielectric film on the surfaces of the substrate 200, the fin part 201 and the mask layer; and carrying out an annealing process to solidify the precursor dielectric film to form the isolating film.
The planarization process is a chemical mechanical polishing process (CMP); in this embodiment, the chemical mechanical polishing process uses the mask layer as a stop layer. The process for back etching the isolating film is an isotropic dry etching process, an anisotropic dry etching process or a wet etching process.
In this embodiment, the mask layer is removed while or after the isolation film is etched back. After the isolation layer 202 is formed, the exposed liner oxide layer is removed; since the exposed pad oxide layer is damaged in the process of etching back the isolation film, the pad oxide layer 203 is not suitable for being used as a subsequent gate oxide layer, and therefore the pad oxide layer needs to be removed.
The liner oxide layer is formed by an In-Situ Steam Generation (ISSG). The parameters of the in-situ steam generation process include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 20 seconds-10 minutes. The liner oxide layer formed by the in-situ steam generation process has good step coverage capability, can tightly cover the sidewall surface of the fin portion 201, and has uniform thickness.
By forming the liner oxide layer, damage to the surfaces of the substrate 200 and the fin portion 201 during the pre-etching process and the ion implantation process can be repaired. Moreover, the liner oxide layer can also protect the surfaces of the fin 201 and the substrate 200 in subsequent processes.
Referring to fig. 2, a third oxidation process is performed to form a third gate oxide layer 203 on the sidewalls and the top surface of the fin 201 in the N-type peripheral region 230 and the P-type peripheral region 240.
The third gate oxide layer 203 is used to form gate oxide layers in the fin transistors of the N-type peripheral region 230 and the P-type peripheral region 240, and is used to enhance the bonding strength between the fin 201 and a subsequently formed gate dielectric layer in the N-type peripheral region 230 and the P-type peripheral region 240, where the gate dielectric layer is made of a high-K dielectric material (the dielectric coefficient is greater than 3.9).
The forming step of the third gate oxide layer 203 includes: respectively forming third gate oxide films on the surfaces of the fin portions 201 of the N-type core region 210, the N-type peripheral region 230, the P-type core region 220 and the P-type peripheral region 240 by adopting a third oxidation process; forming a first patterning layer on the surfaces of the third gate oxide films of the N-type core region 210 and the P-type core region 220; and etching the third gate oxide film by taking the first patterning layer as a mask until the side walls and the top surfaces of the fin portions 201 of the N-type peripheral region 230 and the P-type peripheral region 240 are exposed to form a third gate oxide layer 203.
The material of the third gate oxide layer 203 is silicon oxide; the thickness of the third gate oxide layer 203 is 15 to 25 angstroms. In this embodiment, the thickness of the third gate oxide layer 203 is 20 angstroms; the forming process of the third gate oxide film comprises an in-situ steam generation process; the parameters of the in-situ steam generation process for forming the third gate oxide film include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 10 seconds-5 minutes.
Referring to fig. 3, a first oxidation process is performed to form a first gate oxide layer 204 on sidewalls and top surfaces of the fin 201 in the N-type core region 210 and the P-type core region 220.
The first gate oxide layer 204 is used as a gate oxide layer in the fin transistor of the core region 210. Since the core region 210 is used for forming a core device, the density of the core device is high, and the operating voltage is low, the physical thickness of the first gate oxide layer 204 needs to be small to meet the requirement of reducing the device size, and meanwhile, the equivalent oxide thickness in the first gate oxide layer 204 needs to be small to meet the requirement of reducing the operating voltage.
In this embodiment, the material of the first gate oxide layer 204 is silicon oxide; the first oxidation process is an in situ steam generation process. In the first gate oxide layer 204 formed by the in-situ steam generation process, defects or impurities are few, and the density of the first gate oxide layer 204 is high, so that the bias voltage instability effect in the P-type fin transistor can be reduced. However, the first gate oxide layer 204 formed by the in-situ steam generation process has a larger equivalent oxide thickness, which tends to increase the threshold voltage of the formed fin transistor, and thus, the performance of the fin transistor is improved only by forming the first gate oxide layer 204 by the in-situ steam generation process.
The thickness of the first gate oxide layer 204 is 5-15 angstroms; in this embodiment, the thickness of the first gate oxide layer 204 is 10 angstroms. The thickness of the first gate oxide layer 204 is smaller than that of the third gate oxide layer 203, so that the first gate oxide layer 204 can reduce the operating voltage of the core device.
The parameters of the in-situ steam generation process for forming the first gate oxide layer 204 include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 10 seconds-5 minutes. Since the thickness of the first gate oxide layer 204 is smaller than that of the third gate oxide layer 203, the process time for forming the first gate oxide layer 204 is shorter than that for forming the third gate oxide film.
Referring to fig. 4, a dummy gate layer 205 is formed on the surfaces of the isolation layer 202 and the first gate oxide layer 204 and respectively crosses over the N-type core region 210 and the P-type core region 220 of the fin 201, and the dummy gate layer 205 covers the sidewalls and the top of a portion of the fin 201.
In this embodiment, the dummy gate layer 205 also spans the fin 201 of the N-type peripheral region 230 and the P-type peripheral region 240. The dummy gate layers 205 located in the N-type core region 210, the N-type peripheral region 230, the P-type core region 220, or the P-type peripheral region 240 can be the same dummy gate layer 205 or different dummy gate layers 205.
The material of the dummy gate layer 205 is polysilicon. The forming step of the dummy gate layer 205 includes: forming a pseudo gate electrode film on the surface of the isolation layer 202, the surface of the third gate oxide layer 203 and the surface of the first gate oxide layer 204; flattening the pseudo gate electrode film; after the planarization process, forming a third patterning layer on the surface of the dummy gate film, wherein the third patterning layer covers the position and the shape of the dummy gate layer 205 to be formed; and etching the pseudo gate film by taking the third patterning layer as a mask until the surfaces of the isolation layer 202 and the fin part 201 are exposed to form a pseudo gate layer 205.
In this embodiment, the method further includes: forming a side wall on the surface of the side wall of the pseudo gate layer 205; and forming a source region and a drain region in the dummy gate layer 205 and the fin part 201 on two sides of the side wall.
The material of the side wall comprises one or more of silicon oxide, silicon nitride and silicon oxynitride. The forming step of the side wall comprises the following steps: forming a side wall film on the surface of the dummy gate layer 205 by adopting a deposition process; and etching the side wall film back until the surface of the fin part 201 is exposed to form the side wall.
In one embodiment, the source and drain regions are formed by an ion implantation process. In another embodiment, the forming of the source and drain regions further comprises: forming grooves in the dummy gate layer 205 and the fin parts 201 on two sides of the side wall; forming a stress layer in the groove by adopting a selective epitaxial deposition process; and doping ions in the stress layer to form a source region and a drain region. The doping process is one or the combination of an ion implantation process and an in-situ doping process.
When the formed fin type transistor is a P type fin type transistor, the stress layer is made of silicon germanium, ions doped in the stress layer are P type ions, and the stress layer is a sigma type stress layer. When the formed fin type transistor is an N type fin type transistor, the stress layer is made of silicon carbide, and ions doped in the stress layer are N type ions.
Referring to fig. 5, a dielectric layer 206 is formed on the isolation layer 202 and the fin 201, the dielectric layer 206 covers the sidewalls of the dummy gate layer 205, and the dielectric layer 206 exposes the top of the dummy gate layer 205.
The forming step of the dielectric layer 206 includes: forming a dielectric film on the surfaces of the isolation layer 202, the fin portion 201 and the dummy gate layer 205; and flattening the dielectric film until the top surface of the dummy gate layer 205 is exposed to form the dielectric layer 206.
The forming process of the dielectric film is a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process. The dielectric layer 206 is made of silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric material (having a dielectric constant of greater than or equal to 2.5 and less than 3.9, such as porous silicon oxide or porous silicon nitride), or an ultra-low-k dielectric material (having a dielectric constant of less than 2.5, such as porous SiCOH).
In this embodiment, the dielectric layer 206 is made of silicon oxide; the forming process of the dielectric film is one or more of a Fluid Chemical Vapor Deposition (FCVD) process, a High Density Plasma Deposition (HDP) process and a Plasma enhanced Deposition process.
Referring to fig. 6, the dummy gate layer 205 is removed (as shown in fig. 5), a first trench 211 is formed in the dielectric layer 206 of the N-type core region 210, a second trench 221 is formed in the dielectric layer 206 of the P-type core region 220, and the first trench 211 and the second trench 221 expose the first gate oxide layer 204.
In this embodiment, the method further includes: after removing the dummy gate layer 205, a third trench 231 is formed in the dielectric layer 206 of the N-type peripheral region 230, a fourth trench 241 is formed in the dielectric layer 206 of the P-type peripheral region 240, and the third gate oxide layer 203 is exposed by the first trench 231 and the second trench 221.
The process for removing the dummy gate layer 205 is one or two of a dry etching process and a wet etching process; wherein the dry etching process is an isotropic dry etching process.
In this embodiment, the material of the dummy gate layer 205 is polysilicon, and the process of removing the dummy gate layer 205 is a plasma dry etching process; the parameters of the plasma dry etching process comprise: the gas comprises fluorocarbon gas, HBr and Cl2And a carrier gas, the fluorocarbon gas comprising CF4、CHF3、CH2F2Or CH3And F, the carrier gas is inert gas such as He, the gas flow is 50-400 sccm, and the pressure is 3-8 mTorr.
In another embodiment, the process of removing the dummy gate layer 205 is a wet etching process, and the etching solution of the wet etching process is a mixed solution of hydrofluoric acid and hydrogen peroxide.
Referring to fig. 7, the first gate oxide layer 204 at the bottom of the first trench 211 (as shown in fig. 6) is removed, and the sidewalls and the top surface of the fin 201 of the N-type core region 210 are exposed.
The first gate oxide layer 204 has fewer impurities or defects therein and is denser, which is beneficial to improving the bias voltage instability of the P-type fin transistor. However, the equivalent oxide thickness of the first gate oxide layer 204 is large, which easily increases the threshold voltage of the fin transistor, and still easily affects the performance of the fin transistor as a core device. Especially, for the N-type fin transistor as the core device, the bias temperature instability effect is suppressed by improving the quality of the gate dielectric layer of the high-K dielectric material, so that even if the first gate oxide layer 204 is used as the gate oxide layer of the N-type fin transistor, the performance of the N-type fin transistor as the core device is deteriorated.
Therefore, in the present embodiment, the performance of the fin transistor formed in the N-type core region 210 is improved by removing the first gate oxide layer 204 and forming a second gate oxide layer with a smaller equivalent oxide thickness on the surface of the fin 201 in the N-type core region 210.
The step of removing the first gate oxide layer 204 at the bottom of the first trench 211 includes: forming a first patterned layer 207 on the surface of the first gate oxide layer 204, wherein the first patterned layer 207 exposes the first gate oxide layer 204 at the bottom of the first trench 211; etching the first gate oxide layer 204 by using the first patterning layer 207 as a mask until the side wall and the top surface of the fin 201 of the N-type core region 210 are exposed; the first patterned layer 207 is removed.
The first patterned layer 207 includes a photoresist layer formed using a coating process and a photolithography process. Before forming the photoresist layer, an anti-reflection layer can be further formed in the second trench 221 (shown in fig. 6), the third trench 231 (shown in fig. 6) and the fourth trench 241 (shown in fig. 6) and on the surface of the dielectric layer 206, wherein the surface of the anti-reflection layer is flat; forming the photoresist layer on the surface of the anti-reflection layer; the anti-reflection layer is used for inhibiting light diffuse reflection in the photoetching process so as to improve the pattern accuracy of the photoresist layer.
The process for etching the first gate oxide layer 204 is a wet etching process or an isotropic dry etching process. In this embodiment, the material of the first gate oxide layer 204 is silicon oxide; when the first gate oxide layer 204 is removed by using a wet etching process, an etching solution of the wet etching process is a hydrofluoric acid solution. When the isotropic dry etching process is used to remove the first gate oxide layer 204, the isotropic dry etching process can be a SICONI process.
In this embodiment, the first gate oxide layer 204 at the bottom of the first trench 211 is etched and removed by using a SICONI process. The parameters of the SICONI process comprise: the power is 10W-100W, the frequency is less than 100kHz, the etching temperature is 40 ℃ to 80 ℃, the pressure is 0.5 Torr to 50 Torr, and the etching gas comprises NH3、NF3He, wherein, NH3The flow rate of (1) is 0sccm to 500sccm, NF3The flow rate of (A) is 20sccm to 200sccm, the flow rate of He is 400sccm to 1200sccm, and NF3And NH3Flow rate ratio ofIs 1: 20-5: 1.
Referring to fig. 8, a second oxidation process is performed to form a second gate oxide layer 208 on the sidewalls and the top surface of the fin 201 exposed from the N-type core region 210, where an equivalent oxide thickness of the second gate oxide layer 208 is smaller than an equivalent oxide thickness of the first gate oxide layer 204 (as shown in fig. 6).
The second gate oxide layer 208 is used as a gate oxide layer of a fin transistor formed in the N-type core region 210. The second gate oxide layer 208 is made of silicon oxide; the second gate oxide layer 208 is formed by a chemical oxidation process.
The second gate oxide layer 208 formed by the chemical oxidation process has an equivalent oxide thickness smaller than that of the first gate oxide layer 204, so that the second gate oxide layer 208 is beneficial to reducing the threshold voltage of the fin transistor formed in the N-type core region 210, thereby improving the performance of the N-type fin transistor serving as a core device.
The steps of the chemical oxidation process include: and oxidizing the exposed side wall and the exposed top surface of the fin portion 201 by adopting an aqueous solution into which ozone is introduced, and forming a second gate oxide layer 223 on the side wall and the top surface of the fin portion 201. Wherein, in the water solution with the ozone, the concentration of the ozone in the water is 1 to 15 percent.
The thickness of the second gate oxide layer 208 is 5 to 15 angstroms. In the present embodiment, the thickness of the second gate oxide layer 208 is 10 angstroms. The thickness of the second gate oxide layer 208 is not too thin, otherwise tunneling occurs in the second gate oxide layer 208, and the performance of the fin transistor is deteriorated; the thickness of the second gate oxide layer 208 is not too thick, otherwise, the equivalent oxide layer thickness is easily increased, so that the threshold voltage of the fin transistor is increased, and the formed fin transistor is not suitable for being used as a core device.
Referring to fig. 9, a first gate structure 212 is formed on the surface of the second gate oxide layer 208 to fill the first trench 211 (shown in fig. 8); a second gate structure 222 filling the second trench 221 (as shown in fig. 8) is formed on the surface of the first gate oxide layer 204.
In the present embodiment, after the second gate oxide layer 208 is formed, a first annealing process is performed before the first gate structure 212 and the second gate structure 222 are formed. The first annealing process is spike annealing or laser annealing. The first annealing process is used to remove defects or impurities inside and on the surface of the fin 201, and in the second gate oxide layer 208 and the third gate oxide layer 203.
In this embodiment, the method further includes: a third gate structure 232 filling the third trench 231 (shown in fig. 8) and a fourth gate structure 242 filling the fourth trench 241 (shown in fig. 8) are formed on the surface of the third gate oxide layer 203.
The first gate structure 212 includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer, and the first trench 211 is filled with the first gate layer; the second gate structure 222 includes a second gate dielectric layer and a second gate layer on the second gate dielectric layer, and the second gate layer fills the second trench 221.
The third gate structure 232 includes a third gate dielectric layer and a third gate layer located on the third gate dielectric layer, and the third trench 231 is filled with the third gate layer; the fourth gate structure 242 includes a fourth gate dielectric layer and a fourth gate layer on the fourth gate dielectric layer, and the fourth trench 241 is filled with the fourth gate layer.
The forming steps of the first gate structure 212, the second gate structure 222, the third gate structure 232 and the fourth gate structure 242 include: forming a gate dielectric film on the surface of the dielectric layer 206, the inner wall surfaces of the first trench 211, the second trench 221, the third trench 231 and the fourth trench 241; after forming the gate dielectric film, forming a gate film filling the first trench 211, the second trench 221, the third trench 231 and the fourth trench 241; and flattening the gate film and the gate dielectric film until the surface of the dielectric layer 206 is exposed, forming a first gate dielectric layer and a first gate layer in the first groove 211, forming a second gate dielectric layer and a second gate layer in the second groove 221, forming a third gate dielectric layer and a third gate layer in the third groove 231, and forming a fourth gate dielectric layer and a fourth gate layer in the fourth groove 241.
The first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer are made of high-k dielectric materials (the dielectric coefficient is more than 3.9); the high-k dielectric material comprises hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide. The forming process of the gate dielectric film is an atomic layer deposition process.
The materials of the first gate layer, the second gate layer, the third gate layer and the fourth gate layer comprise copper, tungsten, aluminum or silver; the forming process of the gate electrode film comprises a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, an electroplating process or a chemical plating process. And the process for flattening the gate electrode film and the gate dielectric film is a Chemical Mechanical Polishing (CMP) process.
In one embodiment, before forming the gate electrode film, forming a work function film on the surface of the gate dielectric film; forming a gate film on the surface of the work function film; after planarizing the gate film, the work function film is planarized until the surface of the dielectric layer 206 is exposed, forming a work function layer. The material of the work function layer formed in the first trench 211 and the third trench 231 includes an N-type work function material; the material of the work function layer formed in the second trench 221 and the fourth trench 241 includes a P-type work function material.
In this embodiment, after the gate dielectric film is formed, a second annealing process is performed. And the second annealing process is used for eliminating defects or impurities in the first gate dielectric layer, the second gate dielectric layer, the third gate dielectric layer and the fourth gate dielectric layer. Also, the annealing process can also be used to activate impurity ions located in the source and drain regions within the fin 201.
In summary, in the embodiment, after removing the dummy gate layer, a first trench exposing the first gate oxide layer is formed in the N-type core region, and a second trench exposing the first gate oxide layer is formed in the P-type core region. And the first gate oxide layer is formed on the side wall and the top surface of the fin part by adopting a first oxidation process before the pseudo gate layer is formed. And after removing the pseudo gate layer, removing the first gate oxide layer at the bottom of the first trench, and forming a second oxide layer on the side wall and the top surface of the fin part exposed by the first trench by using a second oxidation process. The second oxide layer is located in a first trench, the first trench is located in an N-type core region, and the first trench is used for forming a fin transistor of the N-type core region. Because the equivalent oxide layer thickness of the formed second oxide layer is larger than that of the first gate oxide layer, when the second gate oxide layer is used as the gate oxide layer in the fin transistor of the N-type core region, the performance of the fin transistor formed by the N-type core region can be improved, and meanwhile, the influence of defects or impurities in the second gate oxide layer on the bias temperature instability effect of the fin transistor of the N-type core region is small. Thus, the performance of the fin transistor formed in the N-type core region is improved. Meanwhile, the first gate oxide layer formed by the first oxidation process is used as the gate oxide layer of the fin type transistor formed in the P-type core region, and the defects or impurities in the first gate oxide layer formed by the first oxidation process are less, so that the bias temperature instability effect of the fin type transistor in the P-type core region can be improved, and the performance of the fin type transistor in the P-type core region is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method for forming a fin transistor includes:
providing a substrate, wherein the substrate comprises an N-type core area and a P-type core area, the substrate surfaces of the N-type core area and the P-type core area are respectively provided with a fin part, the substrate surface is provided with an isolation layer, the isolation layer covers partial side walls of the fin part, and the surface of the isolation layer is lower than the top surface of the fin part;
forming a first gate oxide layer on the side walls and the top surfaces of the fin parts of the N-type core region and the P-type core region by adopting a first oxidation process;
forming a pseudo gate layer respectively crossing the fin parts of the N-type core region and the P-type core region on the surfaces of the isolation layer and the first gate oxide layer, wherein the pseudo gate layer covers the side wall and the top of part of the fin parts;
forming a dielectric layer on the isolation layer and the fin portion, wherein the dielectric layer covers the side wall of the pseudo gate layer and is exposed out of the top of the pseudo gate layer;
removing the pseudo gate layer, forming a first groove in the dielectric layer of the N-type core region, forming a second groove in the dielectric layer of the P-type core region, and exposing the first gate oxide layer from the first groove and the second groove;
removing the first gate oxide layer at the bottom of the first groove, and exposing the side wall of the fin part and the top surface of the N-type core region;
forming a second gate oxide layer on the side wall and the top surface of the fin part exposed out of the N-type core region by adopting a second oxidation process, wherein the equivalent oxide thickness of the second gate oxide layer is smaller than that of the first gate oxide layer;
forming a first grid structure which is filled in the first groove on the surface of the second grid oxide layer;
and forming a second grid structure filled in the second groove on the surface of the first grid oxide layer.
2. The method of claim 1, wherein the first oxidation process is an in-situ steam generation process.
3. The method of claim 1, wherein the first gate oxide layer is between 5 and 15 angstroms thick.
4. The method of claim 1, wherein the second oxidation process is a chemical oxidation process.
5. The method of claim 1, wherein the second gate oxide layer is between 5 and 15 angstroms thick.
6. The method of forming the fin-type transistor of claim 1, wherein the substrate further comprises: the substrate surfaces of the N-type peripheral area and the P-type peripheral area are respectively provided with a fin part; and before the first gate oxide layer is formed, a third gate oxide layer is formed on the side walls and the top surfaces of the fins of the N-type peripheral region and the P-type peripheral region by adopting a third oxidation process.
7. The method of claim 6, wherein the dummy gate layer further spans fins of the N-type and P-type periphery regions.
8. The method of claim 7, wherein after removing the dummy gate layer, a third trench is formed in the dielectric layer in the N-type periphery region and a fourth trench is formed in the dielectric layer in the P-type periphery region, the first trench and the second trench exposing the third gate oxide layer.
9. The method of forming the fin-type transistor of claim 8, further comprising: and forming a third gate structure filled in the third groove and a fourth gate structure filled in the fourth groove on the surface of the third gate oxide layer.
10. The method of claim 6, wherein the third gate oxide layer formation process comprises an in-situ steam generation process; the thickness of the third gate oxide layer is 15-25 angstroms.
11. The method of claim 1, wherein removing the first gate oxide layer at the bottom of the first trench comprises: forming a first patterned layer on the surface of the first gate oxide layer, wherein the first patterned layer exposes the first gate oxide layer at the bottom of the first trench; and etching the first gate oxide layer by taking the first patterning layer as a mask until the side wall of the fin part and the top surface of the N-type core region are exposed.
12. The method of claim 11, wherein the etching process of the first gate oxide layer is a wet etching process or an isotropic dry etching process.
13. The method of claim 1, wherein a first annealing process is performed after forming the second gate oxide layer and before forming the first gate structure and the second gate structure.
14. The method of claim 13, wherein the first annealing process is a spike anneal or a laser anneal.
15. The method of claim 1, wherein the first gate structure comprises a first gate dielectric layer and a first gate layer over the first gate dielectric layer, the first gate layer filling the first trench; the second gate structure comprises a second gate dielectric layer and a second gate layer positioned on the second gate dielectric layer, and the second trench is filled with the second gate layer.
16. The method of forming the fin-type transistor of claim 15, wherein the forming of the first and second gate structures comprises: forming a gate dielectric film on the surface of the dielectric layer, the surface of the inner wall of the first groove and the surface of the inner wall of the second groove; after forming the gate dielectric film, forming a gate film which is filled in the first groove and the second groove; and flattening the gate film and the gate dielectric film until the surface of the dielectric layer is exposed, forming a first gate dielectric layer and a first gate layer in the first groove, and forming a second gate dielectric layer and a second gate layer in the second groove.
17. The method of forming the fin-type transistor of claim 16, further comprising: and after the gate dielectric film is formed, carrying out a second annealing process.
18. The method of claim 1, wherein a mask layer is further formed on a top surface of the fin.
19. The method of forming the fin-type transistor of claim 18, wherein the forming the isolation layer comprises: forming isolation films on the surfaces of the substrate and the fin part; planarizing the isolation film; after the isolation film is flattened, etching back the isolation film until part of the side wall of the fin part is exposed; and removing the mask layer while or after the isolating film is etched back.
20. The method of claim 1, wherein a liner oxide layer is formed on the substrate and fin surface prior to forming the isolation layer; after the isolation layer is formed, the exposed pad oxide layer is removed.
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CN103681672A (en) * 2012-08-31 2014-03-26 三星电子株式会社 Semiconductor device and method of fabricating the same
CN104979198A (en) * 2014-04-02 2015-10-14 中芯国际集成电路制造(上海)有限公司 Method for forming fin type field effect transistor

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