CN108807377B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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CN108807377B
CN108807377B CN201710304556.3A CN201710304556A CN108807377B CN 108807377 B CN108807377 B CN 108807377B CN 201710304556 A CN201710304556 A CN 201710304556A CN 108807377 B CN108807377 B CN 108807377B
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layer
opening
forming
protective layer
semiconductor device
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CN108807377A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

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  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Drying Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a semiconductor device and a forming method thereof, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate is provided with a first opening and a second opening, and removing a second protective layer and a first protective layer in the second opening by taking a first patterning layer as a mask to expose a first gate oxide layer at the bottom of the second opening; removing the first gate oxide layer at the bottom of the second opening and the second protective layer in the first opening to expose the first protective layer at the bottom of the first opening; and forming a second gate oxide layer at the bottom of the second opening. The forming method can avoid photoresist residue and prevent the etching process from damaging the film layer of the core region, thereby improving the channel region quality of the semiconductor device, reducing leakage current and improving the performance and reliability of the semiconductor device.

Description

Semiconductor device and method of forming the same
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.
Background
Transistors are currently being widely used as the most basic semiconductor devices. As the element density and integration of semiconductor devices increase, the gate size becomes shorter and shorter, and the control capability of the conventional transistor on channel current becomes weaker, which causes a short-channel effect, and ultimately affects the electrical performance of the semiconductor device.
In order to further reduce the size of a device and improve the density of the device, a high-K metal gate transistor is introduced on the basis of a semiconductor device, namely a high-K dielectric material is used as a gate dielectric layer, and a metal material is used as a gate electrode; in addition, in order to improve the bonding state between the gate dielectric layer of the high-K dielectric material and the fin portion, a gate oxide layer needs to be formed between the gate dielectric layer of the high-K dielectric material and the fin portion for bonding. The high-K metal gate transistor is formed by adopting a gate last (gate last) process, wherein one gate last process is to remove a pseudo gate layer of polycrystalline silicon and form a gate groove, and then form a gate dielectric layer made of a high-K dielectric material on the surface of the inner wall of the gate groove.
However, as the density of semiconductor devices increases and the size decreases, the difficulty of manufacturing the semiconductor devices increases, and the performance of the formed semiconductor devices deteriorates and the reliability decreases.
Disclosure of Invention
The problem to be solved by the present invention is to provide a semiconductor device and a method for forming the same, the leakage current of the formed semiconductor device is controlled, the driving current is increased, the power consumption is reduced, and the stability is improved.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate comprises a core region and a peripheral region, the substrate is provided with a dielectric structure, the dielectric structure is internally provided with a first opening and a second opening, the first opening is positioned in the peripheral region, the second opening is positioned in the core region, the substrate at the bottoms of the first opening and the second opening is respectively provided with a first gate oxide layer, and the surface of the first gate oxide layer is provided with a first protective layer; forming a second protective layer on the dielectric structures of the core region and the peripheral region, the side wall and the bottom of the first opening and the side wall and the bottom of the second opening; forming a first patterned layer on the second protective layer, wherein the first patterned layer exposes the second protective layer in the second opening; removing the second protective layer and the first protective layer in the second opening by taking the first patterning layer as a mask to expose the first gate oxide layer at the bottom of the second opening; removing the first patterned layer after removing the second protective layer and the first protective layer within the second opening; after the first patterning layer is removed, removing the first gate oxide layer at the bottom of the second opening and the second protective layer in the first opening to expose the first protective layer at the bottom of the first opening; and after removing the first gate oxide layer at the bottom of the second opening and the second protective layer in the first opening, forming a second gate oxide layer at the bottom of the second opening.
Optionally, the substrate includes: the device comprises a substrate and an isolation layer positioned on the substrate. The substrate is provided with a fin part; the isolation layer covers part of the side wall of the fin portion, and the top of the isolation layer is lower than the top of the fin portion.
Optionally, the material of the isolation layer is silicon oxide.
Optionally, the forming steps of the first gate oxide layer and the first protection layer include: forming a first gate oxide layer on the surface of the substrate before forming the dielectric structure, the first opening and the second opening; and carrying out surface treatment on the first gate oxide layer, and forming a first protective layer on the surface of the first gate oxide layer.
Optionally, the first gate oxide layer is made of silicon oxide.
Optionally, the forming process of the first gate oxide layer is an in-situ steam generation process.
Optionally, the step of surface treatment comprises: performing a decoupling plasma nitridation process on the surface of the first gate oxide layer to form an initial protective layer on the surface of the first gate oxide layer; and carrying out annealing process on the initial protection layer to form a first protection layer.
Optionally, the step of forming the first opening and the second opening in the dielectric structure includes: forming a pseudo gate structure on the substrate of the core region and the substrate of the peripheral region respectively, wherein the pseudo gate structure comprises a pseudo gate layer, and the pseudo gate layer is positioned on the first protective layer; forming a source region and a drain region which are respectively positioned in the substrate at two sides of the pseudo gate structure; forming a dielectric structure on the substrate, wherein the dielectric structure covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate layer; and removing the pseudo gate layer and exposing the first protective layer, forming a first opening in the dielectric structure of the peripheral region, and forming a second opening in the dielectric structure of the core region.
Optionally, the dummy gate structure further includes: and the side wall is positioned on the side wall of the pseudo gate layer.
Optionally, the first dielectric layer and the second dielectric layer are located on the first dielectric layer.
Optionally, the hardness of the second dielectric layer is higher than that of the first dielectric layer.
Optionally, the process of removing the dummy gate layer is one or two of a wet etching process and a dry etching process.
Optionally, the step of removing the second protection layer and the first protection layer in the second opening by using the first patterning layer as a mask includes: the first patterned layer fills the first opening, and is also positioned above the dielectric structure of the peripheral region; removing the second protective layer of the core region by taking the first patterning layer as a mask until the first protective layer of the second opening is exposed; after removing the second protective layer of the core region, removing the first protective layer in the second opening until the first gate oxide layer on the substrate of the second opening is exposed; after removing the first protective layer within the second opening, the first patterned layer is removed.
Optionally, the first protection layer is made of silicon oxynitride.
Optionally, the second protective layer is made of silicon oxide.
Optionally, the forming process of the second protection layer is an atomic layer deposition process.
Optionally, the process of removing the second protection layer is a wet etching process, and process parameters of the wet etching process include: the mass percentage of the hydrofluoric acid to the water is 1: 500-1: 2000, the etching time is 5-1000 seconds, and the over-etching amount is 50-300%.
Optionally, the process for removing the first protection layer is a dry etching process, and the process parameters of the dry etching process include: the gas flow rate of He is 600 sccm-2000 sccm, NH3The gas flow rate of (1) is 200 sccm-500 sccm, NF3The gas flow rate of the gas is 20sccm to 200 sccm; the pressure is 2to 10torr, the etching time is 5 to 100 seconds, and the over-etching amount is 50 to 100 percent.
Optionally, a first gate structure filling the first opening is formed on the surface of the first protection layer in the peripheral region; and forming a second gate structure filling the second opening on the surface of the second gate oxide layer of the core region.
The invention also provides a semiconductor device formed by any one of the methods.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the forming method provided by the technical scheme of the invention, after the second protective layer and the first protective layer in the core region are removed, the first gate oxide layer in the core region and the second protective layer in the peripheral region are exposed on the surface of the substrate at the moment, and because the first gate oxide layer and the second protective layer are made of silicon oxide, the first gate oxide layer in the core region can be removed while the second protective layer in the peripheral region is removed, so that the risk that the fin part in the core region is exposed in an etching environment is reduced, the channel region quality of the semiconductor device is improved, the leakage current is reduced, and the performance and the reliability of the semiconductor device are improved.
Further, the first protective layer and the second protective layer of the core region are removed in two steps. Removing the second protective layer made of silicon oxide by a wet etching process; and removing the first protective layer made of silicon oxynitride by a dry etching process. The dry etching is an anisotropic plasma etching process, and the etching selectivity between different materials is high, so that when the first protective layer made of silicon oxynitride is etched, the first gate oxide layer made of silicon oxide is not affected, the risk of over-etching is avoided when the first gate oxide layer in the core region is removed in the follow-up process, and the electrical reliability of the semiconductor device is improved.
Drawings
Fig. 1 to 4 are schematic cross-sectional views illustrating a process of forming a semiconductor device;
fig. 5 to 17 are schematic cross-sectional views illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
As described in the background art, as the density of semiconductor devices increases and the size decreases, the performance of the formed semiconductor devices deteriorates and the reliability decreases.
For the peripheral semiconductor device, since the gate oxide layer is formed before the dummy gate layer is formed, the process of removing the dummy gate layer may damage the gate oxide layer. The damage of the gate oxide layer has more obvious influence on the performance of the semiconductor device as the size of the semiconductor device is smaller. The following description will be made with reference to the accompanying drawings.
Fig. 1 to 4 are schematic cross-sectional views illustrating a process of forming a semiconductor device.
Referring to fig. 1, a substrate 100 is provided, where the substrate 100 includes a peripheral region 110 and a core region 120, and the surfaces of the substrate 100 in the peripheral region 110 and the core region 120 respectively have fins 101; forming an isolation layer 102 on the surface of the substrate 100; forming a dielectric layer 103 on the isolation layer 102 and the fin 101, wherein a first opening 111 is formed in the dielectric layer of the peripheral region 110, a second opening 121 is formed in the dielectric layer of the core region 120, and dummy gate dielectric layers 104 are respectively arranged on the substrate at the bottoms of the first opening 111 and the second opening 121.
Referring to fig. 2, a second passivation layer 106 is formed on the dielectric layer 103 in the peripheral region 110 and the core region 120, on the sidewall and the bottom of the first opening 111, and on the sidewall and the bottom of the second opening 121; a first patterned layer 131 is formed on the second passivation layer 106, and the first patterned layer 131 exposes the second passivation layer 106 in the second opening 121.
Referring to fig. 3, the second passivation layer 106 on the dielectric layer 103 of the core region 120 and in the second opening 121 and the dummy gate dielectric layer 104 at the bottom of the second opening 121 are removed by using the first patterning layer 131 as a mask.
Referring to fig. 4, after removing the second passivation layer 106 on the dielectric layer 103 in the core region 120 and in the second opening 121 and the dummy gate dielectric layer 104 at the bottom of the second opening 121, the first patterning layer 131 is removed (as shown in fig. 3); after removing the patterning layer 131, the second protection layer 106 is removed on the dielectric layer 103 in the peripheral region 110 and in the first opening 111 (as shown in fig. 3).
The first opening 111 and the second opening 121 are formed after the dummy gate layer on the dummy gate dielectric layer is removed, and because the dummy gate dielectric layer 104 is damaged in the process of removing the dummy gate layer, the dummy gate dielectric layer 104 in the core region is not suitable for being used as a gate oxide layer of a device in the core region, and the requirements of the peripheral region on the density of the gate oxide layer and the number of internal defects are low, so that the dummy gate dielectric layer 104 in the peripheral region can be reserved.
In order to remove the dummy gate dielectric layer in the core region 120 and retain the dummy gate dielectric layer in the peripheral region, the first patterning layer 131 needs to be formed in the peripheral region as a mask. Before the first patterning layer 131 is formed, the formed second protection layer 106 can prevent the pseudo gate dielectric layer 104 in the core region 120 and the peripheral region 110 from reacting, so as to avoid photoresist residue and damage to the film structure. However, since a portion of the sidewalls and the top surface of the fin 101 in the core region 120 are exposed before the second passivation layer 106 in the first opening 111 is removed, the fin 101 in the core region 120 is damaged during the etching process of the second passivation layer 106. The damaged fin 101 not only easily causes Time Dependent Dielectric Breakdown (TDDB), resulting in a short channel effect, reducing a driving current, and increasing power consumption, but also easily causes a Bias Temperature Instability (BTI), and the performance of the formed semiconductor structure is deteriorated.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor device, in which after removing a first protective layer and a second protective layer in a core region, the second protective layer in a peripheral region is removed, and simultaneously, a first gate oxide layer in the core region is removed, so that damage to the core region by an etching process can be prevented, thereby improving the quality of a channel region of the semiconductor device, reducing leakage current, and improving the performance and reliability of the semiconductor device.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 17 are schematic cross-sectional views illustrating a process of forming a semiconductor device according to an embodiment of the present invention.
Providing a substrate, wherein the substrate comprises a core area and a peripheral area, the substrate is provided with a dielectric structure, the dielectric structure is internally provided with a first opening and a second opening, the first opening is positioned in the peripheral area, the second opening is positioned in the core area, the substrate at the bottoms of the first opening and the second opening is respectively provided with a first gate oxide layer, and the surface of the first gate oxide layer is provided with a first protective layer. The formation processes of the dielectric structure, the first opening, the second opening, the first gate oxide layer and the first protective layer are described below with reference to fig. 5 to 10.
Referring to fig. 5, a substrate is provided, the substrate including a core region 220 and a peripheral region 210.
In this embodiment, the substrate includes: a substrate 200 and an isolation layer 202 on the substrate. The substrate has a fin 201; the isolation layer covers part of the side wall of the fin portion, and the top of the isolation layer is lower than the top of the fin portion.
In other embodiments, the substrate is a planar base.
The core region 220 is used to form core devices and the peripheral region 210 is used to form peripheral devices. The density of core devices in the core region 220 is greater than the density of peripheral devices in the peripheral region 210, and the Critical Dimension (CD) of the core devices is smaller than the CD of the peripheral devices. The working current or working voltage of the core device is less than that of the peripheral device.
In this embodiment, the steps of forming the substrate 200 and the fin 201 include: providing a semiconductor substrate; forming an initial patterning layer on a part of the surface of the semiconductor substrate, wherein the initial patterning layer needs to cover the corresponding position and shape of the fin portion 201; and etching the semiconductor substrate by taking the initial patterning layer as a mask to form the substrate 200 and the fin part 201.
The material of the semiconductor substrate can be monocrystalline silicon, polycrystalline silicon or amorphous silicon; the material of the semiconductor substrate can also be semiconductor materials such as silicon, germanium, silicon germanium, gallium arsenide and the like; the semiconductor substrate may also be a semiconductor material such as silicon, germanium, silicon germanium, gallium arsenide, or the like on an insulator. In this embodiment, the semiconductor base is a single crystal silicon substrate, that is, the material of the fin 201 and the base 200 is single crystal silicon.
In this embodiment, the initial patterning layer is a photoresist layer and is formed by a coating process and a photolithography process. In another embodiment, the photoresist layer is formed by a multiple patterning mask process in order to reduce the feature size of the fins 201 and the distance between adjacent fins 201.
The process for etching the semiconductor substrate is an anisotropic dry etching process. The sidewalls of the fin 201 are perpendicular or inclined with respect to the surface of the substrate 200, and when the sidewalls of the fin 201 are inclined with respect to the surface of the substrate 200, the bottom dimension of the fin 201 is larger than the top dimension. In the present embodiment, the sidewalls of the fin 201 are vertical with respect to the surface of the substrate 200.
In another embodiment, the fin portion is formed on the semiconductor layer on the surface of the substrate by etching; the semiconductor layer is formed on the surface of the substrate by adopting a selective epitaxial deposition process. The substrate is a substrate of silicon, germanium, silicon germanium and the like, and can also be a substrate of silicon, germanium, silicon germanium and the like on an insulator; the substrate may also be a glass substrate or a III-V compound substrate. The semiconductor layer is made of silicon, germanium, silicon carbide or silicon germanium.
The step of forming the isolation layer 202 includes: forming an isolation film on the surfaces of the substrate 200 and the fin 201; planarizing the isolation film; after planarization or the isolation film, the isolation film is etched back until a portion of the sidewalls of the fin 201 is exposed.
In this embodiment, the material of the isolation layer 202 is silicon oxide; the thickness of the isolation layer 202 is 1/4-1/2 of the height of the fin 201. The formation process of the isolation film is a Flow Chemical Vapor Deposition (FCVD) process.
In other embodiments, the isolation film can also be formed by other chemical vapor deposition processes or physical vapor deposition processes; the other chemical vapor deposition processes include a plasma enhanced chemical vapor deposition Process (PECVD) or a high aspect ratio chemical vapor deposition process (HARP).
The planarization process is a chemical mechanical polishing process (CMP). In the present embodiment, the cmp process is performed until the top surface of the fin 201 is exposed. The process for back etching the isolation film is one or the combination of a wet etching process and a dry etching process.
Referring to fig. 6, an initial first gate oxide layer 213 is formed on the surface of the substrate.
The initial first gate oxide layer 213 serves as a dummy gate dielectric layer for protecting the surface of the substrate during subsequent removal of the dummy gate layer.
In this embodiment, the initial first gate oxide layer 213 is used to form a first gate oxide layer of the subsequent peripheral region 210, so as to enhance the bonding strength between the fin 201 of the peripheral region 210 and the subsequently formed first gate dielectric layer.
In the present embodiment, the initial first gate oxide layer 213 is formed on the substrate 200 and the fin 201, and covers the sidewalls and the top surface of the fin 201.
In this embodiment, the material of the initial first gate oxide layer 213 is silicon oxide, and the formation process of the first gate oxide layer 213 is an In-Situ Steam Generation process (ISSG); the initial first gate oxide layer 213 has a thickness of 20 to 60 angstroms. The parameters of the in-situ steam generation process include: the temperature is 700-1200 ℃, the gas comprises hydrogen and oxygen, the flow of the oxygen is 1 slm-50 slm, the flow of the hydrogen is 1 slm-10 slm, and the time is 10 seconds-5 minutes. The initial first gate oxide layer formed by the in-situ steam generation process has good step coverage capability, can be tightly covered on the surface of the side wall of the fin portion 201, and is uniform in thickness.
In another embodiment, the forming process of the initial first gate oxide layer 213 is a chemical oxidation process; the steps of the chemical oxidation process include: and oxidizing the exposed side wall and the top surface of the fin part 201 by adopting an aqueous solution into which ozone is introduced, and forming a first oxidation layer on the side wall and the surface of the fin part 201. Wherein, in the water solution with the ozone, the concentration of the ozone in the water is 1 to 15 percent.
Referring to fig. 7, the initial first gate oxide layer 213 (as shown in fig. 6) is subjected to a surface treatment to form a first gate oxide layer 203 and a first protection layer 204 on the surface of the first gate oxide layer 203.
The step of surface treatment comprises: processing the surface of the initial first gate oxide layer by adopting a decoupling plasma nitridation process, and forming an initial protective layer on the surface of the first gate oxide layer 203; and performing an annealing process on the initial protection layer to form a first protection layer 204. The nitrogen content gradually decreases from the film outer surface of the first protective layer 204 to the inner surface of the first protective layer.
The first gate oxide layer 203 is not suitable for use as a gate oxide layer of the device in the core region 220, and the peripheral region 210 has low requirements for the density of the gate oxide layer and the number of internal defects, so that the first gate oxide layer 203 in the peripheral region 210 can be retained.
The first protection layer 204 can reduce the damage to the first gate oxide layer 203 in the subsequent etching process for removing the dummy gate layer. When the subsequent etching process for removing the dummy gate layer includes a plasma dry etching process, the plasma etching process is prone to damage the inside of the fin portion 201, and the first protection layer 204 is high in density and hardness, so that the first protection layer can be used for blocking plasma and preventing the fin portion 201 from being damaged, leakage current of a semiconductor device formed in the peripheral region 210 can be reduced, and electrical performance is improved.
In this embodiment, the first gate oxide layer 203 is made of silicon oxide, and the first protection layer 204 is made of silicon oxynitride.
In the present embodiment, the first protection layer 204 covers the sidewalls and the top surface of the fin 201 exposed above the isolation layer 202. When the pseudo gate layer is removed subsequently, the density and hardness of the first protective layer 204 are favorable for protecting the first gate oxide layer 203 and the fin portion 201; moreover, the first protective layer 204 has a higher dielectric coefficient, which is beneficial to inhibiting the tunneling phenomenon of carriers between the fin portion 201 and the first gate dielectric layer formed subsequently, and reducing the leakage current.
The thickness of the first gate oxide layer 203 is 10to 50 angstroms, and the thickness of the first protection layer 204 is 10to 25 angstroms. For the purpose of subsequently and simultaneously removing the first gate oxide layer and the subsequently formed second protection layer, the thickness of the first gate oxide layer 203 and the thickness of the subsequent second protection layer present a corresponding relationship.
And forming a dielectric structure, a first opening and a second opening. The dielectric structure and the steps of forming the first and second openings in the dielectric structure are described below with reference to fig. 8 to 10.
Referring to fig. 8, dummy gate structures are formed on the substrate in the core region 220 and the substrate in the peripheral region 210, respectively, the dummy gate structures include a dummy gate layer 205, and the dummy gate layer 205 is located on the first protection layer 204.
The material of the dummy gate layer 205 is polysilicon. The forming step of the dummy gate layer 205 includes: forming a pseudo gate electrode film on the surface of the first protective layer; flattening the pseudo gate electrode film; after the planarization process, forming a second patterning layer on the surface of the dummy gate film, wherein the second patterning layer covers the position and the shape of the dummy gate layer 205 to be formed; and etching the pseudo gate film by taking the second patterning layer as a mask until the surface of the substrate is exposed to form a pseudo gate layer.
In this embodiment, the method further includes: forming a side wall 215 on the surface of the side wall of the dummy gate layer 205; and forming a source region and a drain region in the dummy gate layer 205 and the fin part 201 on two sides of the side wall.
The material of the sidewall spacers 215 includes one or more of silicon oxide, silicon nitride and silicon oxynitride. The forming step of the side wall 215 includes: forming a side wall film on the surface of the dummy gate layer 205 by adopting a deposition process; the sidewall film is etched back until the top surface of the dummy gate layer 205 is exposed, forming a sidewall 215.
In another embodiment, the forming steps of the source region and the drain region further comprise forming grooves in the fin 201 on two sides of the pseudo gate layer 205 and the side wall 215, forming stress layers in the grooves by adopting a selective epitaxial deposition process, and doping ions in the stress layers to form the source region and the drain region, wherein when the formed semiconductor device is a PMOS transistor, the material of the stress layers is silicon germanium, the ions doped in the stress layers are P-type ions, the stress layers are ∑ -type stress layers, when the formed semiconductor device is an NMOS transistor, the material of the stress layers is silicon carbide, and the ions doped in the stress layers are N-type ions.
Referring to fig. 9, a dielectric structure 230 is formed on the substrate, the dielectric structure 230 covers the sidewalls of the dummy gate structure, and the dielectric structure 230 exposes the top of the dummy gate layer 205.
The dielectric structure 230 includes a first dielectric layer 231 and a second dielectric layer 232 on the first dielectric layer 231, and the hardness of the second dielectric layer 232 is higher than that of the first dielectric layer 231. The second dielectric layer 232 is used as a protective layer for the first dielectric layer during subsequent grinding due to its higher hardness. The thickness of the first dielectric layer 231 is 250 to 500 angstroms, and the thickness of the second dielectric layer 232 is 300to 1000 angstroms.
The forming step of the dielectric structure 230 includes: forming a first dielectric film and a second dielectric film on the surfaces of the isolation layer 202 and the dummy gate layer 205; and flattening the first dielectric film and the second dielectric film until the top surface of the pseudo gate layer 205 is exposed, so as to form the dielectric structure 230.
The forming process of the first dielectric film and the second dielectric film is one or more of a chemical vapor deposition process, a physical vapor deposition process and an atomic layer deposition process. The dielectric structure 230 is made of one or more of silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric material (having a dielectric constant of greater than or equal to 2.5 and less than 3.9, such as porous silicon oxide or porous silicon nitride), or ultra-low-k dielectric material (having a dielectric constant of less than 2.5, such as porous SiCOH).
In this embodiment, the material of the first dielectric layer 231 and the second dielectric layer 232 is silicon oxide.
Referring to fig. 10, the dummy gate layer 205 is removed (as shown in fig. 9) and the first protection layer 204 is exposed, a first opening 211 is formed in the dielectric structure 230 of the peripheral region 210, and a second opening 221 is formed in the dielectric structure 230 of the core region 220.
The process for removing the dummy gate layer 205 is one or a combination of a dry etching process and a wet etching process; wherein the dry etching process is an anisotropic dry etching process.
In this embodiment, the material of the dummy gate layer 205 is polysilicon, and the process of removing the dummy gate layer 205 is a plasma dry etching process. The parameters of the plasma dry etching process comprise: the gas comprises fluorocarbon gas, HBr and Cl2And a carrier gas, the fluorocarbon gas including CF4、CHF3、CH2F2、CH3F; the carrier gas is inert gas, for example, the gas flow of He is 50 sccm-400 sccm, and the pressure is 3 mtorr-8 mtorr.
In the plasma dry etching process, the inside of the fin portion 201 is easily damaged by the plasma with energy, and the density and hardness of the first protection layer 204 are high, so that the bombardment of the plasma can be blocked in the process of diffusing the dummy gate layer 205, and the inside of the fin portion 201 is prevented from being damaged by the plasma.
In another embodiment, the process of removing the dummy gate layer 205 is a wet etching process, and the etching solution of the wet etching process is a hydrofluoric acid solution.
Referring to fig. 11, a second passivation layer 206 is formed on the dielectric structures 230 of the core region 220 and the peripheral region 210, the sidewalls and the bottom of the first opening 211, and the sidewalls and the bottom of the second opening 221.
Forming the second passivation layer 206 on the surfaces of the core region 220 and the peripheral region 210, wherein the second passivation layer 206 completely covers the surfaces of the core region 220 and the peripheral region 210; when the first patterned layer is subsequently removed, the second protective layer 206 can prevent the first protective layer 204 made of silicon oxynitride from reacting, thereby preventing photoresist residue and damage to the film structure.
The forming process of the second protection layer 206 is one or more of a chemical vapor deposition process, a physical vapor deposition process and an atomic layer deposition process. The second passivation layer 206 can avoid reacting with the photoresist and the developing and stripping solution during the photolithography process, and therefore, the material of the second passivation layer 206 is silicon oxide or the similar material with the same characteristics.
In this embodiment, the second passivation layer 206 is made of silicon oxide and has a thickness of 10to 60 angstroms. In the subsequent process, the first gate oxide layer 203 of the core region 220 and the second protection layer 206 of the peripheral region 210 are simultaneously removed, and the thickness of the first gate oxide layer 203 and the thickness of the second protection layer 206 show a corresponding relationship.
Referring to fig. 12, a first patterned layer 240 is formed on the second passivation layer 206, and the first patterned layer 240 exposes the second passivation layer 206 in the second opening 221.
The first patterned layer 240 is a patterned photoresist layer, and the first patterned layer 240 fills the first opening 211. In this embodiment, the first patterned layer 240 also covers the surface of the dielectric structure 230.
The forming of the first patterned layer 240 includes: forming a photoresist layer on the second protection layer 206, wherein the photoresist layer fills the first opening 211 and the second opening 221; forming an initial patterning layer on the photoresist layer by adopting a mask photoetching process; after the initial patterning layer is formed, the photoresist is patterned to form a first patterning layer 240.
Referring to fig. 13, the second passivation layer 206 (shown in fig. 12) and the first passivation layer 204 (shown in fig. 12) in the second opening 221 are removed by using the first patterned layer 240 as a mask, so as to expose the first gate oxide layer 203 at the bottom of the second opening 221.
The step of removing the second protection layer 206 and the first protection layer 204 in the second opening 221 includes: removing the second passivation layer 206 in the second opening 221 using the first patterned layer 240 as a mask; the first passivation layer 204 in the second opening 221 is removed by using the first patterning layer 240 as a mask, and the first gate oxide layer 203 at the bottom of the second opening 221 is exposed.
The peripheral region 210 has low requirements for the density of the gate oxide layer and the number of internal defects, and thus the first gate oxide layer 203 of the peripheral region 210 can be reserved.
The process of removing the second protection layer 206 and the first protection layer 204 in the second opening 221 is one or two of a wet etching process and a dry etching process.
In this embodiment, the second protection layer 206 is made of silicon oxide, and the process of removing the second protection layer 206 is a wet etching process; the first protection layer 204 is made of silicon oxide, and the process for removing the first protection layer 204 is a dry etching process, which is an anisotropic dry etching process.
The process of removing the second protection layer 206 is a wet etching process. The parameters of the wet etching process comprise: the mass percentage of the hydrofluoric acid to the water is 1: 500-1: 2000, the etching time is 5-1000 seconds, and the over-etching amount is 50-300%.
In the wet etching process, silicon oxide is removed by using hydrofluoric acid, and due to the etching selectivity of hydrofluoric acid, the first protection layer 204 made of silicon oxynitride under the second protection layer 206 is not etched. Since the hydrogen and fluorine atoms are relatively strongly bonded, hydrofluoric acid cannot be completely ionized in water, and it is theoretically a weak acid in a low concentration. However, when the concentration is low, the wet etching rate is too slow, and efficient production is not utilized; when the concentration is too high, the resultant of the hydrofluoric acid reacts with the second protective layer 206 made of silicon oxide, and the resultant reacts with excessive hydrofluoric acid to generate highly acidic fluosilicic acid, which causes side reactions.
In this embodiment, the process of removing the first protection layer 204 is a dry etching process, which can be a dry etching process, and the dry etching process is an isotropic SICONI dry etching process. The SICONI dry etching process has uniform etching rate in different directions, and can uniformly remove the first protective layer 204 on the side wall and the top surface of the fin portion 201.
The parameters of the SICONI dry etching process comprise: the gas flow rate of He is 600 sccm-2000 sccm, NH3The gas flow rate of (1) is 200 sccm-500 sccm, NF3The gas flow rate of the gas is 20sccm to 200 sccm; the pressure is 2to 10torr, the etching time is 5 to 100 seconds, and the over-etching amount is 50 to 100 percent.
Referring to fig. 14, after removing the second passivation layer 206 (shown in fig. 12) and the first passivation layer 204 (shown in fig. 12) in the second opening 221, the first patterned layer 240 (shown in fig. 13) is removed.
In the present embodiment, in the process of removing the first patterned layer 240, the second protection layer 206 is used to protect the first protection layer 204, so as to prevent the first protection layer 204 made of silicon oxynitride from being damaged due to reaction. The process of removing the first patterned layer 240 is one or a combination of an ashing process and a wet process.
In this embodiment, the process of removing the first patterning layer 240 is a combination process of an ashing process and a wet process. Wherein the parameters of the ashing process include: the pressure is 50-900 mtorr, the power is 1000-2700 w, N2The gas flow rate of (A) is 500-4000 sccm, H2The gas flow rate is 50 sccm-1000 sccm, and the temperature is 80-250 ℃. Wherein, the parameters of the wet process comprise: h2SO4The volume percentage of the water and the water is 3: 1-6: 1, and the temperature is 100-130 ℃.
The ashing process is a plasma ashing process, and after ashing the first patterned layer 240 of which material is photoresist, the plasma treatment leaves a large amount of organic matter on the surface of the substrate, which requires that it must be removed by a strong oxidizing solvent. By containing H in the wet process2SO4The aqueous solution is used for removing organic matters or polymer residues caused by plasma, so that the cleanliness of the surface of the substrate is ensured, and the generation of process defects is avoided.
Referring to fig. 15, after removing the first patterned layer 240 (as shown in fig. 13), the first gate oxide layer 203 (as shown in fig. 14) at the bottom of the second opening 221 and the second passivation layer 206 (as shown in fig. 14) in the first opening 211 are removed to expose the first passivation layer 204 at the bottom of the first opening 211.
The process of removing the first gate oxide layer 203 at the bottom of the second opening 221 and the second protective layer 206 in the first opening 211 is one or a combination of a wet etching process and an isotropic dry etching process.
The first gate oxide layer 203 and the second protection layer 206 are made of silicon oxide, and a fin 201 is located below the first gate oxide layer 203 in a core region 220, and the first protection layer 204 is located below the second protection layer 206 in a peripheral region 210. The fin 201 in the core region 220 under the first gate oxide layer 203 is easily damaged by the bombardment of plasma in the dry etching process, and therefore, a wet etching process is preferably used to remove the first gate oxide layer 203 and the second protection layer 206.
In this embodiment, the process of removing the first gate oxide layer 203 and the second protective layer 206 is a wet etching process, and the parameters include: the mass percentage of the hydrofluoric acid to the water is 1: 500-1: 2000, the etching time is 5-1000 seconds, and the over-etching amount is 50-300%.
Referring to fig. 16, after removing the first gate oxide layer 203 (shown in fig. 14) at the bottom of the second opening 221 and the second protection layer 206 (shown in fig. 14) in the first opening 211, a second gate oxide layer 207 is formed at the bottom of the second opening 221.
The second gate oxide layer 207 serves as a gate oxide layer of the semiconductor device formed in the core region 220. The second gate oxide layer 207 is made of silicon oxide; the second gate oxide layer 207 is formed by a thermal oxidation process or a wet oxidation process.
The thickness of the second gate oxide layer 207 is 8 to 15 angstroms. In this embodiment, the forming process of the second gate oxide layer 207 is a thermal oxidation process. The parameters of the thermal oxidation process comprise: the time is 100-1000 seconds, the pressure is 50-300 torr, and the gas flow ratio of oxygen to nitrogen is 1/20-1/5.
Referring to fig. 17, a first gate structure filling the first opening 211 is formed on the surface of the first protection layer 204 in the peripheral region 210; a second gate structure filling the second opening 221 is formed on the surface of the second gate oxide layer 207 in the core region 220.
The first gate structure comprises a first gate dielectric layer 212 located on the first protection layer 204, and the first gate dielectric layer 212 covers the top surface of the dielectric structure 230 of the peripheral region 210 and the sidewall and the bottom surface of the first opening 211; the second gate structure includes a second gate dielectric layer 222 located on the second gate oxide layer 207, and the second gate dielectric layer 222 covers the top surface of the dielectric structure 230 of the core region 220 and the sidewall and bottom surface of the second opening 221.
The first gate dielectric layer 212 and the second gate dielectric layer 222 are made of high-k dielectric materials (the dielectric coefficient is greater than 3.9); the high-k dielectric material comprises hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide.
The first gate dielectric layer 212 and the second gate dielectric layer 222 are formed by one or more of a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In one embodiment, the first gate structure further includes a first work function layer on the surface of the first gate dielectric layer 212, and the second gate structure further includes a second work function layer on the surface of the second gate dielectric layer 222. Specifically, after the first gate dielectric layer 212 and the second gate dielectric layer 222 are formed, a first work function layer is formed on the surface of the first gate dielectric layer 212, and a second work function layer is formed on the surface of the second gate dielectric layer 222. The process steps for forming the first work function layer and the second work function layer include: forming a work function film on the surfaces of the first gate dielectric layer 212 and the second gate dielectric layer 222, wherein the work function film covers the top surface of the dielectric structure 230; the work function film is planarized until the surface of the dielectric structure 230 is exposed, forming a first work function layer and a second work function layer. The material in the first work function layer and the material in the second work function layer can be the same or different.
In summary, in the embodiment, after the second protection layer and the first protection layer in the core region are removed, the first gate oxide layer in the core region and the second protection layer in the peripheral region are exposed on the surface of the substrate at this time, and since the first gate oxide layer and the second protection layer are made of silicon oxide, the first gate oxide layer in the core region can be removed while the second protection layer in the peripheral region is removed, so that the risk that the fin portion in the core region is exposed in the etching environment is reduced, the channel region quality of the semiconductor device is improved, the leakage current is reduced, and the performance and reliability of the semiconductor device are improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a core region and a peripheral region, the substrate is provided with a dielectric structure, the dielectric structure is internally provided with a first opening and a second opening, the first opening is positioned in the peripheral region, the second opening is positioned in the core region, the substrate at the bottoms of the first opening and the second opening is respectively provided with a first gate oxide layer, and the surface of the first gate oxide layer is provided with a first protective layer;
forming a second protective layer on the dielectric structures of the core region and the peripheral region, the side wall and the bottom of the first opening and the side wall and the bottom of the second opening;
forming a first patterned layer on the second protective layer, wherein the first patterned layer exposes the second protective layer in the second opening;
removing the second protective layer and the first protective layer in the second opening by taking the first patterning layer as a mask to expose the first gate oxide layer at the bottom of the second opening;
removing the first patterned layer after removing the second protective layer and the first protective layer within the second opening;
after the first patterning layer is removed, removing the first gate oxide layer at the bottom of the second opening and the second protective layer in the first opening to expose the first protective layer at the bottom of the first opening;
and after removing the first gate oxide layer at the bottom of the second opening and the second protective layer in the first opening, forming a second gate oxide layer at the bottom of the second opening.
2. The method for forming a semiconductor device according to claim 1, wherein the substrate comprises: the semiconductor device comprises a substrate and an isolation layer located on the substrate, wherein a fin portion is arranged on the substrate, the isolation layer covers part of the side wall of the fin portion, and the top of the isolation layer is lower than that of the fin portion.
3. The method for forming a semiconductor device according to claim 2, wherein a material of the isolation layer is silicon oxide.
4. The method for forming a semiconductor device according to claim 1, wherein the step of forming the first gate oxide layer and the first protective layer comprises: forming an initial first gate oxide layer on the surface of the substrate before forming the dielectric structure, the first opening and the second opening; and carrying out surface treatment on the initial first gate oxide layer to form a first gate oxide layer and a first protective layer positioned on the surface of the first gate oxide layer.
5. The method for forming a semiconductor device according to claim 4, wherein the first gate oxide layer is formed using silicon oxide.
6. The method of forming a semiconductor device according to claim 5, wherein the forming process of the initial first gate oxide layer is an in-situ steam generation process.
7. The method for forming a semiconductor device according to claim 6, wherein the surface treatment step includes: performing a decoupling plasma nitridation process on the surface of the initial first gate oxide layer to form an initial protective layer on the surface of the first gate oxide layer; and carrying out annealing process on the initial protection layer to form a first protection layer.
8. The method of forming a semiconductor device of claim 1, wherein the step of forming the first opening and the second opening within the dielectric structure comprises: forming a pseudo gate structure on the substrate of the core region and the substrate of the peripheral region respectively, wherein the pseudo gate structure comprises a pseudo gate layer, and the pseudo gate layer is positioned on the first protective layer; forming a source region and a drain region which are respectively positioned in the substrate at two sides of the pseudo gate structure; forming a dielectric structure on the substrate, wherein the dielectric structure covers the side wall of the pseudo gate structure and exposes the top of the pseudo gate layer; and removing the pseudo gate layer and exposing the first protective layer, forming a first opening in the dielectric structure of the peripheral region, and forming a second opening in the dielectric structure of the core region.
9. The method of forming a semiconductor device of claim 8, wherein the dummy gate structure further comprises: and the side wall is positioned on the side wall of the pseudo gate layer.
10. The method of forming a semiconductor device of claim 8, wherein the dielectric structure comprises: the first dielectric layer and the second dielectric layer are positioned on the first dielectric layer.
11. The method for forming a semiconductor device according to claim 10, wherein hardness of the second dielectric layer is higher than hardness of the first dielectric layer.
12. The method for forming a semiconductor device according to claim 8, wherein a process of removing the dummy gate layer is one or a combination of a wet etching process and a dry etching process.
13. The method of forming a semiconductor device according to claim 1, wherein the step of removing the second protective layer and the first protective layer in the second opening using the first patterned layer as a mask comprises: the first patterned layer fills the first opening, and is also positioned above the dielectric structure of the peripheral region; removing the second protective layer of the core region by taking the first patterning layer as a mask until the first protective layer of the second opening is exposed; after removing the second protective layer of the core region, removing the first protective layer in the second opening until the first gate oxide layer on the substrate of the second opening is exposed; after removing the first protective layer within the second opening, the first patterned layer is removed.
14. The method for forming a semiconductor device according to claim 13, wherein a material of the first protective layer is silicon oxynitride.
15. The method for forming a semiconductor device according to claim 13, wherein a material of the second protective layer is silicon oxide.
16. The method for forming a semiconductor device according to claim 15, wherein a process for forming the second protective layer is an atomic layer deposition process.
17. The method for forming a semiconductor device according to claim 13, wherein the process for removing the second protective layer is a wet etching process, and process parameters of the wet etching process include: the mass percentage of the hydrofluoric acid to the water is 1: 500-1: 2000, the etching time is 5-1000 seconds, and the over-etching amount is 50-300%.
18. The method for forming a semiconductor device according to claim 13, wherein the process for removing the first protective layer is a dry etching process, and process parameters of the dry etching process include: the gas flow rate of He is 600 sccm-2000 sccm, NH3The gas flow rate of (1) is 200 sccm-500 sccm, NF3The gas flow rate of the gas is 20sccm to 200 sccm; the pressure is 2to 10torr, the etching time is 5 to 100 seconds, and the over-etching amount is 50 to 100 percent.
19. The method for forming a semiconductor device according to claim 1, wherein a first gate structure filling the first opening is formed on a surface of the first protective layer in the peripheral region; and forming a second gate structure filling the second opening on the surface of the second gate oxide layer of the core region.
20. A semiconductor device formed according to the method of any one of claims 1 to 19.
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