CN107978514B - Transistor and forming method thereof - Google Patents
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- CN107978514B CN107978514B CN201610919492.3A CN201610919492A CN107978514B CN 107978514 B CN107978514 B CN 107978514B CN 201610919492 A CN201610919492 A CN 201610919492A CN 107978514 B CN107978514 B CN 107978514B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
A transistor and a forming method thereof are provided, the forming method comprises the following steps: forming a substrate including a core region and a peripheral region; forming a first dummy gate structure and a second dummy gate structure on the substrate of the core region and the substrate of the peripheral region respectively, wherein the first dummy gate structure comprises a first gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure comprises a second gate oxide layer and a second dummy gate electrode layer; removing the first dummy gate electrode layer and the second dummy gate electrode layer, and forming a first opening and a second opening in the dielectric layer on the substrate between the dummy gate structures; forming a first barrier layer covering the side wall, the bottom and the core area dielectric layer of the first opening and a second barrier layer covering the side wall, the bottom and the peripheral area dielectric layer of the second opening; forming a photoresist pattern which fills the second opening and covers the peripheral area; removing the first gate oxide layer and the first barrier layer; removing the photoresist pattern; removing the second barrier layer; a gate structure is formed within the first opening and within the second opening. The formation method can improve the electrical performance of the transistor.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a transistor and a method for forming the same.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease as very large scale integrated circuits are developed. To accommodate the reduction in feature size, the channel length of MOSFET devices has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.
Therefore, to better accommodate the reduction in feature size, semiconductor processing is gradually beginning to transition from planar MOSFET transistors to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). The gate of a FinFET may control the ultra-thin body (fin) from at least two sides. Compared with a planar MOSFET device, the planar MOSFET device has stronger control capability on a channel, thereby being capable of well inhibiting a short-channel effect.
The finfet is mainly divided into a Core (Core) device and an Input and output (I/O) device according to functional distinction. The core device comprises a core MOS device, and the input and output devices comprise input and output MOS devices. Typically, the input-output device operating voltage is much greater than the core device operating voltage. In order to prevent the problems of electrical breakdown and the like, the larger the working voltage of the device is, the thicker the thickness of the gate dielectric layer of the device is required to be, and therefore, the thickness of the gate dielectric layer of the input and output device is usually larger than that of the gate dielectric layer of the core device.
However, the electrical performance of transistors formed by the prior art is still to be improved.
Disclosure of Invention
The invention provides a transistor and a forming method thereof, which can improve the electrical property of the transistor.
In order to solve the above problems, the present invention provides a method for forming a transistor, including: forming a substrate including a core region for forming a core device and a peripheral region for forming an input-output device; forming a plurality of dummy gate structures on the substrate, wherein a first dummy gate structure is positioned on the substrate in the core region, and a second dummy gate structure is positioned on the substrate in the peripheral region, the first dummy gate structure comprises a first gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure comprises a second gate oxide layer and a second dummy gate electrode layer; forming a dielectric layer on the substrate between the first pseudo gate structure and the second pseudo gate structure; removing the first dummy gate electrode layer and the second dummy gate electrode layer, and forming a first opening exposing the first gate oxide layer and a second opening exposing the second gate oxide layer in the dielectric layer; forming a barrier layer covering the side wall and the bottom of the first opening, the side wall and the bottom of the second opening and the dielectric layer, wherein the first barrier layer is positioned in the core area, and the second barrier layer is positioned in the peripheral area; forming a photoresist pattern which fills the second opening and covers the peripheral area; removing the first gate oxide layer and the first barrier layer by taking the photoresist pattern as a mask; removing the photoresist pattern; after removing the photoresist pattern, removing the second barrier layer to expose the second gate oxide layer at the bottom of the second opening; forming a metal layer in the first opening and the second opening, wherein the metal layer in the first opening is used for forming a first grid structure; the second gate oxide layer and the metal layer in the second opening are used for forming a second gate structure.
Optionally, the barrier layer is an oxide layer.
Optionally, the barrier layer is a silicon oxide layer.
Optionally, the preparation method of the silicon oxide layer is atomic layer deposition.
Optionally, the atomic layer deposition process parameters are as follows: the growth temperature is 80-300 deg.C, the pressure in the chamber is 5mTorr-20Torr, and the growth time is 5-100 cycles.
Optionally, the thickness of the barrier layer is
Optionally, the step of removing the first gate oxide layer and the first barrier layer includes: and removing by adopting a SiCoNi etching process or a diluted hydrofluoric acid solution.
Optionally, the process parameters of the SiCoNi etching process include: the flow rate of helium gas is 600sccm to 2000sccm, the flow rate of nitrogen trifluoride gas is 20sccm to 200sccm, the flow rate of ammonia gas is 200sccm to 500sccm, the pressure of the chamber is 2Torr to 10Torr, and the process time is 20s to 400 s.
Optionally, the volume concentration percentage of hydrofluoric acid in the hydrofluoric acid solution is 0.05% -0.2%.
Optionally, the step of removing the photoresist pattern includes: and removing the photoresist pattern by adopting an ashing process.
Optionally, the forming method further includes: before removing the second barrier layer, forming a sacrificial layer at the bottom of the first opening; and in the step of removing the second barrier layer, the sacrificial layer at the bottom of the first opening is also removed.
Optionally, the sacrificial layer is a silicon oxide layer.
Optionally, the thickness of the sacrificial layer is
Optionally, the step of removing the sacrificial layer and the second barrier layer includes: and (4) adopting a diluted hydrofluoric acid solution to perform a removing step.
Optionally, after the first opening and the second opening are formed, nitrogen doping is performed on the first gate oxide layer exposed by the first opening and the second gate oxide layer exposed by the second opening.
Accordingly, the invention provides a transistor formed by the formation method.
Correspondingly, the invention also provides a transistor, comprising: a substrate including a core region having a core device and a peripheral region having an input-output device; the dielectric layer is positioned on the substrate and is internally provided with a first opening penetrating through the dielectric layer in the core area and a second opening penetrating through the dielectric layer in the peripheral area; the first gate oxide layer is positioned at the bottom of the first opening; the second gate oxide layer is positioned at the bottom of the second opening; the blocking layer is positioned on the side wall of the first opening, the first gate oxide layer, the side wall of the second opening, the second gate oxide layer and the top of the dielectric layer, the blocking layer positioned in the core area is the first blocking layer, and the blocking layer positioned in the peripheral area is the second blocking layer.
Optionally, the barrier layer is an oxide layer.
Optionally, the barrier layer is a silicon oxide layer.
Optionally, the thickness of the barrier layer is
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the forming method of the transistor, the barrier layers are formed on the side wall and the bottom of the first opening and the side wall and the bottom of the second opening, the photoresist patterns which fill the second opening and cover the peripheral area are formed, the barrier layers are removed after the photoresist patterns are removed, and the photoresist residues are removed in the process of removing the barrier layers, so that the photoresist patterns are removed more thoroughly and are not easy to remain, and the electrical performance of the transistor is improved.
In addition, the second gate oxide layer can be used as a part of the second gate structure in the subsequent process, and the formation of the barrier layer can reduce the reaction of the second gate oxide layer and a photoresistance pattern and reduce photoresistance residues, so that the quality of the second gate structure is improved, the electrical performance of a transistor is improved, and the yield of devices is improved.
The invention provides a transistor formed by adopting the forming method, and the photoresistance residue on the second gate oxide layer of the transistor is less, so the electrical property of the transistor can be improved.
The invention also provides a transistor which comprises a blocking layer positioned on the side wall of the first opening, the first gate oxide layer, the side wall of the second opening, the second gate oxide layer and the top of the dielectric layer.
Drawings
Fig. 1 to 6 are schematic structural diagrams corresponding to steps of a method for forming a transistor;
fig. 7 to 17 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a transistor according to the present invention.
Detailed Description
As can be seen from the background, the electrical performance of transistors formed by the prior art still remains to be improved. The reason why the electrical performance of the transistor is poor is analyzed in combination with the forming method in the prior art. Referring to fig. 1 to 6, schematic structural diagrams corresponding to steps of a method for forming a transistor are shown. The forming method of the transistor comprises the following steps:
referring to fig. 1, a substrate 100 is formed, the substrate 100 including a core region i and a peripheral region ii. The substrate 100 in the core region i has a first fin 110 thereon, and the substrate 100 in the peripheral region ii has a second fin 120 thereon.
Referring to fig. 2, fig. 2 is a schematic cross-sectional view along the extending direction of the first fin 110 and the second fin 120, and a first dummy gate structure (not shown) crossing the first fin 110 and covering a portion of the top and sidewall surfaces of the first fin 110, and a second dummy gate structure (not shown) crossing the second fin 120 and covering a portion of the top and sidewall surfaces of the second fin 120 are formed on the substrate 100. The first dummy gate structure comprises a first gate oxide layer 111 located on the surface of the first fin portion 110 and a first dummy gate electrode layer 112 located on the first gate oxide layer 111, and the second dummy gate structure comprises a second gate oxide layer 121 located on the surface of the second fin portion 120 and a second dummy gate electrode layer 122 located on the second gate oxide layer 121.
With reference to fig. 2, a first source-drain doped region 113 is formed in the first fin 110 on both sides of the first dummy gate structure, and a second source-drain doped region 123 is formed in the second fin 120 on both sides of the second dummy gate structure. A dielectric layer 130 covering the first dummy gate structure, the second dummy gate structure, the first source-drain doped region 113 and the second source-drain doped region 123 is further formed on the substrate 100.
Referring to fig. 3, the first dummy gate electrode layer 112 (shown in fig. 2) and the second dummy gate electrode layer 122 (shown in fig. 2) are etched away, and a first opening 200 exposing the first gate oxide layer 111 and a second opening 210 exposing the second gate oxide layer 121 are formed in the dielectric layer 130; and performing plasma nitridation treatment on the first gate oxide layer 111 exposed from the first opening 200 and the second gate oxide layer 121 exposed from the second opening 210.
Referring to fig. 4, forming a photoresist pattern 300 covering the peripheral region ii, and etching and removing the first gate oxide layer 111 at the bottom of the first opening 200 by using the photoresist pattern 300 as a mask (as shown in fig. 3); the photoresist pattern 300 is removed.
Referring to fig. 5, an interface layer 115 is formed at the bottom of the first opening 200; and forming a gate dielectric layer 140 on the interface layer 115 at the bottom of the first opening 200, on the side wall of the first opening 200, on the second gate oxide layer 121 at the bottom of the second opening 210, and on the side wall of the second opening 210.
Referring to fig. 6, the first opening 200 (shown in fig. 5) and the second opening 210 (shown in fig. 5) are filled with metal to form a metal layer 150, the interfacial layer 115, the gate dielectric layer 140 and the metal layer 150 in the core region i form a first gate structure 116, and the second gate oxide layer 121, the gate dielectric layer 140 and the metal layer 150 in the peripheral region ii form a second gate structure 126.
In the forming method of the transistor in the prior art, the plasma nitridation treatment is performed on the second gate oxide layer 121, so that the reliability performance of the transistor on time-dependent dielectric breakdown is improved, however, when the nitrogen content of the second gate oxide layer 121 is high (for example, more than 15%), amino groups in the second gate oxide layer 121 are likely to react with the photoresist pattern 300, and therefore, in the process of removing the photoresist pattern 300, the photoresist pattern 300 which reacts with the amino groups is difficult to be removed, so that photoresist residue is caused, and the electrical performance of the transistor is further affected.
In addition, the amino group in the second gate oxide layer 121 reacts with the photoresist pattern 300, photoresist residue is easily left on the surface of the second gate oxide layer 121, and the performance of the gate dielectric layer 140 formed on the second gate oxide layer 121 is affected, thereby affecting the electrical performance of the transistor.
In order to solve the above technical problem, the present invention provides a method for forming a transistor, including: forming a substrate comprising a core region and a peripheral region; forming a plurality of dummy gate structures on a substrate, wherein a first dummy gate structure is positioned on the substrate of a core region, and a second dummy gate structure is positioned on the substrate of a peripheral region, the first dummy gate structure comprises a first gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure comprises a second gate oxide layer and a second dummy gate electrode layer; forming a dielectric layer on the substrate between the first pseudo gate structure and the second pseudo gate structure; removing the first dummy gate electrode layer and the second dummy gate electrode layer, and forming a first opening exposing the first gate oxide layer and a second opening exposing the second gate oxide layer in the dielectric layer; forming a barrier layer covering the side wall and the bottom of the first opening, the side wall and the bottom of the second opening and the dielectric layer, wherein the first barrier layer is positioned in the core area, and the second barrier layer is positioned in the peripheral area; forming a photoresist pattern which fills the second opening and covers the peripheral area; removing the first gate oxide layer and the first barrier layer by taking the photoresist pattern as a mask; removing the photoresist pattern; after removing the photoresist pattern, removing the second barrier layer to expose the second gate oxide layer at the bottom of the second opening; forming a metal layer in the first opening and the second opening, wherein the metal layer in the first opening is used for forming a first grid structure; the second gate oxide layer and the metal layer in the second opening are used for forming a second gate structure.
In the invention, the barrier layer is formed on the side wall and the bottom of the second opening and the dielectric layer, the photoresist pattern which fills the second opening and covers the peripheral area is formed, the barrier layer is removed after the photoresist pattern is removed, and the photoresist remains in the process of removing the barrier layer and is removed together, so that the photoresist pattern is removed more thoroughly and is not easy to remain, and the electrical performance of the transistor is improved.
In addition, the second gate oxide layer can be used as a part of the second gate structure in the subsequent process, and the formation of the barrier layer can reduce the reaction of the second gate oxide layer and the photoresistive pattern, so that the quality of the second gate structure is improved, and the electrical performance of the transistor is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 7 to 17 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a transistor according to the present invention. The present embodiment takes a finfet as an example. However, the forming method of the present invention can be applied to other semiconductor devices.
Referring to fig. 7 and 8 in combination, respectively, a perspective view of a transistor and a schematic cross-sectional structure along the direction of AA1 (shown in fig. 7) are shown, and a substrate 400 is formed, wherein the substrate 400 includes a core region i (refer to fig. 8) for forming a core device and a peripheral region ii (refer to fig. 8) for forming an input-output device.
In this embodiment, the substrate 400 in the core region i has a first fin 410 thereon, and the substrate 400 in the peripheral region ii has a second fin 420 thereon.
The substrate 400 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 400 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the first fin 410 and the second fin 420 are made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 400 is a silicon substrate, and the first fin portion 410 and the second fin portion 420 are made of silicon.
Specifically, the step of forming the substrate 400 includes: providing an initial substrate, and forming a hard mask layer (not shown) on the initial substrate; etching the initial substrate by taking the hard mask layer as a mask to form a plurality of discrete protrusions; the protrusion is a fin portion, the etched initial substrate is used as a substrate 400, the fin portion located in the core region i is a first fin portion 410, and the fin portion located in the peripheral region ii is a second fin portion 420.
It should be noted that, in this embodiment, after the first fin portion 410 and the second fin portion 420 are formed, an isolation structure 401 is further formed on the surface of the substrate 400.
The isolation structure 401 is used for electrical isolation between adjacent fins and between the core region i and the peripheral region ii, and the isolation structure 401 may be made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the isolation structure 401 is made of silicon oxide.
In this embodiment, the isolation structure 401 is a shallow trench isolation structure. In other embodiments, the isolation structure may also be a local silicon oxide isolation structure.
Referring to fig. 9, fig. 9 is a schematic cross-sectional view along BB1 (shown in fig. 7), wherein a plurality of dummy gate structures are formed on the substrate 400, a first dummy gate structure is located on the substrate 400 in the core region i, and a second dummy gate structure is located on the substrate 400 in the peripheral region ii.
The first dummy gate structure and the second dummy gate structure occupy space positions for the first gate structure and the second gate structure which are formed subsequently.
In this embodiment, the first dummy gate structure crosses over the first fin 410 and covers part of the top and the side wall surface of the first fin 410, and includes a first gate oxide layer 411 and a first dummy gate electrode layer 412, and the second dummy gate structure crosses over the second fin 420 and covers part of the top and the side wall surface of the second fin 420, and includes a second gate oxide layer 421 and a second dummy gate electrode layer 422.
Specifically, the step of forming the first and second dummy gate structures includes: forming a dummy gate oxide film covering the first fin portion 410 and the second fin portion 420; forming a dummy gate electrode film on the dummy gate oxide film; carrying out planarization treatment on the dummy gate electrode film; forming a first pattern layer (not shown) on the dummy gate electrode film; and with the first pattern layer as a mask, patterning the dummy gate electrode film and the dummy gate oxide film, forming a first gate oxide layer 411 on the first fin portion 410, and forming a first dummy gate electrode layer 412 on the first gate oxide layer 411, wherein the first dummy gate electrode layer 412 spans across the first fin portion 410. Forming a second gate oxide layer 421 on the second fin portion 420, forming a second dummy gate electrode layer 422 on the second gate oxide layer 421, wherein the second dummy gate electrode layer 422 crosses over the second fin portion 420, the first gate oxide layer 411 and the first dummy gate electrode layer 412 form a first dummy gate structure, and the second gate oxide layer 421 and the second dummy gate electrode layer 422 form a second dummy gate structure; and etching to remove the first pattern layer.
The material of the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422 may be polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, or amorphous carbon. In this embodiment, the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422 are made of polysilicon, and the first gate oxide layer 411 and the second gate oxide layer 421 are made of silicon oxide.
In this embodiment, the forming process of the first gate oxide layer 411 and the second gate oxide layer 421 is an In-situ steam Generation oxidation (ISSG) process.
After the first dummy gate structure and the second dummy gate structure are formed, the method for forming the transistor further includes: a first side wall layer 413 is formed on the first dummy gate structure side wall, and a second side wall layer 423 is formed on the second dummy gate structure side wall.
The material of the first sidewall layer 413 and the second sidewall layer 423 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, or boron carbonitride. In this embodiment, the material of the first sidewall layer 413 and the second sidewall layer 423 is silicon nitride.
It should be noted that, after the first dummy gate structure and the second dummy gate structure are formed, the forming method further includes: and forming a first source-drain doped region (not marked) in the first fin portion 410 on two sides of the first dummy gate structure, and forming a second source-drain doped region (not marked) in the second fin portion 420 on two sides of the second dummy gate structure.
Specifically, the step of forming the first source-drain doped region includes: forming a first stress layer 414 in the first fin portion 410 on two sides of the first dummy gate structure, and forming a first source drain doped region in the first stress layer 414 by adopting an in-situ doping mode; the step of forming the second source-drain doped region comprises the following steps: and forming a second stress layer 424 in the second fin part 420 at two sides of the second pseudo gate structure, and forming a second source-drain doped region in the second stress layer 424 in an in-situ doping manner.
Referring to fig. 10, a dielectric layer 460 is formed on the substrate 400 between the first dummy gate structure and the second dummy gate structure.
In this embodiment, the dielectric layer 460 is located on the isolation structure 401 and on a portion of the first fin portion 410 and a portion of the second fin portion 420, the dielectric layer 460 further covers the first source-drain doping region and the second source-drain doping region, and the dielectric layer 460 exposes the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422.
In this embodiment, the dielectric layer 460 is a stacked structure, and includes a first dielectric layer 440 on the substrate 400, and a second dielectric layer 450 on the first dielectric layer 440.
The first dielectric layer 440 and the second dielectric layer 450 are made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the first dielectric layer 440 and the second dielectric layer 450 are made of silicon oxide.
Referring to fig. 11, the first dummy gate electrode layer 412 (refer to fig. 10) and the second dummy gate electrode layer 422 (refer to fig. 10) are removed, and a first opening 600 exposing the first gate oxide layer 411 and a second opening 610 exposing the second gate oxide layer 421 are formed in the dielectric layer 460.
In this embodiment, in the same process step, the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422 are etched and removed. Specifically, the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422 are etched away using a maskless etching process.
In this embodiment, the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422 are removed by etching using a dry etching process, and the etching process has a high etching selection ratio for the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422, so that the dielectric layer 460 is not damaged while the first dummy gate electrode layer 412 and the second dummy gate electrode layer 422 are removed by etching.
In this embodiment, the method for forming the transistor further includes: after the first opening 600 and the second opening 610 are formed, the first gate oxide layer 411 and the second gate oxide layer 421 are subjected to a nitrogen doping process.
The nitrogen doping treatment is used for nitriding the first gate oxide layer 411 and the second gate oxide layer 421, so that interface state charges of the first gate oxide layer 411 and the second gate oxide layer 421 are reduced, the surface uniformity of the first gate oxide layer 411 and the second gate oxide layer 421 is improved, and the time-dependent dielectric breakdown reliability performance of the semiconductor device is improved.
Specifically, the nitrogen doping process used in this embodiment is a plasma nitridation process.
Referring to fig. 12, a barrier layer (not labeled) is formed covering the sidewalls and bottom of the first opening 600, the sidewalls and bottom of the second opening 610, and the dielectric layer 460.
The first barrier layer 416 is located in the core region i, and the second barrier layer 426 is located in the peripheral region ii.
The second blocking layer 426 is used for reducing photoresist residues in the peripheral region ii, and the second blocking layer 426 can also reduce the reaction of the second gate oxide 421 and the photoresist pattern, so as to reduce the photoresist residues, thereby improving the quality of a subsequently formed second gate structure, further improving the electrical performance of a transistor, and improving the yield of devices.
Accordingly, the blocking layer is formed using a material that can be formed on the first gate oxide layer 411 and the second gate oxide layer 421 and can be removed. The blocking layer may be an oxide layer, and in this embodiment, the blocking layer is a silicon oxide layer. The silicon oxide layer is easy to form and remove, and the silicon oxide layer can be removed by conventional dry etching or wet etching, so that the method has better process compatibility with the existing process, and the process difficulty is reduced.
In this embodiment, an atomic layer deposition process is used to prepare the silicon oxide layer. The specific process parameters are as follows: the growth temperature is 80-300 deg.C, the pressure in the chamber is 5mTorr-20Torr, and the growth time is 5-100 cycles. The silicon oxide layer is grown at a lower temperature, so that the realization difficulty and the cost of the process are reduced, and meanwhile, the influence of the lower growth temperature on other parts of the transistor is smaller, so that the influence on the electrical performance of the transistor is smaller.
It should be noted that, if the blocking layer is too thin, the blocking layer is difficult to perform a function of better blocking the reaction between the second gate oxide 421 and the photoresist pattern, and it is difficult to reduce the photoresist residue during the process of removing the photoresist pattern, so that it is difficult to improve the electrical performance of the transistor. If the barrier layer is too thick, the cost and difficulty of removing the barrier layer by the subsequent removal process may be increased. Thus, in this embodiment, the barrierThe thickness of the layer is
Referring to fig. 13, a photoresist pattern 520 filling the second opening 610 (refer to fig. 12) and covering the peripheral region ii is formed.
On one hand, the photoresist pattern 520 is used as a mask in the subsequent process of removing the first gate oxide layer 411 and the first barrier layer 416, on the other hand, the photoresist pattern 520 can also be used as a protective layer for the bottom and the side wall of the second opening 610, so that the bottom and the side wall of the second opening 610 are prevented from being damaged by a removing process in the subsequent process of removing the first gate oxide layer 411 and the first barrier layer 416, and a subsequently formed second gate structure is damaged, and the electrical performance of the transistor is further reduced.
Specifically, the step of forming the photoresist pattern 520 includes: the second opening 610 is filled with photoresist by spin coating, and the dielectric layer 460 in the peripheral region II is covered, and then the photoresist is soft-dried to form a solid film. Then, the wafer coated with the photoresist is exposed and developed to form a photoresist pattern 520. In addition, in order to obtain better lithography effect and reduce reflection during lithography, the photoresist pattern 520 may further include a Bottom Anti-reflection Coating (BARC).
It should be noted that the second blocking layer 426 can reduce the reaction between the second gate oxide 421 and the photoresist pattern 520, and reduce the photoresist residue, so as to improve the quality of the subsequently formed second gate structure, further improve the electrical performance of the transistor, and improve the yield of the device.
Referring to fig. 14, the first gate oxide layer 411 (refer to fig. 13) and the first barrier layer 416 (refer to fig. 13) are removed using the photoresist pattern 520 as a mask.
Because the core region I is used for forming a core device, the peripheral region II is used for forming an input/output device, the working voltage of the core device is lower than that of the input/output device, and in order to prevent the problems of electric breakdown and the like, when the working voltage of the device is higher, the thickness of a gate dielectric layer of the device is required to be thicker, namely, the thickness of the gate dielectric layer of the subsequently formed core device is smaller than that of the gate dielectric layer of the input/output device. For this reason, in this embodiment, before forming the gate dielectric layer, the first gate oxide layer 411 (as shown in fig. 13) at the bottom of the first opening 600 is removed, and the second gate oxide layer 421 at the bottom of the second opening 610 is remained, where the second gate oxide layer 421 serves as a part for forming a second gate structure subsequently.
Specifically, the step of removing the first gate oxide layer 411 and the first barrier layer 416 includes: and removing by adopting a SiCoNi etching process or a diluted hydrofluoric acid solution.
In this embodiment, a SiCoNi etching process is used to perform the removal step. The SiCoNi etching process comprises the following steps: helium is used as a diluent gas, and nitrogen trifluoride and ammonia gas are used as reaction gases to generate etching gas; removing the first barrier layer 416 and the first gate oxide layer 411 by etching gas to form a byproduct; carrying out an annealing process to sublimate and decompose the by-product into a gaseous product; and removing the gaseous product by air suction.
Specifically, the technological parameters of the SiCoNi etching process include: the flow rate of helium gas is 600sccm to 2000sccm, the flow rate of nitrogen trifluoride gas is 20sccm to 200sccm, the flow rate of ammonia gas is 200sccm to 500sccm, the pressure of the chamber is 2Torr to 10Torr, and the process time is 20s to 400 s.
In other embodiments, a hydrofluoric acid solution may be further used to remove the first barrier layer and the first gate oxide layer, and in order to achieve a good removal effect and reduce damage to the transistor in the removal process, the hydrofluoric acid solution has a hydrofluoric acid volume concentration of 0.05% to 0.2%.
Referring to fig. 15, the photoresist pattern 520 (refer to fig. 14) is removed.
In this embodiment, an ashing process is used to remove the photoresist pattern 520. Specifically, the ashing process uses a plasma gas containing oxygen radicals or oxygen ions to remove the photoresist pattern 520.
In other embodiments, the photoresist pattern may be removed by wet cleaning.
Referring to fig. 16, after removing the photoresist pattern 520, the second barrier layer 426 (refer to fig. 15) is removed to expose the second gate oxide 421 at the bottom of the second opening 610.
In the process of removing the second barrier layer 426, the photoresist residue on the surface of the second barrier layer 426 and the second barrier layer 426 can be removed together, so that the photoresist residue is reduced, and the performance of the transistor is improved.
In this embodiment, the method for forming the transistor further includes: forming a sacrificial layer (not shown) at the bottom of the first opening 600 before removing the second barrier layer 426; in the step of removing the second barrier layer 426, the sacrificial layer at the bottom of the first opening 600 is also removed.
In the process of removing the second barrier layer 426, the sacrificial layer may reduce damage to the substrate 400 at the bottom of the first opening 600, so as to improve the quality of a subsequently formed first gate structure, and further improve the electrical performance of the transistor, and in the process of removing the second barrier layer 426, the sacrificial layer at the bottom of the first opening 600 and the second barrier layer 426 at the bottom of the second opening may be removed together, which does not increase the complexity of the removal process, and has good compatibility with the existing removal process.
In addition, since defects are generated on the substrate 400 at the bottom of the first opening 600 in the process of removing the first gate oxide layer 411 and the first barrier layer 416, the defects can be oxidized by forming a sacrificial layer at the bottom of the first opening 600, and the defects and the sacrificial layer can be removed together in the process of subsequently removing the sacrificial layer, so that the uniformity and the integrity of the substrate 400 at the bottom of the first opening 600 are improved, the quality of a subsequently formed first gate structure is improved, and the electrical performance of the transistor is improved.
In this embodiment, the sacrificial layer formed at the bottom of the first opening 600 is a silicon oxide layer. Specifically, the step of forming the sacrificial layer includes: by the inclusion of H2O2Forms a silicon oxide layer at the bottom of the first opening 600.
If the thickness of the sacrificial layer is too thick, the substrate 400 at the bottom of the first opening 600 is excessively consumed, and the cost and difficulty of subsequently removing the sacrificial layer are increased. If the sacrificial layer is too thin, it is difficultThe defects at the bottom of the first opening 600 are completely oxidized, so that it is difficult to completely remove the defects through a subsequent sacrificial layer removing process, and it is difficult to obtain the bottom of the first opening 600 with improved uniformity and good integrity. Therefore, in this embodiment, the thickness of the sacrificial layer is
In this embodiment, the step of removing the sacrificial layer and the second barrier layer 426 includes: and (4) adopting a diluted hydrofluoric acid solution to perform a removing step.
In order to achieve a good removal effect and reduce damage to the transistor in the removal process, in this embodiment, the hydrofluoric acid solution has a hydrofluoric acid volume concentration percentage of 0.05% to 0.2%.
Referring to fig. 17, a metal layer 404 is formed in the first opening 600 (refer to fig. 16) and the second opening 610 (refer to fig. 16).
The material of the metal layer 404 may be copper, tungsten, aluminum or silver, and in this embodiment, the metal layer 404 is tungsten.
Before forming the metal layer 404 in the first opening 600 and the second opening 610, the method for forming the transistor further includes: forming an interfacial layer 418 (IL) at the bottom of the first opening 600; a gate dielectric layer 403 is formed on the interface layer 418 at the bottom of the first opening 600 and the second gate oxide 421 at the bottom of the second opening 610.
The interface layer 418, the gate dielectric layer 403 and the metal layer 404 in the first opening 600 form a first gate structure 700, and the second gate oxide 421, the gate dielectric layer 403 and the metal layer 404 in the second opening form a second gate structure 701.
In this embodiment, the interface layer 418 is made of silicon oxide and is formed by a thermal oxidation process. Since the interface layer 418 is subsequently used to form the first gate structure 700, the thickness of the interface layer 418 is less than the thickness of the second gate oxide 421 of the second gate structure.
The gate dielectric layer 403 comprises a high-K dielectric layer formed of a high-K dielectric material (having a dielectric coefficient greater than 3.9). The high-K dielectric material comprises hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide or aluminum oxide. In this embodiment, the gate dielectric layer 403 is made of titanium oxide.
In this embodiment, a barrier layer (not labeled) is formed on the sidewall and the bottom of the first opening 600 (shown in fig. 12) and the sidewall and the bottom of the second opening 610 (shown in fig. 12), and then a photoresist pattern 520 (shown in fig. 13) filling the second opening 610 and covering the peripheral region ii is formed, after the photoresist pattern 520 is removed, the barrier layer is removed, and photoresist residues are removed in the process of removing the barrier layer, so that the photoresist pattern 520 is removed more thoroughly and is not easy to remain, thereby improving the electrical performance of the transistor; in addition, since the second gate oxide 421 is used as a part of the second gate structure 701 (as shown in fig. 17) in the subsequent process, the formation of the blocking layer can reduce the reaction between the second gate oxide 421 and the photoresist pattern 520, and reduce the photoresist residue, thereby improving the quality of the second gate structure 701, further improving the electrical performance of the transistor, and improving the yield of the device.
With continued reference to fig. 17, a schematic diagram of the structure of one embodiment of the transistor of the present invention is shown. Accordingly, the present invention provides a transistor formed by the formation method described in the foregoing embodiment.
Since the photoresist residue on the second gate oxide layer 421 of the transistor is less, the electrical performance of the transistor can be improved.
Referring to fig. 12 in combination, a schematic diagram of a transistor according to an embodiment of the present invention is shown. Correspondingly, the invention also provides a transistor, comprising:
a substrate 400 including a core region I having a core device and a peripheral region II having an input-output device;
a dielectric layer 460 located on the substrate 400, wherein the dielectric layer 460 has a first opening 600 penetrating through the dielectric layer 460 in the core region i and a second opening 610 penetrating through the dielectric layer 460 in the peripheral region ii;
a first gate oxide layer 411 located at the bottom of the first opening 600;
a second gate oxide 421 located at the bottom of the second opening 610;
and the barrier layers (not marked) are positioned on the side wall of the first opening 600, the first gate oxide layer 411, the side wall of the second opening 610, the second gate oxide layer 421 and the top of the dielectric layer 460, the barrier layer positioned in the core area I is the first barrier layer 416, and the barrier layer positioned in the peripheral area II is the second barrier layer 426.
In this embodiment, the transistor is a finfet, and thus the substrate 400 has a fin. Specifically, the substrate 400 in the core region i has a first fin 410 thereon, and the substrate 400 in the periphery region ii has a second fin 420 thereon.
The substrate 400 is made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate 400 can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate; the first fin 410 and the second fin 420 are made of silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 400 is a silicon substrate, and the first fin portion 410 and the second fin portion 420 are made of silicon.
In this embodiment, the transistor further includes: isolation structures 401 on the substrate 400 between adjacent ones of the fins.
The isolation structure 401 is used for electrically isolating adjacent fins and the core region i and the peripheral region ii, and the isolation structure 401 may be made of silicon oxide, silicon nitride or silicon oxynitride. In this embodiment, the isolation structure 401 is made of silicon oxide.
In this embodiment, the isolation structure 401 is a shallow trench isolation structure. In other embodiments, the isolation structure may also be a local silicon oxide isolation structure.
In this embodiment, the dielectric layer 460 is located on the isolation structure 401 and on a portion of the first fin 410 and a portion of the second fin 420.
In this embodiment, the dielectric layer 460 is a stacked structure, and includes a first dielectric layer 440 on the substrate 400, and a second dielectric layer 450 on the first dielectric layer 440.
The first dielectric layer 440 and the second dielectric layer 450 are made of an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the first dielectric layer 440 and the second dielectric layer 450 are made of silicon oxide.
In this embodiment, the material of the first gate oxide 411 and the second gate oxide 42 is silicon oxide. Wherein, the second gate oxide 421 is used as a part of the gate structure of the peripheral region ii transistor.
In the semiconductor manufacturing process, if a photoresist pattern is formed in the peripheral region ii, the peripheral region ii is prone to have photoresist residues, and the photoresist residues can be removed while the barrier layer is removed, so that the second barrier layer 426 is used for reducing the photoresist residues in the peripheral region ii; the second blocking layer 426 can also reduce the reaction of the second gate oxide 421 with the photoresist pattern, and reduce the photoresist residue, thereby improving the quality of the gate structure of the peripheral region ii, further improving the electrical performance of the transistor, and improving the yield of the device.
The material of the barrier layer is set as follows: a material which is easily formed on the first gate oxide layer 411 and the second gate oxide layer 421 and is easily removed. The blocking layer may be an oxide layer, and in this embodiment, the blocking layer is a silicon oxide layer. The silicon oxide layer is easy to form and remove, and the silicon oxide layer can be removed by conventional dry etching or wet etching, so that the method has better process compatibility with the existing process, and the process difficulty is reduced.
It should be noted that the thickness of the barrier layer is not too small nor too large. If the thickness of the blocking layer is too small, the blocking layer is difficult to better play a role in blocking the reaction between the second gate oxide 421 and the photoresist pattern, and in the process of removing the photoresist pattern, the photoresist residue is difficult to reduce, so that the electrical performance of the transistor is difficult to improve; if the thickness of the barrier layer is too large, it is easy to increase the removal of the barrier layerCost and process difficulties. Therefore, in this embodiment, the thickness of the barrier layer is
In the present embodiment, a transistor is provided, where the transistor includes a blocking layer (not labeled) located on the sidewall of the first opening 600, the sidewall of the first gate oxide 411, the sidewall of the second opening 610, the sidewall of the second gate oxide 421, and the top of the dielectric layer 460, and in the process of manufacturing a semiconductor, if a photoresist pattern is formed on the blocking layer, the photoresist residue on the blocking layer is removed together with the process of removing the blocking layer, so that the photoresist residue can be reduced or avoided, and the electrical performance of the transistor is further improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a transistor, comprising:
forming a substrate including a core region for forming a core device and a peripheral region for forming an input-output device;
forming a plurality of dummy gate structures on the substrate, wherein a first dummy gate structure is positioned on the substrate in the core region, and a second dummy gate structure is positioned on the substrate in the peripheral region, the first dummy gate structure comprises a first gate oxide layer and a first dummy gate electrode layer, and the second dummy gate structure comprises a second gate oxide layer and a second dummy gate electrode layer;
forming a dielectric layer on the substrate between the first pseudo gate structure and the second pseudo gate structure;
removing the first dummy gate electrode layer and the second dummy gate electrode layer, and forming a first opening exposing the first gate oxide layer and a second opening exposing the second gate oxide layer in the dielectric layer;
forming a barrier layer covering the side wall and the bottom of the first opening, the side wall and the bottom of the second opening and the dielectric layer, wherein the first barrier layer is positioned in the core area, and the second barrier layer is positioned in the peripheral area;
forming a photoresist pattern which fills the second opening and covers the peripheral area;
removing the first gate oxide layer and the first barrier layer by taking the photoresist pattern as a mask;
removing the photoresist pattern;
after removing the photoresist pattern, removing the second barrier layer to expose the second gate oxide layer at the bottom of the second opening;
forming a metal layer in the first opening and the second opening, wherein the metal layer in the first opening is used for forming a first grid structure; the second gate oxide layer and the metal layer in the second opening are used for forming a second gate structure.
2. The method of claim 1, wherein the barrier layer is an oxide layer.
3. The method of forming a transistor according to claim 1, wherein the barrier layer is a silicon oxide layer.
4. The method for forming a transistor according to claim 3, wherein the silicon oxide layer is formed by atomic layer deposition.
5. The method for forming a transistor according to claim 4, wherein the atomic layer deposition process parameters are: the growth temperature is 80-300 deg.C, the pressure in the chamber is 5mTorr-20Torr, and the growth time is 5-100 cycles.
6. The method of claim 1, wherein the barrier layer has a thickness of
7. The method of forming a transistor of claim 1, wherein said step of removing the first gate oxide layer and the first barrier layer comprises: and removing by adopting a SiCoNi etching process or a diluted hydrofluoric acid solution.
8. The method of claim 7, wherein the SiCoNi etch process comprises: the flow rate of helium gas is 600sccm to 2000sccm, the flow rate of nitrogen trifluoride gas is 20sccm to 200sccm, the flow rate of ammonia gas is 200sccm to 500sccm, the pressure of the chamber is 2Torr to 10Torr, and the process time is 20s to 400 s.
9. The method according to claim 7, wherein a volume concentration percentage of hydrofluoric acid in the hydrofluoric acid solution is 0.05% to 0.2%.
10. The method of forming a transistor according to claim 1, wherein the step of removing the photoresist pattern comprises: and removing the photoresist pattern by adopting an ashing process.
11. The method of forming a transistor according to claim 1, further comprising: before removing the second barrier layer, forming a sacrificial layer at the bottom of the first opening;
and in the step of removing the second barrier layer, the sacrificial layer at the bottom of the first opening is also removed.
12. The method for forming a transistor according to claim 11, wherein the sacrificial layer is a silicon oxide layer.
13. The method of forming a transistor according to claim 11, wherein the sacrificial layer has a thickness of
14. The method of forming a transistor according to claim 11, wherein the step of removing the sacrificial layer and the second barrier layer comprises: and (4) adopting a diluted hydrofluoric acid solution to perform a removing step.
15. The method of forming a transistor according to claim 1, wherein after forming said first opening and said second opening, a nitrogen doping process is performed on a first gate oxide layer exposed by said first opening and a second gate oxide layer exposed by said second opening.
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