CN112151382A - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN112151382A
CN112151382A CN201910579442.9A CN201910579442A CN112151382A CN 112151382 A CN112151382 A CN 112151382A CN 201910579442 A CN201910579442 A CN 201910579442A CN 112151382 A CN112151382 A CN 112151382A
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fin
initial
layer
substrate
forming
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韩秋华
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a device region and an isolation region; performing a first etching process on the substrate to form an initial substrate and a plurality of initial fin parts located on the initial substrate, wherein the initial fin parts comprise pseudo fin parts in the isolation region and channel fin parts located in the device region; removing the pseudo fin part and the initial substrate with partial thickness below the pseudo fin part, and forming a groove in the initial substrate; and carrying out a second etching process on the initial substrate, and removing the initial substrate with the partial thickness exposed by the channel fin part to form the fin part. Compared with the situation of directly forming the fin parts, the depth-to-width ratio of the area between the adjacent initial fin parts is smaller in the embodiment of the invention, so that less polymer impurities are accumulated in the process of forming the initial fin parts by etching, the included angle between the side walls of the initial fin parts and the normal of the initial substrate is smaller, the pseudo fin parts are not easy to remain, an epitaxial layer is not easy to form on an isolation area subsequently, and the electrical performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, and the difficulty of the gate voltage to pinch off the channel is increased, so that the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE), is more likely to occur.
Therefore, in order to reduce the impact of short channel effects, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which optimize the performance of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a device region and an isolation region for realizing isolation of the device region; performing a first etching process on the substrate to form an initial substrate and a plurality of initial fin parts located on the initial substrate, wherein the initial fin parts comprise a pseudo fin part in an isolation region and a channel fin part located in a device region; removing the pseudo fin portion and the initial substrate with partial thickness below the pseudo fin portion, and forming a groove in the initial substrate; performing a second etching process on the initial substrate, removing the initial substrate with the partial thickness exposed by the channel fin parts, and forming a substrate and a bottom fin part positioned on the substrate, wherein the bottom fin part and the channel fin part are used as fin parts, and the surface of the substrate between the fin parts is higher than the bottom surface of the groove; and forming an isolation layer in the groove and on the substrate exposed out of the fin part.
Optionally, after forming the initial fin portion, before removing the dummy fin portion, the method further includes: and forming a protective layer on the side wall of the initial fin part.
Optionally, the step of providing a substrate comprises: forming a mask layer on the substrate; the first etching process comprises the following steps: and etching the substrate by using the mask layer as a mask through a dry etching process to form the initial substrate and the initial fin part positioned on the initial substrate.
Optionally, in the first etching process, an included angle between the sidewall of the initial fin portion and the normal of the surface of the initial substrate is less than 2 degrees.
Optionally, the height of the initial fin portion is 40 nm to 100 nm.
Optionally, in the second etching process, the thickness of the initial substrate is etched to be 20 nm to 80 nm.
Optionally, in the step of forming the groove, a distance between a bottom surface of the groove and a top of the initial fin portion is 100 nm to 200 nm.
Optionally, the number of the dummy fin portions is one or more; removing the pseudo fin portion and the initial substrate with partial thickness below the pseudo fin portion through one or more patterning steps to form the groove; the step of patterning comprises: forming a shielding layer on the initial fin portion, wherein the shielding layer is provided with an opening for exposing one pseudo fin portion; etching the pseudo fin part exposed out of the opening and the initial substrate with partial thickness by taking the shielding layer as a mask to form a groove; after the groove is formed, removing the shielding layer; or the number of the dummy fin parts is one or more; removing the pseudo fin portion and the initial substrate with partial thickness below the pseudo fin portion through one patterning step to form the groove; the step of patterning comprises: forming a shielding layer exposing the one or more pseudo fin portions, wherein the shielding layer is provided with an opening exposing the pseudo fin portions; etching the pseudo fin part exposed out of the opening by taking the shielding layer as a mask to form the groove; and removing the shielding layer after removing the pseudo fin part.
Optionally, the blocking layer includes an organic dielectric layer, a hard mask layer on the organic dielectric layer, and a photoresist layer on the hard mask layer.
Optionally, an ashing process is used to remove the blocking layer.
Optionally, in the step of forming the protective layer, the thickness of the protective layer is 2 nm to 10 nm.
Optionally, the material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Optionally, the step of forming the protective layer includes: conformally covering the initial fin part and the initial substrate exposed by the initial fin part with the protective material layer; and removing the protective material layer on the initial fin part and the initial substrate, wherein the residual protective material layer on the side wall of the initial fin part is used as the protective layer.
Optionally, the protective material layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the device comprises an initial substrate, a first isolation layer and a second isolation layer, wherein the initial substrate comprises a device region and an isolation region for realizing isolation of the device region; a channel fin portion located on the initial substrate in the device region; and the groove is positioned in the initial substrate between the channel fin parts on one side, close to the isolation region, of the adjacent device regions.
Optionally, the semiconductor structure further includes: and the protective layer covers the side wall of the channel fin part.
Optionally, an included angle between the sidewall of the channel fin portion and the normal of the initial substrate surface is less than 2 degrees.
Optionally, the height of the channel fin is 40 nm to 100 nm.
Optionally, the thickness of the protective layer is 2 nm to 10 nm.
Optionally, the material of the protective layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the initial fin part is formed firstly, the height of the initial fin part is lower than that of the fin part formed subsequently, compared with the situation that the fin part is formed directly, because the depth-to-width ratio of the area between the adjacent initial fin parts is smaller, the accumulated polymer impurities are less in the process of forming the initial fin part by etching, the influence of the polymer impurities on the etching track is smaller, and the included angle between the side wall of the initial fin part and the normal line of an initial substrate is smaller, therefore, the pseudo fin part is not easy to have residues in the process of removing the pseudo fin part; in the second etching process, the residual pseudo fin part is further removed, so that an epitaxial layer is not easily formed on the isolation region in the process of forming the source and drain doping layer by adopting an epitaxial growth process subsequently, the probability of electric leakage caused by connection of the epitaxial layer and a subsequently formed gate structure or the source and drain doping layer is reduced, and the electrical property of the semiconductor structure is improved.
Drawings
Fig. 1 to 3 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure;
fig. 4 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As can be seen from the background art, the performance of the devices formed at present is still not good. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 3, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
As shown in fig. 1, a base is provided, and the base includes a substrate 1, a fin portion 2 on the substrate 1, and the fin portion 2 includes a device fin portion 22 for forming a device and a dummy fin portion 21 to be removed.
As shown in fig. 2, an opening 3 exposing the dummy fin 21 is formed.
As shown in fig. 3, the opening 3 is used as a mask to etch and remove the dummy fin portion 21 (as shown in fig. 2); and after removing the dummy fin portion 21, forming an isolation layer 5 on the substrate 1 exposed by the device fin portion 22.
The opening 3 is used as a mask, the pseudo fin portion 21 is removed through a dry etching process, the pseudo fin portion 4 is prone to remaining in the pseudo fin portion 21, the isolation layer 5 is prone to exposing the remaining pseudo fin portion 4, an epitaxial layer is prone to epitaxially growing on the remaining pseudo fin portion 4 in the process of forming a source drain doping layer through subsequent epitaxial growth, and the epitaxial layer is in contact with a subsequently formed gate structure or the source drain doping layer, so that the performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a substrate, where the substrate includes a device region and an isolation region for isolating the device region; performing a first etching process on the substrate to form an initial substrate and a plurality of initial fin parts located on the initial substrate, wherein the initial fin parts comprise a pseudo fin part in an isolation region and a channel fin part located in a device region; removing the pseudo fin portion and the initial substrate with partial thickness below the pseudo fin portion, and forming a groove in the initial substrate; performing a second etching process on the initial substrate, removing the initial substrate with the partial thickness exposed by the channel fin parts, and forming a substrate and a bottom fin part positioned on the substrate, wherein the bottom fin part and the channel fin part are used as fin parts, and the surface of the substrate between the fin parts is higher than the bottom surface of the groove; and forming an isolation layer in the groove and on the substrate exposed out of the fin part.
In the embodiment of the invention, the initial fin part is formed firstly, the height of the initial fin part is lower than that of the fin part formed subsequently, compared with the situation that the fin part is formed directly, because the depth-to-width ratio of the area between the adjacent initial fin parts is smaller, the accumulated polymer impurities are less in the process of forming the initial fin part by etching, the influence of the polymer impurities on the etching track is smaller, the included angle between the side wall of the initial fin part and the normal line of an initial substrate is smaller, and the pseudo fin part is not easy to have residues in the process of removing the pseudo fin part; in the second etching process, the residual pseudo fin part is further removed, so that an epitaxial layer is not easily formed on the isolation region in the process of forming the source and drain doping layer by adopting an epitaxial growth process subsequently, the probability of electric leakage caused by connection of the epitaxial layer and a subsequently formed gate structure or the source and drain doping layer is reduced, and the electrical property of the semiconductor structure is improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 4 to 12 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 4, a substrate 100 is provided, the substrate 100 including a device region I and an isolation region II for isolating the device region I.
The substrate 100 is used to provide a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the substrate 100 may also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride, or the like.
The forming method further includes: a mask layer 101 is formed on the substrate 100.
The mask layer 101 serves as an etching mask for forming an initial fin portion subsequently.
Specifically, the material of the mask layer 101 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the mask layer 101 is made of silicon nitride.
As shown in fig. 5, a first etching process is performed on the substrate 100 to form an initial substrate 102 and a plurality of initial fins 103 located on the initial substrate 102, where the initial fins 103 include dummy fins 1032 in the isolation region II and trench fins 1031 located in the device region I.
Subsequently removing the dummy fin 1032 and a part of the thickness of the initial substrate 102 to form a groove; after the grooves are formed, a second etching process is adopted to etch the initial substrate 102 by taking the mask layer 101 as a mask, so that a substrate and a bottom fin portion located on the substrate are formed, and the bottom fin portion and the channel fin portion 1031 are used as fin portions. The height of the initial fin portion 103 is lower than that of the fin portion formed subsequently, and compared with the situation that the fin portion is formed directly, the depth-to-width ratio of the region between the adjacent initial fin portions 103 is smaller, so that polymer impurities accumulated in the process of forming the initial fin portion 103 by etching are less, the influence of the polymer impurities on an etching track is smaller, the included angle between the side wall of the initial fin portion 103 and the surface normal of the initial substrate 102 is smaller, and the pseudo fin portion 1032 is not easy to remain in the process of removing the pseudo fin portion 1032; in addition, in the second etching process, the residual pseudo fin portion 1032 is further removed, so that in the process of forming the source and drain doped layers by adopting an epitaxial growth process, an epitaxial layer is not easily formed on the isolation region II, the probability of electric leakage caused by connection of the epitaxial layer and a subsequently formed gate structure or the source and drain doped layers is reduced, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the first etching process includes: and etching the substrate 100 by using the mask layer 101 as a mask through a dry etching process to form the initial substrate 102 and the initial fin part 103 on the initial substrate 102. The dry etching process is an anisotropic etching process and has good etching profile controllability, so that an included angle between the side wall of the initial fin portion 103 and the surface normal of the initial substrate 102 is small.
It should be noted that, in the first etching process, an included angle between the sidewall of the initial fin portion 103 and the normal line of the surface of the initial substrate 102 is not too large. In the subsequent process, a shielding layer exposing the dummy fin portion 1032 is formed, and the dummy fin portion 1032 is removed by etching with the shielding layer as a mask. If the included angle is too large, that is, in a direction perpendicular to the extending direction of the initial fin portion 103, the bottom of the dummy fin portion 1032 is large in size, after the dummy fin portion 1032 is removed by etching using a shielding layer as a mask, the dummy fin portion 1032 is prone to remain, and in the process of forming a source and drain doping layer through subsequent epitaxial growth, an epitaxial layer connected with the source and drain doping layer or a gate structure is prone to grow in the isolation region II, so that the electrical performance of the semiconductor structure is poor. In this embodiment, an angle between the sidewall of the initial fin 103 and the normal of the surface of the initial substrate 102 is less than 2 degrees.
Specifically, the process parameters of the first etching process include: the etching gas includes: CF (compact flash)4、HBr、NF3And Cl2，CF4The gas flow rate of the catalyst is 10sccm to 500sccm, the gas flow rate of HBr is 10sccm to 500sccm, NF3The gas flow rate of (1) is 10sccm to 100sccm, Cl2The gas flow rate of (2) is 50sccm to 500 sccm.
It should be noted that the flow rate of the etching gas should not be too large or too small. If the flow of the etching gas is too large, a large etching rate is likely to be generated, and in the process of forming the initial fin portion 103 by etching, the etching rate in the first etching process is likely to be difficult to control, so that the height of the initial fin portion 103 is too high, the formation quality of the initial fin portion 103 is also likely to be poor, and correspondingly, when the semiconductor structure works, the migration rate of carriers in the channel fin portion 1031 is relatively slow. If the flow rate of the etching gas is too low, the removal rate of the base 100 material exposed out of the mask layer 101 is too low, so that the time for forming the initial substrate 102 and the initial fin portion 103 on the initial substrate 102 is too long, and the time for forming the initial fin portion 103 on the initial substrate 102 is not too longThe forming efficiency of the semiconductor structure is improved. In this example, CF4The flow rate of (2) is 10sccm to 200 sccm; HBr gas flow rate is 10sccm to 500 sccm; NF3The flow rate of (2) is 5sccm to 200 sccm; cl2The gas flow rate of (2) is 50sccm to 500 sccm.
It should be noted that the height of the initial fin 103 should not be too high or too low. If the height of the initial fin portion 103 is too high, the aspect ratio of the region between adjacent initial fin portions 103 is large, and more polymer impurities are accumulated in the opening, so that the influence of the polymer impurities on the etching track is large, the included angle between the corresponding initial fin portion 103 side wall and the initial substrate 102 is large, and the dummy fin portion 1032 is prone to remain after the first etching process. In the subsequent process, the trench fin 1031 serves as a channel region, and if the height of the initial fin 103 is too low, the height of the corresponding trench fin 1031 is too low, that is, the height of the channel region is too low, which may result in a smaller driving current of the semiconductor structure. In this embodiment, the height of the initial fin 103 is 40 nm to 100 nm.
In this embodiment, the method for forming the semiconductor structure further includes: after the forming the initial fin portion 103, before removing the dummy fin portion 1032, the method further includes: a protection layer 104 is formed on the sidewalls of the initial fin 103.
The protection layer 104 is formed on the sidewall of the trench fin 1031, a shielding layer exposing the dummy fin 1032 is formed subsequently, and the protection layer 104 prevents the trench fin 1031 from being damaged in the subsequent process of removing the dummy fin 1032 by using the shielding layer as a mask. The channel fin 1031 serves as a channel region, so that when the semiconductor structure operates, the transfer rate of carriers in the channel fin 1031 is high.
In this embodiment, the material of the protection layer 104 is different from the material of the dummy fin 1032 and the material of the shielding layer, so that a higher etching selectivity ratio exists between the dummy fin 1032 and the protection layer 104 and between the dummy fin 1032 and the shielding layer in the subsequent process of etching the dummy fin 1032.
In this embodiment, the material of the protection layer 104 is a dielectric material.
Specifically, the material of the protection layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the protection layer 104 includes silicon oxide. The silicon oxide is a commonly used material in the semiconductor process, and the cost of the silicon oxide material is lower, so that the process cost and the process complexity for forming the semiconductor structure are reduced.
In this embodiment, the step of forming the protection layer 104 includes: conformally covering the initial fin 103 and the initial substrate 102 exposed by the initial fin 103 with the protective material layer (not shown); the protective material layer on the initial fin 103 and on the initial substrate 102 is removed, and the remaining protective material layer on the sidewall of the initial fin 103 serves as a protective layer 104.
In this embodiment, the protective material Layer is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process has good deposition uniformity, is favorable for improving the thickness uniformity and the film quality of the protective material layer, is correspondingly favorable for improving the film forming quality of the protective material layer, and is also favorable for accurately controlling the deposition thickness of the protective material layer by adopting the atomic layer deposition process, so that the protective layer 104 can better protect the channel fin part 1031. In other embodiments, the protective material layer may be formed by a Chemical Vapor Deposition (CVD) process.
It should be noted that the protective layer 104 is not too thick nor too thin. If the passivation layer 104 is too thick, too much process time is required to form the passivation layer 104, and accordingly, too much time is required to remove the passivation layer 104, which is not favorable for improving the formation efficiency of the semiconductor structure. If the protection layer 104 is too thin, the protection layer 104 on the channel fin 1031 is easily removed too early in the subsequent process of removing the dummy fin 1032, so that the protection layer 104 cannot protect the channel fin 1031. In this embodiment, the thickness of the protection layer 104 is 2 nm to 10 nm.
Referring to fig. 6 to 10, the dummy fins 1032 and the initial substrate 102 below the dummy fins 1032 are removed, and a recess 110 is formed in the initial substrate 102 (as shown in fig. 10).
The recess 110 is located in the isolation region II, and the recess 110 is prepared for forming an isolation layer later.
In this embodiment, the distance from the bottom surface of the recess 110 to the top of the channel fin 1031 should not be too large or too small. If the distance is too large, too much process time is spent for forming the groove 110, and an isolation layer is formed in the groove 110 subsequently, the isolation layer is made of silicon oxide subjected to annealing treatment, the isolation layer becomes denser in the annealing process, so that large stress exists in the isolation layer, and the stress in the isolation layer easily causes the subsequently formed fin portion to bend or incline. If the distance is too small, the thickness of the isolation layer formed in the groove 110 subsequently is likely to be small, and accordingly, the isolation layer cannot well isolate the adjacent device region I. In the embodiment, the distance from the bottom surface of the recess 110 to the top of the channel fin 1031 is 100 nm to 200 nm.
In this embodiment, the number of the dummy fins 1032 is one or more; the grooves 110 are formed by removing the dummy fin 1032 and the initial substrate 102 below the dummy fin 1032 by a thickness through one or more patterning steps.
In this embodiment, only one dummy fin portion 1032 is removed in one patterning step, and compared with a case where a plurality of dummy fin portions 1032 are removed in one patterning step, in an etching process, more etching gas is only in contact with the dummy fin portion 1032 exposed by the opening 106, so that the etched rate of the dummy fin portion 1032 is faster, the corresponding dummy fin portion 1032 is better in removal effect, and the residual dummy fin portion 1032 is not easy to exist.
Specifically, the patterning step includes:
as shown in fig. 6, a shielding layer 105 is formed on the initial fin 103, and the shielding layer 105 has an opening 106 exposing one of the dummy fins 1032.
In this embodiment, the shielding layer 105 is a triple-layer mask (tri-layer mask) technology, that is, the shielding layer 105 includes an organic dielectric layer 1051, a hard mask layer 1052 on the organic dielectric layer 1051, and a photoresist layer 1053 on the hard mask layer 1052. Compared with a single-layer photoresist mask, the three-layer mask layer is not easy to fall off, so that rework is not needed, and the pattern transfer precision is improved. The process of forming the shielding layer 105 is a process commonly used in the semiconductor field, and the description of the embodiment is omitted here.
After a groove is formed by subsequent etching, the photoresist layer 1053 and the hard mask layer 1052 are consumed and removed, and the remaining shielding layer 105 is the organic dielectric layer 1051. The organic dielectric layer 1051 is a material that is easy to remove, so that the damage to the protection layer 104 in the subsequent process of removing the shielding layer 105 is small. Accordingly, the material of the organic dielectric layer 1051 is an organic material including: one or more of a BARC (bottom-antireflective coating) material, an ODL (organic dielectric layer) material, a photoresist, a DARC (dielectric-antireflective coating) material, a spin-on carbon (SOC) material, a DUO (Deep UV Light Absorbing Oxide) material, and an APF (Advanced Patterning Film) material. In this embodiment, the organic dielectric layer 1051 is made of Spin On Carbon (SOC) layer material.
Note that the fact that the shielding layer 105 has the opening 106 exposing one of the dummy fins 1032 means that the photoresist layer 1053 in the shielding layer 105 exposes the dummy fin 1032.
As shown in fig. 7, the dummy fin 1032 exposed by the opening 106 and the initial substrate 102 with a partial thickness are etched by using the shielding layer 105 as a mask, so as to form a groove 110.
In the process of etching the dummy fin portion 1032 exposed from the opening 106 by using the shielding layer 105 as a mask, the shielding layer 105 protects the initial fin portion 103 covered by the shielding layer 105.
In this embodiment, the dummy fin 1032 and the initial substrate 102 with a partial thickness are etched by using the shielding layer 105 as a mask and using a dry etching process, so as to form the groove 110. The dry etching process is an anisotropic etching process, and has good etching profile controllability, so that the protective layer 104 covered by the shielding layer 105 is not easily damaged in the etching process, the channel fin portion 1031 covered by the protective layer 104 is not easily etched by mistake, and the formation quality of subsequent fin portions is improved.
The technological parameters of the dry etching process comprise: the etching gas includes: CF (compact flash)4、NF3And Cl2，CF4The gas flow rate of (1) is 10sccm to 500sccm, NF3The gas flow rate of (1) is 10sccm to 100sccm, Cl2The gas flow rate of (2) is 50sccm to 500 sccm.
It should be noted that the flow rate of the etching gas should not be too large or too small. If the flow of the etching gas is too large, a large etching rate is easily generated, the process stability is poor, and the protective layer 104 on the sidewall of the channel fin portion 1031 is easily etched by mistake, so that the channel fin portion 1031 is easily etched by mistake, and further, the migration rate of carriers in a channel is slow when a subsequent semiconductor structure works. If the flow rate of the etching gas is too small, the removal rate of the dummy fin 1032 and the initial substrate 102 in the thickness of the portion below the dummy fin 1032 is too slow, which is not favorable for improving the formation efficiency of the semiconductor structure. In this example, CF4The gas flow rate of (1) is 10sccm to 500sccm, NF3The gas flow rate of (1) is 10sccm to 100sccm, Cl2The gas flow rate of (2) is 50sccm to 500 sccm.
It should be noted that, in the process of etching the dummy fin 1032 exposed by the opening 106 and the initial substrate 102 with a partial thickness to form the groove 110, the shielding layer 105 is etched, so that the size of the opening 106 is easily increased, but because the shielding layer 105 and the protection layer 104 have an etching selection ratio, the protection layer 104 is less damaged, and thus the trench fin 1031 covered by the protection layer 104 is not easily damaged.
It should be noted that, in the patterning step, the protection layer 104 on the sidewall of the dummy fin 1032 is also etched. Removing the protection layer 104 provides for subsequent formation of a recess in the isolation region II.
As shown in fig. 8, after the groove 110 is formed, the shielding layer 105 is removed (as shown in fig. 7).
In this embodiment, the masking layer 105 is removed by an ashing process.
As shown in fig. 9, after removing one of the dummy fins 1032, forming a shielding layer 105 on the initial fin 103 again, where the shielding layer 105 has an opening 106 exposing one of the dummy fins 1032, and removing the dummy fins 1032 exposed by the opening 106 by using the opening 106 as a mask to form a recess 110.
As shown in fig. 10, after a plurality of patterning steps, the dummy fins 1032 are removed, and a plurality of grooves 110 are formed. The recess 110 provides for the subsequent formation of an isolation layer.
In other embodiments, the number of the dummy fin portions is one or more; and removing the pseudo fin part and the initial substrate with partial thickness below the pseudo fin part through one patterning step to form the groove.
The step of patterning comprises: forming a shielding layer exposing the one or more pseudo fin portions, wherein the shielding layer is provided with an opening exposing the pseudo fin portions; etching the pseudo fin part exposed out of the opening by taking the shielding layer as a mask to form the groove; and removing the shielding layer after removing the pseudo fin part.
Referring to fig. 11, a second etching process is performed on the initial substrate 102 (as shown in fig. 10), the initial substrate 102 with a partial thickness exposed by the trench fin 1031 is removed, a substrate 107 and a bottom fin 108 located on the substrate 107 are formed, the bottom fin 108 and the trench fin 1031 are used as fins 109, and the surface of the substrate 107 between the fins 109 is higher than the bottom surface of the groove 110.
The fin 109 provides for subsequent formation of semiconductor devices.
In this embodiment, the second etching process includes: and removing the initial substrate 102 with the exposed partial thickness of the channel fin portion 1031 by using the mask layer 101 (as shown in fig. 10) as a mask and adopting a dry etching process to form a substrate 107 and a bottom fin portion 108 located on the substrate 107, wherein the bottom fin portion 108 and the channel fin portion 1031 are used as fin portions 109. The dry etching process is an anisotropic etching process and has better etching profile controllability. In the etching process, the protection layer 104 is not easily damaged, so that the channel fin 1031 covered by the protection layer 104 is not easily etched by mistake.
It should be noted that, in the second etching process, the thickness of the initial substrate 102 is not too large or too small. If the etching thickness is too large, the height of the bottom fin portion 108 is easily too high, an isolation layer is subsequently formed in the groove 110, the isolation layer is made of silicon oxide subjected to annealing treatment, the isolation layer becomes more compact in the annealing process, large stress exists in the isolation layer, and the stress in the isolation layer easily causes the fin portion 109 to bend or incline. If the etching thickness in the second etching process is too small, the thickness of the subsequently formed isolation layer is too small, and the isolation layer cannot well electrically isolate the gate structure from the substrate 107. In this embodiment, in the second etching process, the thickness of the initial substrate 102 is 20 nm to 80 nm.
It should be noted that, in the second etching process, the dummy fin portion 1032 remaining in the isolation region II and the remaining protection layer 104 are further etched, so that the subsequent formation of the isolation layer can cover the remaining dummy fin portion 1032 and the remaining protection layer 104, and in the process of forming the source and drain doping layer, an epitaxial layer connected to the source and drain doping layer and the gate structure is not easily grown on the isolation region II, thereby reducing the probability of leakage current of the semiconductor structure.
It should be noted that, in the second etching process, the groove 110 is further etched, so that the groove 110 is deeper, and the isolation layer formed in the groove 110 subsequently has a better isolation effect on the device region I.
In this embodiment, after the second etching process is performed, the protection layer 104 on the sidewall of the trench fin 1031 is removed. The protective layer 104 on the sidewalls of the channel fin 1031 is removed in preparation for the subsequent formation of a gate structure crossing the channel fin 1031.
In this embodiment, the protective layer 104 is removed by a wet etching process.
Specifically, the wet etching solution is an HF solution.
It should be noted that, after the second etching process is performed, the method further includes: the mask layer 101 on the tunnel fin 1031 is removed (as shown in fig. 10). The mask layer 101 is removed in preparation for the subsequent formation of a gate structure that spans the fin 109.
Referring to fig. 12, an isolation layer 111 is formed in the recess 110 and on the substrate 107 where the fin 109 is exposed.
The isolation layer 111 located between adjacent fins 109 is used to electrically isolate the adjacent fins 109, and the isolation layer 111 located in the recess 110 (as shown in fig. 11) is used to isolate the adjacent device region I.
The isolation layer 111 is made of a dielectric material.
Specifically, the material of the isolation layer 111 includes one or more of silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 111 includes silicon oxide. The silicon oxide is a dielectric material with a common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 111.
It should be noted that, in this embodiment, the isolation layer 111 covers a portion of the sidewall of the trench fin 1031. In other embodiments, the top surface of the isolation layer may be flush with or lower than the bottom surface of the channel fin.
It should be noted that the forming process of the isolation layer 111 includes an annealing process, the isolation layer 111 becomes denser after the annealing process, and the isolation layer 111 has a larger stress.
With continued reference to fig. 12, the method of forming the semiconductor structure further includes: after the isolation layer 111 is formed, a gate structure 112 crossing the fin portion 109 and a source-drain doping layer (not shown in the figure) located in the fin portion 109 on two sides of the gate structure 112 are formed, wherein the gate structure 112 covers part of the top surface and part of the side wall of the fin portion 109.
The gate structure 112 is used to control the channel in the fin 109 to be turned on and off during semiconductor operation.
In this embodiment, the gate structure 112 is a metal gate structure. In other embodiments, the gate structure may also be a polysilicon gate structure.
In this embodiment, the isolation layer 111 covers a portion of the sidewall of the channel fin 1031, and correspondingly, the bottom surface of the gate structure 102 is higher than the bottom surface of the channel fin 1031.
In other embodiments, the bottom surface of the gate structure may be lower than or flush with the bottom surface of the channel fin.
When the semiconductor structure works, the source-drain doped layer is used for providing stress for a channel and improving the migration rate of carriers.
In this embodiment, the source-drain doping layer is formed by an epitaxial growth process. Because the residual dummy fin 1032 and the residual protection layer 104 are covered by the isolation layer 111, an epitaxial layer is not easily formed on the residual dummy fin 1032 in the process of forming the source and drain doping layers, so that the situation of electric leakage caused by the contact between the epitaxial layer and the source and drain doping layers or the gate structure 112 is avoided.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 10, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: an initial substrate 102, including a device region I and an isolation region II for realizing isolation of the device region I; a channel fin 1031 located on the initial substrate 102 in the device region I; a recess 110 in the initial substrate 102 between the channel fins 1031 on a side of the adjacent device region I near the isolation region II.
In the forming process of the semiconductor structure, a first etching process is used to etch a substrate, so as to form the initial substrate 102 and an initial fin portion 103 (shown in fig. 5) located on the initial substrate 102, where the initial fin portion 103 located in the device region I is used as a channel fin portion 1031, and the initial fin portion 103 located in the isolation region II is used as a dummy fin portion 1032 (shown in fig. 5); removing the dummy fin portion 1032 in the isolation region II; removing the dummy fins 1032 and a part of the thickness of the initial substrate 102 to form a groove 110; and subsequently, etching the initial substrate 102 by using a second etching process to form a substrate and a bottom fin portion located on the substrate, wherein the bottom fin portion and the channel fin portion 1031 are used as fin portions. The height of the initial fin portion 103 is lower than that of the fin portion formed subsequently, and compared with the situation that the fin portion is formed directly, the depth-to-width ratio of the region between the adjacent initial fin portions 103 is smaller, so that polymer impurities accumulated in the process of forming the initial fin portion 103 by etching are less, the influence of the polymer impurities on an etching track is smaller, the included angle between the side wall of the initial fin portion 103 and the surface normal of the initial substrate 102 is smaller, and the pseudo fin portion 1032 is not easy to remain in the process of removing the pseudo fin portion 1032; in addition, the second etching process is subsequently utilized to further remove the residual pseudo fin portion 1032 and the isolation layer formed in the groove 110 and on the substrate exposed by the fin portion, the isolation layer is easy to cover the pseudo fin portion 1032, so that in the process of forming the source and drain doping layer by the epitaxial growth process subsequently, an epitaxial layer is not easy to form on the isolation region II, the probability of electric leakage caused by connection of the epitaxial layer and a subsequently formed gate structure or the source and drain doping layer is reduced, and the electrical performance of the semiconductor structure is improved.
The initial substrate 102 is used to provide a process platform for subsequently forming semiconductor structures.
In this embodiment, the initial substrate 102 is made of silicon. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate. The surface of the initial substrate 102 can also form an interface layer, and the material of the interface layer is silicon oxide, silicon nitride, silicon oxynitride or the like.
In this embodiment, the material of the channel fin 1031 is the same as the material of the initial substrate 102. In other embodiments, the material of the channel fin may also be different from the material of the initial substrate.
The mask layer 101 serves as an etching mask for etching the initial substrate 102 in a subsequent second etching process.
Specifically, the material of the mask layer 101 includes one or more of silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the mask layer 101 is made of silicon nitride.
The channel fin 1031 serves as a channel region when the semiconductor structure is in operation.
It should be noted that an included angle between the sidewall of the trench fin 1031 and the normal line of the initial substrate 102 is not too large, that is, an included angle between the sidewall of the initial fin 103 and the normal line of the initial substrate 102 is not too large. If the included angle is too large, that is, in the direction perpendicular to the extending direction of the channel fin portion 1031, the bottom of the dummy fin portion 1032 is large in size, after the dummy fin portion 1032 and the initial substrate 102 below the dummy fin portion 1032 are correspondingly etched, residual dummy fin portions 1032 are prone to exist, and in the process of forming a source and drain doping layer through subsequent epitaxial growth, an epitaxial layer connected with the source and drain doping layer or a gate structure is prone to grow in the isolation region II, so that the electrical performance of the semiconductor structure is poor. In this embodiment, an included angle between the sidewall of the trench fin 1031 and the normal of the surface of the initial substrate 102 is less than 2 degrees.
It should be noted that the height of the trench fin 1031 is not too high nor too low. If the height of the trench fin 1031 is too high, that is, the height of the initial fin 103 is too high, the aspect ratio of the region between adjacent initial fins 103 is large, and the polymer impurities accumulated in the opening are more, so that the influence of the polymer impurities on the etching track is large, the included angle between the sidewall of the corresponding initial fin 103 and the initial substrate 102 is large, and the dummy fin 1032 is likely to remain after the first etching process. In the subsequent process, the trench fin 1031 serves as a channel region, and if the height of the trench fin 1031 is too low, the height of the corresponding trench fin 1031 is too low, that is, the height of the channel region is too low, which may result in a smaller driving current of the semiconductor structure. In this embodiment, the height of the channel fin 1031 is 40 nm to 100 nm.
The semiconductor structure further includes: and a protection layer 104 covering the sidewalls of the trench fin 1031.
Specifically, the protection layer 104 conformally covers the sidewalls of the trench fin 1031.
The protective layer 104 is formed on the sidewall of the trench fin 1031, and the protective layer 104 makes the trench fin 1031 less susceptible to damage in a subsequent process of etching the initial substrate 102 exposed by the trench fin 1031 by using the mask layer 101 as a mask. The channel fin 1031 serves as a channel region, so that when the semiconductor structure operates, the transfer rate of carriers in the channel fin 1031 is high.
In this embodiment, the material of the protection layer 104 is a dielectric material.
Specifically, the material of the protection layer 104 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the protection layer 104 includes silicon oxide. The silicon oxide is a commonly used material in the semiconductor process, and the cost of the silicon oxide material is lower, so that the process cost and the process complexity for forming the semiconductor structure are reduced.
It should be noted that the protective layer 104 is not too thick nor too thin. The formation of the protective layer 104 generally includes: conformally covering the channel fin 1031 and the exposed protective material layer of the initial substrate 102 on the channel fin 1031, removing the protective material layer on the top of the channel fin 1031 and the initial substrate 102, and using the residual protective material layer on the sidewall of the channel fin 1031 as a protective layer 104. If the protection layer 104 is too thick, too much processing time may be spent for forming the protection material layer, and accordingly, too much processing time may be spent for removing the protection material layer on the top of the channel fin 1031 and the initial substrate 102 to form the protection layer 104, which is not favorable for improving the formation efficiency of the semiconductor structure. If the protection layer 104 is too thin, the protection layer 104 on the channel fin 1031 is easily removed too early in the subsequent second etching process, so that the protection layer 104 cannot protect the channel fin 1031. In this embodiment, the thickness of the protection layer 104 is 2 nm to 10 nm.
The recess 110 is located in the isolation region II, and the recess 110 is prepared for forming an isolation layer later.
It should be noted that the distance from the bottom surface of the recess 110 to the top of the channel fin 1031 is neither too large nor too small. If the distance is too large, too much process time is spent for forming the groove 110, and an isolation layer is formed in the groove 110 subsequently, the isolation layer is made of silicon oxide subjected to annealing treatment, the isolation layer becomes denser in the annealing process, so that large stress exists in the isolation layer, and the stress in the isolation layer easily causes the subsequently formed fin portion to bend or incline. If the distance is too small, the thickness of the isolation layer formed in the groove 110 subsequently is likely to be small, and accordingly, the isolation layer cannot well isolate the adjacent device region I. In this embodiment, the distance from the bottom surface of the recess 110 to the top of the channel fin 1031 is 100 nm to 200 nm.
The semiconductor structure may be formed by the formation method of the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure of this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be effected therein by one of ordinary skill in the pertinent art without departing from the scope or spirit of the present embodiments, and it is intended that the scope of the present embodiments be defined by the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a device region and an isolation region for realizing isolation of the device region;
performing a first etching process on the substrate to form an initial substrate and a plurality of initial fin parts located on the initial substrate, wherein the initial fin parts comprise a pseudo fin part in an isolation region and a channel fin part located in a device region;
removing the pseudo fin portion and the initial substrate with partial thickness below the pseudo fin portion, and forming a groove in the initial substrate;
performing a second etching process on the initial substrate, removing the initial substrate with the partial thickness exposed by the channel fin parts, and forming a substrate and a bottom fin part positioned on the substrate, wherein the bottom fin part and the channel fin part are used as fin parts, and the surface of the substrate between the fin parts is higher than the bottom surface of the groove;
and forming an isolation layer in the groove and on the substrate exposed out of the fin part.
2. The method of forming a semiconductor structure of claim 1, wherein after forming the initial fin portion and before removing the dummy fin portion further comprises: and forming a protective layer on the side wall of the initial fin part.
3. The method of forming a semiconductor structure of claim 1 or 2, wherein the step of providing a substrate comprises: forming a mask layer on the substrate;
the first etching process comprises the following steps: and etching the substrate by using the mask layer as a mask through a dry etching process to form the initial substrate and the initial fin part positioned on the initial substrate.
4. The method of claim 1 or 2, wherein an angle between the sidewalls of the initial fin portion and a normal to the surface of the initial substrate is less than 2 degrees in the first etching process.
5. The method of claim 1 or 2, wherein the initial fin has a height of 40 nm to 100 nm.
6. The method for forming a semiconductor structure according to claim 1 or 2, wherein in the second etching process, the initial substrate is etched to a thickness of 20 nm to 80 nm.
7. The method of claim 1 or 2, wherein in the step of forming the recess, a distance between a bottom surface of the recess and a top of the initial fin is in a range from 100 nm to 200 nm.
8. The method for forming a semiconductor structure according to claim 1 or 2, wherein the number of the dummy fin portions is one or more; removing the pseudo fin portion and the initial substrate with partial thickness below the pseudo fin portion through one or more patterning steps to form the groove;
the step of patterning comprises: forming a shielding layer on the initial fin portion, wherein the shielding layer is provided with an opening for exposing one pseudo fin portion; etching the pseudo fin part exposed out of the opening and the initial substrate with partial thickness by taking the shielding layer as a mask to form a groove; after the groove is formed, removing the shielding layer;
or the number of the dummy fin parts is one or more;
removing the pseudo fin portion and the initial substrate with partial thickness below the pseudo fin portion through one patterning step to form the groove;
the step of patterning comprises: forming a shielding layer exposing the one or more pseudo fin portions, wherein the shielding layer is provided with an opening exposing the pseudo fin portions; etching the pseudo fin part exposed out of the opening by taking the shielding layer as a mask to form the groove; and removing the shielding layer after removing the pseudo fin part.
9. The method of claim 8, wherein the masking layer comprises an organic dielectric layer, a hard mask layer on the organic dielectric layer, and a photoresist layer on the hard mask layer.
10. The method of forming a semiconductor structure according to claim 8, wherein the blocking layer is removed by an ashing process.
11. The method of forming a semiconductor structure of claim 2, wherein in the step of forming the protective layer, the protective layer has a thickness of 2 nm to 10 nm.
12. The method of forming a semiconductor structure of claim 2, wherein a material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
13. The method of forming a semiconductor structure of claim 2, wherein forming the protective layer comprises: conformally covering the initial fin part and the initial substrate exposed by the initial fin part with the protective material layer; and removing the protective material layer on the initial fin part and the initial substrate, wherein the residual protective material layer on the side wall of the initial fin part is used as the protective layer.
14. The method of claim 13, wherein the layer of protective material is formed using an atomic layer deposition process or a chemical vapor deposition process.
15. A semiconductor structure, comprising:
the device comprises an initial substrate, a first isolation layer and a second isolation layer, wherein the initial substrate comprises a device region and an isolation region for realizing isolation of the device region;
a channel fin portion located on the initial substrate in the device region;
and the groove is positioned in the initial substrate between the channel fin parts on one side, close to the isolation region, of the adjacent device regions.
16. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: and the protective layer covers the side wall of the channel fin part.
17. The semiconductor structure of claim 15 or 16, wherein the trench fin sidewalls are angled less than 2 degrees from the initial substrate surface normal.
18. The semiconductor structure of claim 15 or 16, wherein the channel fin has a height of 40 nm to 100 nm.
19. The semiconductor structure of claim 16, wherein the protective layer has a thickness of 2 nm to 10 nm.
20. The semiconductor structure of claim 16, wherein a material of the protective layer comprises one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, and boron carbonitride.
CN201910579442.9A 2019-06-28 2019-06-28 Semiconductor structure and forming method thereof Pending CN112151382A (en)

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