CN108155148B - Method for forming semiconductor structure - Google Patents

Method for forming semiconductor structure Download PDF

Info

Publication number
CN108155148B
CN108155148B CN201611100045.1A CN201611100045A CN108155148B CN 108155148 B CN108155148 B CN 108155148B CN 201611100045 A CN201611100045 A CN 201611100045A CN 108155148 B CN108155148 B CN 108155148B
Authority
CN
China
Prior art keywords
layer
isolation
forming
isolation layer
isolation structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201611100045.1A
Other languages
Chinese (zh)
Other versions
CN108155148A (en
Inventor
肖芳元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Original Assignee
Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Manufacturing International Shanghai Corp, Semiconductor Manufacturing International Beijing Corp filed Critical Semiconductor Manufacturing International Shanghai Corp
Priority to CN201611100045.1A priority Critical patent/CN108155148B/en
Publication of CN108155148A publication Critical patent/CN108155148A/en
Application granted granted Critical
Publication of CN108155148B publication Critical patent/CN108155148B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

A method of forming a semiconductor structure, comprising: forming a substrate and a fin part; forming a first isolation layer and a second isolation layer; forming an initial isolation structure so as to form a preset height difference between the top surface of the first isolation layer and the initial isolation structure; and etching back the first isolation layer and the initial isolation structure to form a first isolation structure and a second isolation structure respectively. According to the technical scheme, after a first isolation layer and a second isolation layer are formed, an initial isolation structure is formed by thinning the second isolation layer, and a preset height difference is formed between the first isolation layer and the initial isolation structure. Compared with the method of forming the sacrificial layer on the dielectric layer in the prior art, the technical scheme of the invention simplifies the process steps, reduces the process difficulty and is beneficial to improving the yield and the efficiency of forming the semiconductor structure.

Description

Method for forming semiconductor structure
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a method for forming a semiconductor structure.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Transistors are currently being widely used as one of the basic semiconductor devices. Therefore, as the density and integration of semiconductor devices are increased, the gate size of the planar transistor is shorter and shorter, the control capability of the conventional planar transistor on channel current is weakened, a short channel effect occurs, leakage current is increased, and the electrical performance of the semiconductor device is finally affected.
In order to overcome the short channel body effect of the transistor and suppress the leakage current, a fin field effect transistor (FinFET) is proposed in the prior art, and the fin field effect transistor is a common multi-faceted gate device. The structure of the fin field effect transistor comprises: the semiconductor device comprises a fin part and an isolation layer, wherein the fin part and the isolation layer are positioned on the surface of a semiconductor substrate, the isolation layer covers part of the side wall of the fin part, and the surface of the isolation layer is lower than the top of the fin part; the grid electrode structure is positioned on the surface of the isolation layer, the top of the fin part and the surface of the side wall; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
With the continuous reduction of the size of the semiconductor device, the distance between adjacent fin portions is reduced, which causes the difficulty of the process for forming the semiconductor structure to be increased and the process flow to be complicated.
Disclosure of Invention
The invention provides a method for forming a semiconductor structure, which aims to simplify the process flow and reduce the process difficulty.
To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate is provided with a plurality of discrete fin parts which are arranged in an array; forming a first isolation layer between adjacent fin parts in the extending direction of the fin parts and a second isolation layer between adjacent fin parts in the extending direction of the vertical fin parts; thinning the second isolation layer to form an initial isolation structure so as to form a preset height difference between the top surface of the first isolation layer and the initial isolation structure; and etching back the first isolation layer and the initial isolation structure to form a first isolation structure and a second isolation structure respectively, wherein the second isolation structure exposes out of part of the side wall surface of the fin part, and the top surface of the first isolation structure is higher than that of the second isolation structure.
Optionally, the step of thinning the second isolation layer includes: forming a protective layer on the first isolation layer, wherein the second isolation layer is exposed out of the protective layer; removing partial materials of the second isolation layer by taking the protection layer as a mask to form an initial isolation structure so as to realize thinning; after the thinning process is performed on the second isolation layer and before the etching back of the first isolation layer and the initial isolation structure, the forming method further includes: and removing the protective layer.
Optionally, in the step of forming the protective layer on the first isolation layer, the protective layer is made of photoresist.
Optionally, the step of forming the protective layer on the first isolation layer includes: forming a protective layer on the first isolation layer by adopting a coating process and a photoetching process; the step of removing the protective layer comprises: and removing the protective layer by ashing.
Optionally, the thickness of the protective layer is within
Figure BDA0001169790400000025
To
Figure BDA0001169790400000026
Within the range.
Optionally, in the step of forming the first isolation layer and the second isolation layer, the first isolation layer and the second isolation layer are made of the same material.
Optionally, in the step of forming the first isolation layer and the second isolation layer, the first isolation layer and the second isolation layer are both made of silicon oxide.
Optionally, in the step of thinning the second isolation layer, the preset height difference is set at
Figure BDA0001169790400000021
To
Figure BDA0001169790400000022
Within the range; after etching back the first isolation layer and the initial isolation structure, a height difference between a top surface of the first isolation structure and a top surface of the second isolation structure is
Figure BDA0001169790400000023
To
Figure BDA0001169790400000024
Within the range.
Optionally, in the step of forming the substrate, a mask layer is further disposed on the fin portion; in the step of forming the first isolation layer and the second isolation layer, the first isolation layer and the second isolation layer are flush with the mask layer; and thinning the mask layer in the process of thinning the second isolation layer to ensure that the residual mask layer has preset thickness.
Optionally, the step of forming the substrate includes: providing a substrate; forming the mask layer on the substrate; and etching the substrate by taking the mask layer as a mask to form the substrate and a plurality of discrete fin parts positioned on the substrate.
Optionally, the step of forming the first isolation layer and the second isolation layer includes: filling a dielectric material between the fin parts to form a dielectric material layer; and carrying out planarization treatment on the dielectric material layer until the mask layer is exposed, and forming the first isolation layer and the second isolation layer.
Optionally, in the step of performing thinning processing on the second isolation layer, the etching rate of the mask layer is equal to the etching rate of the second isolation layer.
Optionally, the step of thinning the second isolation layer includes: and performing thinning treatment in a dry etching mode.
Optionally, before the mask layer is thinned, the thickness of the mask layer is greater than or equal to that of the mask layer
Figure BDA0001169790400000031
In the step of thinning the second isolation layer, the preset height difference is
Figure BDA0001169790400000032
To
Figure BDA0001169790400000033
Within the range; after the mask layer is thinned, the preset thickness of the residual mask layer is
Figure BDA0001169790400000035
To
Figure BDA0001169790400000034
Within the range.
Optionally, the step of etching back the first isolation layer and the initial isolation structure includes: performing first etching on the first isolation layer and the initial isolation structure to enable the remaining initial isolation structure to be flush with the top of the fin part and expose the mask layer; removing the mask layer to expose the top surface of the fin part; and performing second etching on the remaining first isolation layer and the initial isolation structure to form the first isolation structure and the second isolation structure.
Optionally, in the step of performing the first etching, the first etching is performed by using a SiCoNi etching method.
Optionally, in the step of forming the substrate, the mask layer is made of silicon nitride; and in the step of removing the mask layer, removing the mask layer by adopting a wet etching mode.
Optionally, in the step of performing the second etching, the second etching is performed in a SiCoNi etching manner.
Optionally, after the first isolation structure and the second isolation structure are formed, the forming method further includes: and forming a dummy gate structure on the first isolation structure and a gate structure on the fin, wherein the gate structure crosses the fin and covers the partial top and partial side wall surface of the fin.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, after a first isolation layer and a second isolation layer are formed, an initial isolation structure is formed by thinning the second isolation layer, and a preset height difference is formed between the first isolation layer and the initial isolation structure. Compared with the method of forming the sacrificial layer on the dielectric layer in the prior art, the technical scheme of the invention simplifies the process steps, reduces the process difficulty and is beneficial to improving the yield and the efficiency of forming the semiconductor structure.
In an alternative scheme of the invention, the surface of the fin portion is provided with a mask layer, the top surfaces of the first isolation layer and the second isolation layer are flush with the top surface of the mask layer, and the mask layer is thinned to a preset thickness in the process of back-etching the second isolation layer. The existence of the mask layer can effectively protect the fin part from being damaged in the process of back etching the second isolation structure, and the performance of the formed semiconductor structure is improved.
Drawings
FIGS. 1-4 are schematic structural diagrams of steps of a method for forming a semiconductor structure;
fig. 5 to 19 are schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the invention.
Detailed Description
As can be seen from the background art, the semiconductor structure forming method in the prior art has a problem of complicated process. The reason for the complex process is now analyzed in conjunction with a method of forming a semiconductor structure:
as device dimensions decrease, the distance between adjacent transistors also decreases. For finfet devices, the distance between adjacent fins is getting smaller. Specifically, the distance (Head to Head, HTH) between the ends of adjacent fins is smaller and smaller along the extending direction of the fins. The reduced distance between the ends of adjacent fins can cause bridging problems between adjacent devices, resulting in degraded performance of the resulting semiconductor structure. For this reason, the prior art introduces a Single Diffusion Break (SDB) structure.
Fig. 1 to 4 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure with a single diffusion barrier structure.
Referring to fig. 1, a substrate 10 is formed, and the substrate 10 has a plurality of discrete fins 11 thereon, and the plurality of fins 11 are arranged in an array. The extending direction of the fin portion 11 is a first direction (as aa in fig. 1), and the extending direction perpendicular to the fin portion 11 is a second direction (as bb in fig. 1).
With continued reference to fig. 1, a dielectric material is filled between adjacent fins 11 to form a dielectric layer 15 flush with the top of the fins 11, and the dielectric layer 15 located between adjacent fins 11 along the second direction forms a second isolation layer 12 b.
Referring to fig. 2, a mask layer 13 is formed on the fin portion 11 and the second isolation layer 12b, a filling opening is formed in the mask layer 13, and a dielectric layer between adjacent fin portions 11 along the first direction is exposed at the bottom of the filling opening; and forming a sacrificial layer 14 in the filling opening, wherein the sacrificial layer 14 and the dielectric layer 15 between the adjacent fins 11 along the first direction form a first isolation layer 12 a.
Referring to fig. 3, the mask layer 13 (shown in fig. 2) is removed to expose the second isolation layer 12 b. The top surface of the first isolation layer 12a and the top surface of the second isolation layer 12b have a predetermined height difference h.
Referring to fig. 4, the first isolation layer 12a and the second isolation layer 12b are etched back to form a first isolation structure 16a and a second isolation structure 16b, the second isolation structure 16b exposes a portion of the sidewall of the fin 11, and a top surface of the first isolation structure 16a is higher than a top surface of the second isolation structure 16 b.
As shown in fig. 2 and 3, after the dielectric layer is formed, a mask layer 13 is formed on the fins 11 and the second isolation layer 12b, filling openings are formed in the mask layer 13, and a sacrificial layer 14 is formed in the filling openings, so that a first isolation layer 12a is formed on the dielectric layer between the sacrificial layer 14 and the fins 11 adjacent to each other in the first direction under the sacrificial layer 14, and a preset height difference h is formed between the top surfaces of the first isolation layer 12a and the second isolation layer 12 b. That is, the sacrificial layer 14 is formed to heighten the dielectric layer 15 between the fins 11 adjacent in the first direction, so that a predetermined height difference h is formed between the first isolation layer 12a and the second isolation layer 12 b. The method has multiple steps and complex process.
To solve the above technical problem, the present invention provides a method for forming a semiconductor structure, including:
forming a substrate, wherein the substrate is provided with a plurality of discrete fin parts which are arranged in an array; forming a first isolation layer between adjacent fin parts in the extending direction of the fin parts and a second isolation layer between adjacent fin parts in the extending direction of the vertical fin parts; thinning the second isolation layer to form an initial isolation structure so as to form a preset height difference between the top surface of the first isolation layer and the initial isolation structure; and etching back the first isolation layer and the initial isolation structure to form a first isolation structure and a second isolation structure respectively, wherein the second isolation structure exposes out of part of the side wall surface of the fin part, and the top surface of the first isolation structure is higher than that of the second isolation structure.
According to the technical scheme, after a first isolation layer and a second isolation layer are formed, an initial isolation structure is formed by thinning the second isolation layer, and a preset height difference is formed between the first isolation layer and the initial isolation structure. Compared with the method of forming the sacrificial layer on the dielectric layer in the prior art, the technical scheme of the invention simplifies the process steps, reduces the process difficulty and is beneficial to improving the yield and the efficiency of forming the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 5 to 19 are schematic structural diagrams corresponding to steps of a semiconductor structure forming method according to an embodiment of the present invention.
Referring to fig. 5 and 6, fig. 6 is a schematic view of a cross-sectional structure of fig. 5 taken along line CC. Forming a substrate 100, wherein the substrate 100 has a plurality of discrete fins 110, and the plurality of fins 110 are arranged in an array.
The substrate 100 is used to provide an operating platform for a semiconductor process, and the fin 110 is used to form a finfet. Specifically, on the substrate 100, the plurality of discrete fins 110 are arranged in an array in a fin extending direction (e.g., AA in fig. 5) and a vertical fin extending direction (e.g., BB in fig. 5).
It should be noted that fig. 5 only shows 4 fins 110 arranged in an array in the fin extending direction and the vertical fin extending direction.
The material of the substrate 100 is monocrystalline silicon. In other embodiments of the present invention, the substrate may also be a polysilicon substrate, an amorphous silicon substrate or a silicon germanium substrate, a carbon silicon substrate, a silicon on insulator substrate, a germanium on insulator substrate, a glass substrate or a III-V compound substrate, such as a gallium nitride substrate or a gallium arsenide substrate. The material of the substrate may be chosen to be suitable for process requirements or easy to integrate.
The material of the fin 110 is the same as that of the substrate 100, and is also single crystal silicon. In other embodiments of the present invention, the material of the fin may be different from the material of the substrate, and may be selected from materials suitable for forming a fin, such as germanium, silicon carbon, or gallium arsenide.
In this embodiment, the fin 110 further has a mask layer 120 thereon.
The mask layer 120 serves as an etch mask in the process of forming the substrate 100 and the fin 110. In addition, the mask layer 120 is also used to stop in a subsequent semiconductor process, and is used to define the heights of the first isolation layer and the second isolation layer formed subsequently. The mask layer 120 is also used to protect the fin 110 in a subsequent semiconductor process, and to prevent the fin 110 from being damaged.
Specifically, the step of forming the substrate 100 includes: providing a substrate; forming a mask layer 120 on the substrate; and etching the substrate by using the mask layer 120 as a mask to form the substrate 100 and a plurality of discrete fin portions 110 on the substrate 100.
In this embodiment, the mask layer 120 is made of silicon nitride. The step of forming the mask layer 120 includes: forming a mask material layer on the substrate; forming a pattern layer on the mask material layer; and etching the mask material layer by taking the pattern layer as a mask until the surface of the substrate is exposed so as to form the mask layer 120.
The pattern layer is used for patterning the mask material layer so as to define the size and the position of the fin portion.
In this embodiment, the pattern layer is a patterned photoresist layer and may be formed through a coating process and a photolithography process. In other embodiments of the present invention, the patterned layer may also be a mask formed by a multi-patterning mask process, so as to reduce the feature size of the fin portion and the distance between adjacent fin portions, and improve the integration level of the formed semiconductor structure. The multiple patterning mask process comprises the following steps: a Self-aligned Double patterning (SaDP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (SaDDP) process.
It should be noted that, in this embodiment, the method of forming the substrate 100 and the fin portion 110 by one etching is only an example. In other embodiments of the present invention, a substrate and an initial fin portion located on the substrate may also be formed by performing first etching on the base; and performing second etching on the initial fin part to form a plurality of fin parts arranged along the extending direction of the fin part. The mask layer may be an etching mask layer in the second etching.
Fig. 7 to 9 are combined, in which fig. 7 is a perspective view based on fig. 5, fig. 8 is a schematic sectional structure along DD direction in fig. 7, and fig. 9 is a schematic sectional structure along EE direction in fig. 7. A first isolation layer 131 is formed between adjacent fins 110 along a fin extension direction (e.g., AA in fig. 5), and a second isolation layer 132 is formed between adjacent fins 110 along a direction perpendicular to the fin extension direction (e.g., BB in fig. 5).
The first isolation layer 131 is used to achieve electrical isolation between adjacent fins 110 along a fin extending direction (e.g., AA in fig. 5), and the second isolation layer 132 is used to achieve electrical isolation between adjacent fins 110 perpendicular to the fin extending direction (e.g., BB in fig. 5).
In this embodiment, the first isolation layer 131 and the second isolation layer 132 are made of the same material and are both silicon oxide. In other embodiments of the present invention, the material of the first isolation layer and the second isolation layer may also be selected from silicon nitride, silicon oxynitride, a low-K dielectric material (dielectric constant greater than or equal to 2.5 and less than 3.9), or an ultra-low-K dielectric material (dielectric coefficient less than 2.5).
In this embodiment, the fin 110 further has a mask layer 120 thereon. The first isolation structure 131 and the second isolation structure 132 are flush with the mask layer 120.
The first isolation layer 131 and the second isolation layer 132 may be simultaneously formed. Specifically, the step of forming the first isolation layer 131 and the second isolation layer 132 includes: filling a dielectric material between adjacent fins 110 to form a dielectric material layer, wherein the dielectric material layer covers the fins 110; and performing planarization treatment on the dielectric material layer until the mask layer 120 is exposed, so as to form the first isolation layer 131 and the second isolation layer 132.
With the improvement of the integration level of the semiconductor device, the distance between the adjacent fins 110 is reduced, the aspect ratio of the trench between the adjacent fins 110 is increased, and the difficulty of the process for filling the dielectric material is increased. In order to achieve sufficient filling of the dielectric material and avoid forming a gap between adjacent fins 110, in this embodiment, the step of forming the dielectric material layer includes: the dielectric material is filled by means of Fluid Chemical Vapor Deposition (FCVD). In other embodiments of the present invention, the dielectric material layer may also be formed by a High Aspect Ratio (HARP) Process.
And in the step of carrying out planarization treatment on the medium material layer, the planarization treatment is carried out in a chemical mechanical polishing mode. The mask layer 120 acts as a stop during the planarization process, and thus the chemical mechanical polishing stops until the mask layer 120 is exposed. The first isolation layer 131 and the second isolation layer 132 are formed to be flush with the mask layer 120.
Referring to fig. 10 to 13, the second isolation layer 132 (shown in fig. 10) is thinned to form an initial isolation structure 133, so that a predetermined height difference H is formed between the top surface of the first isolation layer 131 and the initial isolation structure 133.
The thinning process is used to form the initial isolation structure 133 and make a preset height difference H between the top surface of the first isolation layer 131 and the initial isolation structure 133, so as to subsequently form a first isolation structure and a second isolation structure with a height difference on the top surface.
It should be noted that, in this embodiment, the materials of the first isolation layer 131 and the second isolation layer 132 are the same, so that the removal rates of the first isolation layer 131 and the second isolation layer 132 are equal in the subsequent etching back process of the first isolation layer 131 and the second isolation layer 132.
In this embodiment, the semiconductor structure is a single-diffusion structureA Single Diffusion Break (SDB), such that the first isolation structure is formed flush with the fin 110, and the height difference between the top surface of the second isolation structure and the top surface of the fin 110 is between
Figure BDA0001169790400000091
To
Figure BDA0001169790400000092
Within the range, that is, the difference in height between the top surface of the first isolation structure and the top surface of the second isolation structure is formed
Figure BDA0001169790400000093
To
Figure BDA0001169790400000094
Within the range. Therefore, in the step of thinning the second isolation layer 132, the predetermined height difference H is
Figure BDA0001169790400000095
To
Figure BDA0001169790400000096
Within the range.
Since the materials of the first isolation layer 131 and the second isolation layer 132 are the same, in this embodiment, the first isolation layer 131 is prevented from being damaged during the thinning process by forming a protection layer on the first isolation layer 131.
Specifically, the manner of performing the thinning process on the second isolation layer 132 in this embodiment is described in detail below with reference to the drawings.
Referring to fig. 10 and 11, fig. 10 is a perspective view based on fig. 7, and fig. 11 is a schematic sectional view taken along line FF in fig. 10. A protection layer 140 is formed on the first isolation layer 131, and the protection layer 140 exposes the second isolation layer 132.
In the process of thinning the second isolation layer 132, the protection layer 140 is used to protect the first isolation layer 131 and prevent the first isolation layer 131 from being damaged, so as to form a height difference between the first isolation layer 131 and the second isolation layer 132. In this embodiment, the fin 110 further has a mask layer 120 thereon, so that the protection layer 140 is located on the first isolation layer 131, and exposes the second isolation layer 132 and the corresponding region of the mask layer 120.
In this embodiment, the material of the protection layer 140 is photoresist, and the protection layer 140 may be formed on the first isolation layer 131 by using a coating process and a photolithography process.
Specifically, the step of forming the protection layer 140 includes: forming a protective material layer covering the first isolation layer 131, the second isolation layer 132 and the mask layer 120 by a coating process; and photoetching the protective material layer to expose the second isolation layer 132 and the area corresponding to the mask layer 120.
If the thickness of the protection layer 140 is too small, it is difficult to protect the first isolation structure during the thinning process of the second isolation layer 132, which may affect the formation of the height difference between the first isolation structure and the remaining second isolation structure; if the thickness of the protective layer 140 is too large, it may cause a problem of material waste and increase process difficulty. In this embodiment, the thickness of the protection layer 140 is within
Figure BDA0001169790400000101
To
Figure BDA0001169790400000102
Within the range.
It should be noted that, in the present embodiment, the method of forming the protection layer 140 by using photoresist is only an example. In other embodiments of the present invention, the protection layer may also be a hard mask layer or other film layers.
Referring to fig. 12 and 13, fig. 12 is a perspective view based on fig. 10, and fig. 13 is a schematic sectional view taken along line GG in fig. 12. With the protection layer 140 (as shown in fig. 10) as a mask, a portion of the material of the second isolation layer 132 is removed to form an initial isolation structure 133, so as to achieve thinning.
In this embodiment, the fin 110 has the mask layer 120 thereon, and the first isolation layer 131 and the second isolation layer 132 are flush with the top surface of the mask layer 120, so that the mask layer 120 is thinned during the thinning process of the second isolation layer 132, so that the remaining mask layer 120 has a predetermined thickness.
Specifically, it is right in the step of thinning processing is carried out to second isolation layer 132, thinning processing is right mask layer 120's etching rate with thinning processing is right the etching rate of second isolation layer 132 equals, is favorable to reducing right the control degree of difficulty of second isolation layer 132 thinning processing technology.
In this embodiment, the second isolation layer 132 and the mask layer 120 are thinned by dry etching.
Specifically, the dry etching process parameters include: gas pressure is in the range of 5mTorr to 15mTorr, source power is in the range of 50W to 150W, bias voltage is in the range of 500V to 1000V, and process gas comprises CH4And He, the process gas flow rate is: CH (CH)4In the range of 70sccm to 150sccm, in the range of 100sccm to 200sccm, and at a process temperature in the range of 60 ℃ to 90 ℃.
It should be noted that, in order to avoid the fin portion 110 being damaged by the thinning process, in this embodiment, the thinning process is performed until the thickness of the mask layer 120 reaches the preset thickness D.
After the mask layer 120 is thinned, if the preset thickness D of the remaining mask layer 120 is too small, the protection capability of the mask layer 120 on the top of the fin 110 is difficult to ensure, and the fin 110 may be damaged in the thinning process; if the predetermined thickness D of the remaining mask layer 120 is too large, the process time for subsequently removing the mask layer 120 may be prolonged, and the process efficiency may be reduced. Therefore, in this embodiment, after the mask layer 120 is thinned, the predetermined thickness D of the remaining mask layer 120 is within the range of
Figure BDA0001169790400000111
To
Figure BDA0001169790400000112
Within the range.
It should be noted that, after the mask layer 120 is thinned, the predetermined thickness of the remaining mask layer 120 is set to be equal to
Figure BDA0001169790400000113
To
Figure BDA0001169790400000114
Within the range. And after the second isolation layer 132 is thinned, the preset height difference H between the top surface of the first isolation layer 131 and the initial isolation structure 133 is
Figure BDA0001169790400000117
To
Figure BDA0001169790400000115
Within the range; therefore, in order to make the predetermined thickness D of the remaining mask layer 120 meet the requirement, before the mask layer 120 is thinned, the thickness of the mask layer 120 is greater than or equal to that of the mask layer 120
Figure BDA0001169790400000116
With continued reference to fig. 12 and 13, the presence of the protection layer 140 (as shown in fig. 11) may affect the subsequent etching back of the first isolation layer 131 and the initial isolation structure 133. Therefore, after the thinning process is performed on the second isolation layer 132 and before the etching back of the first isolation layer 131 and the initial isolation structure 133, the forming method further includes: the protective layer 140 is removed (as shown in fig. 10).
Specifically, the material of the protection layer 140 is photoresist, so that the protection layer 140 is removed by ashing.
Specifically, in the step of removing the protective layer 140 by ashing, the process parameters include: the gas pressure is in the range of 10mTorr to 20mTorr, the source power is in the range of 800W to 1000W, the bias voltage is 0V, and the process gas comprises O2The process gas flow is as follows: o is2Is in the range of 150sccm to 250sccmThe process temperature is in the range of 40 ℃ to 60 ℃.
Referring to fig. 14 to 19, the first isolation layer 131 and the initial isolation structure 133 are etched back to form a first isolation structure 151 and a second isolation structure 152, respectively, wherein the second isolation structure 152 exposes a portion of the sidewall surface of the fin 110, and a top surface of the first isolation structure 151 is higher than a top surface of the second isolation structure 152.
The step of etching back the first isolation layer 131 and the initial isolation structure 133 serves to form a first isolation structure 151 and a second isolation structure 152. The second isolation structure 152 exposes a portion of the sidewall surface of the fin 110, so that a subsequently formed gate structure can cover a portion of the sidewall surface of the fin 110.
Since there is a predetermined height difference H between the top of the first isolation layer 131 and the top of the initial isolation structure 133, the first isolation layer 131 and the initial isolation structure 133 are etched at the same time in the step of etching back the first isolation layer 131 and the initial isolation structure 133. There is also a height difference between the top surface of the first isolation structure 151 and the top surface of the second isolation structure 152.
Specifically, the materials of the first isolation layer 131 and the second isolation layer 132 are the same, that is, the materials of the first isolation layer 131 and the initial isolation structure 133 are the same, and in the step of etching back the first isolation layer 131 and the initial isolation structure 133, the etching rate of the first isolation layer 131 is equal to the etching rate of the initial isolation structure 133, so that the height difference between the top of the first isolation structure 151 and the top of the second isolation structure 152 is equivalent to the preset height difference H.
Specifically, the preset height difference H (as shown in fig. 12) is set at
Figure BDA0001169790400000121
To
Figure BDA0001169790400000122
In range, so that the first isolation layer 131 and the initial layer are etched backAfter the isolation structure 133, the top surface of the first isolation structure 131 and the top surface of the second isolation structure 133 have a height difference
Figure BDA0001169790400000124
To
Figure BDA0001169790400000123
Within the range.
It should be noted that in the present embodiment, the semiconductor structure is a single diffusion isolation device (SDB), so the top surface of the second isolation structure 152 is lower than the top surface of the fin 110.
Specifically, the step of forming the first isolation structure 151 and the second isolation structure 152 includes:
referring to fig. 14 to 16, wherein fig. 14 is a perspective view based on fig. 12, fig. 15 is a schematic sectional structure view taken along line HH of fig. 14, and fig. 16 is a schematic sectional structure view taken along line II of fig. 14.
Performing a first etching on the first isolation layer 131 and the initial isolation structure 133, so that the remaining initial isolation structure 133 is flush with the top of the fin 110, and the mask layer 120 is exposed.
The first etch is used to expose the mask layer 120, thereby providing a process surface for subsequent steps of removing the mask layer 120.
In order to avoid the first etching from damaging the fin portion 110, in this embodiment, the first etching is performed by a SiCoNi etching method.
Referring to fig. 17, the masking layer 120 is removed (as shown in fig. 16), exposing the top surface of the fin 110.
The step of removing the mask layer 120 serves to expose the top surface of the fin 110, so that a subsequently formed gate structure covers a portion of the top surface of the fin 110. In this embodiment, the mask layer 120 is made of silicon nitride. The mask layer 120 is removed by means of wet etching with phosphoric acid.
Referring to fig. 18 and 19, fig. 19 is a schematic view of a cross-sectional structure taken along the line JJ in fig. 18.
And performing second etching on the remaining first isolation layer 131 (shown in fig. 17) and the initial isolation structure 133 (shown in fig. 17) to form the first isolation structure 151 and the second isolation structure 152.
Specifically, the remaining first isolation layer 131 and the initial isolation structure 133 are subjected to a second etching to expose a portion of the sidewall surface of the fin 110, so as to form a first isolation structure 151 and a second isolation structure 152. In order to avoid damaging the fin portion 110, in the step of performing the second etching, the second etching is performed in a SiCoNi etching manner.
It should be noted that, in this embodiment, the semiconductor structure is a single diffusion blocking device, so after the first isolation structure 151 and the second isolation structure 152 are formed, the forming method further includes: forming a dummy gate structure on the first isolation structure 151 and a gate structure on the fin 110, wherein the gate structure crosses over the fin 110 and covers part of the top and part of the sidewall of the fin 110.
The method for forming the gate structure and the dummy gate structure is the same as that in the prior art, and the description of the invention is omitted.
In summary, according to the technical solution of the present invention, after forming the first isolation layer and the second isolation layer, the second isolation layer is thinned to form the initial isolation structure, so that a predetermined height difference is formed between the first isolation layer and the initial isolation structure. Compared with the method of forming the sacrificial layer on the dielectric layer in the prior art, the technical scheme of the invention simplifies the process steps, reduces the process difficulty and is beneficial to improving the yield and the efficiency of forming the semiconductor structure. In an alternative embodiment of the present invention, the fin portion has a mask layer on a surface thereof, top surfaces of the first isolation layer and the second isolation layer are flush with a top surface of the mask layer, and the mask layer is thinned to a predetermined thickness in a process of etching back the second isolation layer. The existence of the mask layer can effectively protect the fin part from being damaged in the process of back etching the second isolation structure, and the performance of the formed semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (18)

1. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate is provided with a plurality of discrete fin parts which are arranged in an array; the fin part is also provided with a mask layer;
forming a first isolation layer between adjacent fin parts in the extending direction of the fin parts and a second isolation layer between adjacent fin parts in the extending direction of the vertical fin parts; the first isolation layer and the second isolation layer are flush with the mask layer;
thinning the second isolation layer to form an initial isolation structure so as to form a preset height difference between the top surface of the first isolation layer and the initial isolation structure;
etching back the first isolation layer and the initial isolation structure to form a first isolation structure and a second isolation structure respectively, wherein the second isolation structure exposes part of the side wall surface of the fin portion, and the top surface of the first isolation structure is higher than that of the second isolation structure;
and thinning the mask layer in the process of thinning the second isolation layer to ensure that the residual mask layer has preset thickness.
2. The method of forming in accordance with claim 1, wherein thinning the second isolation layer comprises:
forming a protective layer on the first isolation layer, wherein the second isolation layer is exposed out of the protective layer;
removing partial materials of the second isolation layer by taking the protection layer as a mask to form an initial isolation structure so as to realize thinning;
after the thinning process is performed on the second isolation layer and before the etching back of the first isolation layer and the initial isolation structure, the forming method further includes: and removing the protective layer.
3. The forming method according to claim 2, wherein in the step of forming the protective layer on the first isolation layer, a material of the protective layer is a photoresist.
4. The forming method of claim 3, wherein the step of forming the protective layer on the first isolation layer comprises: forming a protective layer on the first isolation layer by adopting a coating process and a photoetching process;
the step of removing the protective layer comprises: and removing the protective layer by ashing.
5. The method of claim 2, wherein the protective layer has a thickness of
Figure FDA0002220785030000021
To
Figure FDA0002220785030000022
Within the range.
6. The forming method of claim 1, wherein in the step of forming the first isolation layer and the second isolation layer, the first isolation layer and the second isolation layer are the same material.
7. The forming method according to claim 1 or 6, wherein in the step of forming the first isolation layer and the second isolation layer, a material of each of the first isolation layer and the second isolation layer is silicon oxide.
8. The method of forming of claim 1 or 6, wherein the step of thinning the second isolation layerIn the step, the preset height difference is
Figure FDA0002220785030000023
To
Figure FDA0002220785030000024
Within the range;
after etching back the first isolation layer and the initial isolation structure, a height difference between a top surface of the first isolation structure and a top surface of the second isolation structure is
Figure FDA0002220785030000025
To
Figure FDA0002220785030000026
Within the range.
9. The method of forming of claim 1, wherein forming the substrate comprises:
providing a substrate;
forming the mask layer on the substrate;
and etching the substrate by taking the mask layer as a mask to form the substrate and a plurality of discrete fin parts positioned on the substrate.
10. The method of forming of claim 1, wherein the step of forming the first isolation layer and the second isolation layer comprises:
filling a dielectric material between the fin parts to form a dielectric material layer;
and carrying out planarization treatment on the dielectric material layer until the mask layer is exposed, and forming the first isolation layer and the second isolation layer.
11. The forming method according to claim 1, wherein in the step of thinning the second isolation layer, an etching rate of the mask layer by the thinning is equal to an etching rate of the second isolation layer by the thinning.
12. The method of forming in accordance with claim 11, wherein thinning the second isolation layer comprises: and performing thinning treatment in a dry etching mode.
13. The method of claim 11, wherein the thickness of the mask layer is greater than or equal to the thickness of the mask layer before the thinning process is performed on the mask layer
Figure FDA0002220785030000031
In the step of thinning the second isolation layer, the preset height difference is
Figure FDA0002220785030000032
To
Figure FDA0002220785030000033
Within the range;
after the mask layer is thinned, the preset thickness of the residual mask layer is
Figure FDA0002220785030000034
To
Figure FDA0002220785030000035
Within the range.
14. The method of forming of claim 1, wherein the step of etching back the first isolation layer and the initial isolation structure comprises:
performing first etching on the first isolation layer and the initial isolation structure to enable the remaining initial isolation structure to be flush with the top of the fin part and expose the mask layer;
removing the mask layer to expose the top surface of the fin part;
and performing second etching on the remaining first isolation layer and the initial isolation structure to form the first isolation structure and the second isolation structure.
15. The method of forming of claim 14 wherein the step of performing a first etch uses a SiCoNi etch to perform the first etch.
16. The method of claim 14, wherein in the step of forming the substrate, the mask layer is made of silicon nitride;
and in the step of removing the mask layer, removing the mask layer by adopting a wet etching mode.
17. The method of forming of claim 14 wherein the step of performing a second etch is performed by a SiCoNi etch.
18. The method of forming of claim 1, wherein after forming the first isolation structure and the second isolation structure, the method of forming further comprises: and forming a dummy gate structure on the first isolation structure and a gate structure on the fin, wherein the gate structure crosses the fin and covers the partial top and partial side wall surface of the fin.
CN201611100045.1A 2016-12-02 2016-12-02 Method for forming semiconductor structure Active CN108155148B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201611100045.1A CN108155148B (en) 2016-12-02 2016-12-02 Method for forming semiconductor structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201611100045.1A CN108155148B (en) 2016-12-02 2016-12-02 Method for forming semiconductor structure

Publications (2)

Publication Number Publication Date
CN108155148A CN108155148A (en) 2018-06-12
CN108155148B true CN108155148B (en) 2020-05-08

Family

ID=62470448

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611100045.1A Active CN108155148B (en) 2016-12-02 2016-12-02 Method for forming semiconductor structure

Country Status (1)

Country Link
CN (1) CN108155148B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123773B1 (en) * 2014-08-15 2015-09-01 Globalfoundries Inc. T-shaped single diffusion barrier with single mask approach process flow
US9368496B1 (en) * 2015-01-30 2016-06-14 Globalfoundries Inc. Method for uniform recess depth and fill in single diffusion break for fin-type process and resulting devices
CN107689330A (en) * 2016-08-04 2018-02-13 中芯国际集成电路制造(北京)有限公司 A kind of semiconductor devices and preparation method, electronic installation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9123773B1 (en) * 2014-08-15 2015-09-01 Globalfoundries Inc. T-shaped single diffusion barrier with single mask approach process flow
US9368496B1 (en) * 2015-01-30 2016-06-14 Globalfoundries Inc. Method for uniform recess depth and fill in single diffusion break for fin-type process and resulting devices
CN107689330A (en) * 2016-08-04 2018-02-13 中芯国际集成电路制造(北京)有限公司 A kind of semiconductor devices and preparation method, electronic installation

Also Published As

Publication number Publication date
CN108155148A (en) 2018-06-12

Similar Documents

Publication Publication Date Title
TWI416634B (en) Method of forming an integrated circuit structure
KR100518606B1 (en) Method for fabricating a recess channel array transistor using a mask layer having high etch selectivity for silicon substrate
US8936986B2 (en) Methods of forming finfet devices with a shared gate structure
CN108735813B (en) Semiconductor structure and forming method thereof
CN107785315B (en) Method for forming semiconductor structure
US11742414B2 (en) Semiconductor device with fins
CN113594039B (en) Semiconductor structure and forming method thereof
US10658489B2 (en) Semiconductor structure and fabrication method thereof
CN107768308B (en) Semiconductor structure and forming method thereof
CN111129142B (en) Semiconductor device and method of forming the same
CN109003899B (en) Semiconductor structure, forming method thereof and forming method of fin field effect transistor
US11658076B2 (en) Semiconductor device and fabrication method thereof
CN113838934B (en) Semiconductor structure and forming method thereof
CN108155148B (en) Method for forming semiconductor structure
CN113496894B (en) Method for forming semiconductor structure
CN111769046B (en) Semiconductor structure and forming method thereof
CN111081547B (en) Semiconductor device and method of forming the same
CN110556338B (en) Semiconductor device and method of forming the same
CN107731917B (en) Method for forming semiconductor structure
CN112151382A (en) Semiconductor structure and forming method thereof
CN107516674B (en) Method for forming fin field effect transistor
US11837497B2 (en) Semiconductor device
CN107492501B (en) Method for forming fin field effect transistor
CN108022843B (en) Method for forming semiconductor structure
CN115810582A (en) Semiconductor structure and forming method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant