CN107492501B - Method for forming fin field effect transistor - Google Patents

Method for forming fin field effect transistor Download PDF

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CN107492501B
CN107492501B CN201610420451.XA CN201610420451A CN107492501B CN 107492501 B CN107492501 B CN 107492501B CN 201610420451 A CN201610420451 A CN 201610420451A CN 107492501 B CN107492501 B CN 107492501B
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fin
etching
thickness
edge region
edge
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CN107492501A (en
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李勇
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

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  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

A method for forming a fin field effect transistor comprises the following steps: providing a substrate comprising an effective area, first edge areas positioned at two sides of the effective area and a second edge area positioned at one side of the first edge area, wherein a fin part is formed on the substrate; forming a first pattern layer covering the fin part of the effective area and the fin part of the first edge area; etching to remove the fin part with the first thickness in the second edge region; forming a second graphic layer covering the fin part of the active area; and etching and removing the fin part with the second thickness in the first edge area by taking the second pattern layer as a mask, wherein the second thickness is smaller than the first thickness. According to the invention, the amount of the etched fin part on the substrate of the first edge region close to the effective region is reduced, so that the second pattern layer is reduced or prevented from being damaged by etching, the fin part on the substrate of the effective region is prevented from being exposed in an etching environment, the fin part on the substrate of the effective region is prevented from being damaged by etching, the fin part on the substrate of the effective region is ensured to have good appearance, and the performance of the formed fin field effect transistor is correspondingly improved.

Description

Method for forming fin field effect transistor
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a fin field effect transistor.
Background
With the continuous development of semiconductor process technology, the development trend of semiconductor process nodes following moore's law is continuously reduced. To accommodate the reduction in process nodes, the channel length of MOSFET fets has to be continuously shortened. The shortening of the channel length has the advantages of increasing the die density of the chip, increasing the switching speed of the MOSFET field effect transistor and the like.
However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage pinch-off (ping off) channel is increased, and the sub-threshold leakage (SCE) phenomenon, i.e. the so-called short-channel effect (SCE) is more likely to occur.
Therefore, in order to better accommodate the scaling requirements of device dimensions, semiconductor processes are gradually starting to transition from planar MOSFET transistors to three-dimensional transistors with higher performance, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, the control capability of the gate on a channel is much stronger than that of a planar MOSFET device, and the short channel effect can be well inhibited; and compared with other devices, the FinFET has better compatibility of the existing integrated circuit manufacturing technology.
However, the performance of the finfet formed by the prior art needs to be further improved.
Disclosure of Invention
The invention aims to provide a method for forming a fin field effect transistor, which improves the electrical performance of the formed fin field effect transistor.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a substrate, wherein the substrate comprises an effective area, first edge areas positioned at two opposite sides of the effective area, and a second edge area positioned at one side of the first edge area, the second edge area and the effective area are respectively positioned at two opposite sides of the first edge area, and discrete fin parts are formed on the effective area, the first edge area and the second edge area; forming a first graph layer on the fin part of the effective area and the substrate as well as the fin part of the first edge area and the substrate; etching and removing the fin part with the first thickness in the second edge region by taking the first pattern layer as a mask; removing the first graphic layer; forming a second graphic layer on the fin part of the effective area and the substrate; etching and removing the fin part with the second thickness in the first edge area by taking the second pattern layer as a mask, wherein the second thickness is smaller than the first thickness; and removing the second graphic layer.
Optionally, after the etching and removing the fin portion with the first thickness in the second edge region and the etching and removing the fin portion with the second thickness in the first edge region, the method further includes the steps of: and forming isolation layers on the side walls of the fins in the effective area and the side walls of the remaining fins in the first edge area on the substrate, wherein the top of each isolation layer is lower than that of the fin in the effective area.
Optionally, the isolation layer is further located on a sidewall of the remaining fin portion of the first edge region, and a top of the isolation layer is higher than a top of the remaining fin portion of the first edge region or is flush with the top of the remaining fin portion of the first edge region.
Optionally, after the fin portion with the second thickness in the first edge region is removed by etching, the thickness of the remaining fin portion in the first edge region is 1/5 to 2/3 of the thickness of the fin portion in the first edge region before etching.
Optionally, the fin portion with the second thickness in the first edge region is removed by etching by using a dry etching process.
Optionally, the process parameters of the dry etching process include: the etching gas comprises CF4、Si2F6、HCl、HBr、Cl2He, Ar or N2The flow rate of the etching gas is 40sccm to 80sccm, the pressure of the etching reaction chamber is 5 mTorr to 50 mTorr, the etching power is 200 watts to 2000 watts, and the temperature of the etching reaction chamber is 20 ℃ to 80 ℃.
Optionally, the etching rate of the fin portion with the first thickness in the second edge region removed by etching is a first etching rate; and the etching rate of the fin part with the second thickness in the first edge area is removed by etching is a second etching rate, and the second etching rate is equal to the first etching rate.
Optionally, the etching time for etching and removing the fin portion with the first thickness in the second edge region is a first time; and the etching time for etching and removing the fin part with the second thickness in the first edge area is a second time, and the second time is less than the first time.
Optionally, the process of removing the fin portion with the first thickness in the second edge region by etching includes removing the fin portion with the entire thickness in the second edge region by etching until the substrate of the second edge region is exposed.
Optionally, the process of removing the fin portion with the first thickness in the second edge region by etching includes removing the fin portion with a partial thickness in the second edge region by etching, and the top of the formed isolation layer is higher than the top of the remaining fin portion in the second edge region.
Optionally, in a direction parallel to the arrangement direction of the fin portions, distances between adjacent fin portions on the substrate are equal.
Optionally, in a direction parallel to the fin portion arrangement direction, a distance between adjacent fin portions on the substrate is 5 to 100 angstroms.
Optionally, the fin portion with the first thickness in the second edge region is removed by etching first, and then the fin portion with the second thickness in the first edge region is removed by etching.
Optionally, the fin portion with the second thickness in the first edge region is removed by etching, and then the fin portion with the first thickness in the second edge region is removed by etching.
Optionally, the second graphic layer is also located on the second edge region substrate.
Optionally, the second pattern layer is made of photoresist; the process for forming the second pattern layer comprises the following steps: forming an initial pattern film on the substrate of the effective area, the first edge area and the second edge area, wherein the initial pattern film is also positioned on the fin part; and removing the initial pattern film above the first edge area to form the second pattern layer.
Optionally, the number of the active region fins is greater than or equal to 1.
Optionally, before forming the isolation layer, a hard mask layer is further formed on the top of the fin portion; and in the process of forming the isolation layer, the hard mask layer is also removed.
Optionally, the process of forming the isolation layer includes: forming an isolation film on the substrate, wherein the isolation film is positioned on the side wall and the top of the fin part; carrying out planarization treatment on the top surface of the isolation film; and etching back to remove part of the thickness of the isolation film to form the isolation layer.
Optionally, the method further comprises the steps of: forming a grid electrode structure crossing the fin part of the effective region, wherein the grid electrode structure covers the top and the side wall of the fin part of the effective region; and doping the fin parts on the two sides of the grid structure to form a source drain doped region.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the technical scheme of the fin field effect transistor, the distance between the second edge region and the effective region is larger than the distance between the effective regions of the first edge region, and discrete fin parts are formed on the effective region, the first edge region and the second edge region substrate; forming a first pattern layer covering the fin part of the effective area and the fin part of the first edge area; etching and removing the fin part with the first thickness in the second edge region by taking the first pattern layer as a mask; and then, forming a second pattern layer covering the fin part in the active area, and etching and removing the fin part with the second thickness in the first edge area by taking the second pattern layer as a mask, wherein the second thickness is smaller than the first thickness. Therefore, in the invention, the amount of the first edge region fin part removed by etching is less than the amount of the second edge region fin part removed by etching, so that in the etching process of removing the second thickness fin part of the first edge region by etching, the etching damage of the etching process to the second pattern layer is less, and the fin part close to the first edge region on the substrate of the effective region is prevented from being exposed, thereby preventing the fin part on the substrate of the effective region from being damaged by etching, enabling the fin part on the substrate of the effective region to have good appearance, and further improving the electrical performance of the formed fin field effect tube.
In the alternative, isolation layers located on the sidewalls of the active region fins and the sidewalls of the remaining fins of the first edge region are formed on the substrate, the top of each isolation layer is lower than the top of each active region fin, and the top of each isolation layer is higher than the top of each remaining fin of the first edge region or flush with the top of each remaining fin of the first edge region. The isolation layer not only plays the electrical isolation effect between the adjacent fin portion on the effective area basement, still covers on the first marginal zone surplus fin portion, avoids the first marginal zone fin portion to expose the harmful effects of introducing.
Drawings
Fig. 1 to 8 are schematic cross-sectional views illustrating a finfet formation process according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the electrical performance of the finfet formed in the prior art needs to be improved.
In a finfet, a substrate typically includes an active region and an edge region adjacent to the active region, wherein fins are formed on the substrate in the active region and no fin is formed on the substrate in the edge region. Generally, the process steps for forming fins on the substrate in the active area include: firstly, forming discrete fin parts on the substrate of the effective region and the substrate of the edge region; then, forming a pattern layer covering the fin part on the substrate of the active area; etching and removing the fin part on the substrate of the edge region by taking the pattern layer as a mask; and removing the graph layer.
However, in the fin field effect transistor formed by the above method, the fin portion on the substrate of the active region is damaged, which causes changes in the shape and size of the fin portion, and the damage to the fin portion on the substrate of the active region, which is close to the edge region, is particularly serious.
The main causes of this problem, analyzed, include: because the fin part on the substrate of the edge region is completely etched and removed, the etching time of the etching process is long, so that the pattern layer is etched and lost, particularly the side wall of the pattern layer close to the edge region is seriously damaged, and the fin part on the substrate of the effective region is exposed in the etching environment, so that the fin part on the substrate of the effective region is etched; in addition, the pattern layer is limited by the conditions of the photolithography process, so that the edge position accuracy of the pattern layer is to be improved, and when the width of the pattern layer on the fin sidewall is smaller than the expected width, the fin sidewall is exposed due to small etching damage, which is one of the reasons that the fin portion next to the edge region on the active region substrate is easily exposed to the etching environment.
In order to solve the above problems, the present invention provides a method for forming a fin field effect transistor, including: providing a substrate, wherein the substrate comprises an effective area, first edge areas positioned at two opposite sides of the effective area, and a second edge area positioned at one side of the first edge area, the second edge area and the effective area are respectively positioned at two opposite sides of the first edge area, and discrete fin parts are formed on the effective area, the first edge area and the second edge area; forming a first graph layer covering the fin part of the effective area and the fin part of the first edge area; etching and removing the fin part with the first thickness in the second edge region by taking the first pattern layer as a mask; removing the first graphic layer; forming a second graphic layer covering the fin part of the effective area; etching and removing the fin part with the second thickness in the first edge area by taking the second pattern layer as a mask, wherein the second thickness is smaller than the first thickness; and removing the second graphic layer.
In the invention, the substrate comprises an effective area, first edge areas positioned at two opposite sides of the effective area and a second edge area positioned at one side of the first edge area, the distance between the second edge area and the effective area is greater than the distance between the effective areas of the first edge area, and discrete fin parts are formed on the effective area, the first edge area and the second edge area; forming a first pattern layer covering the fin part of the effective area and the fin part of the first edge area; etching and removing the fin part with the first thickness in the second edge region by taking the first pattern layer as a mask; and then, forming a second pattern layer covering the fin part in the active area, and etching and removing the fin part with the second thickness in the first edge area by taking the second pattern layer as a mask, wherein the second thickness is smaller than the first thickness. Therefore, in the invention, the amount of the first edge region fin part removed by etching is less than the amount of the second edge region fin part removed by etching, so that in the etching process of removing the second thickness fin part of the first edge region by etching, the etching damage of the etching process to the second pattern layer is less, and the fin part close to the first edge region on the substrate of the effective region is prevented from being exposed, thereby preventing the fin part on the substrate of the effective region from being damaged by etching, enabling the fin part on the substrate of the effective region to have good appearance, and further improving the electrical performance of the formed fin field effect tube.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 1 to 8 are schematic cross-sectional views illustrating a finfet formation process according to an embodiment of the present invention.
Referring to fig. 1, a substrate 101 is provided, where the substrate 101 includes an active area 10, first edge areas 20 located at two opposite sides of the active area 10, and the substrate 101 further includes a second edge area 30 located at one side of the first edge area 20, where the second edge area 30 and the active area 10 are located at two opposite sides of the first edge area 20, and discrete fins 102 are formed on the substrate 101 of the active area 10, the first edge area 20, and the second edge area 30.
The first edge regions 20 are located on two opposite sides of the active region 10 and are adjacent to the active region 10; the active region 10, the first edge region 20 and the second edge region 30 are sequentially arranged in parallel. The fins 102 of the active area 10 are effective fins (effective fins), and the fins 102 of the active area 10 are reserved subsequently; the fin 102 in the first edge region 10 and the second edge region 20 is etched.
In this embodiment, the number of the fins 102 in the active area 10 is 3 as an example, and in other embodiments, the number of the fins in the active area may also be any natural number greater than or equal to 1, for example, 1, 5, or 10. The number of the fins 102 in the first edge region 20 is any natural number greater than or equal to 1, and the number of the second edge regions 30 is any natural number greater than or equal to 1.
The substrate 101 is made of silicon, germanium, silicon carbide, gallium arsenide or indium gallium arsenide, and the substrate 101 can also be a silicon substrate on an insulator or a germanium substrate on an insulator; the material of the fin 102 includes silicon, germanium, silicon carbide, gallium arsenide, or indium gallium arsenide. In this embodiment, the substrate 101 is a silicon substrate, and the fin portion 102 is made of silicon.
In this embodiment, the process steps for forming the substrate 101 and the fin portion 102 include: providing an initial substrate; forming a graphical hard mask layer 103 on the surface of the initial substrate; and etching the initial substrate by taking the hard mask layer 103 as a mask, wherein the etched initial substrate is taken as the substrate 101, and the protrusion on the surface of the substrate 101 is taken as the fin part 102. The fin portions 102 of the active region 10, the first edge region 20 and the second edge region 30 have the same thickness.
In one embodiment, the process steps for forming the hard mask layer 103 include: firstly, forming an initial hard mask; forming a graphical photoresist layer on the surface of the initial hard mask; etching the initial hard mask by taking the patterned photoresist layer as a mask to form a hard mask layer 103 on the surface of the initial substrate; and removing the patterned photoresist layer. In other embodiments, the forming process of the hard mask layer can further include: a Self-aligned Double patterning (SADP) process, a Self-aligned Triple patterning (Self-aligned Triple patterning) process, or a Self-aligned quadruple patterning (Self-aligned Double patterning) process. The double patterning process includes a LELE (Litho-Etch-Litho-Etch) process or a LLE (Litho-Litho-Etch) process.
In this embodiment, after the formation of the fin 102, the hard mask layer 103 on the top surface of the fin 102 is retained. The hard mask layer 103 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the hard mask layer 103 can serve as a stop position of the planarization process to protect the top of the fin portion 102.
In this embodiment, the top dimension of the fin 102 is smaller than the bottom dimension. In other embodiments, the sidewalls of the fin can also be perpendicular to the base surface, i.e., the top dimension of the fin is equal to the bottom dimension.
The thicknesses of the fins 102 of the active area 10, the first edge area 20, and the third edge area 30 are the same, and the widths of the fins 102 of the active area 10, the first edge area 20, and the second edge area 30 are the same in a direction parallel to the surface of the substrate 101.
In the direction parallel to the arrangement direction of the fins 102, the distances between adjacent fins 102 on the substrate 101 are equal, so that the problem of etching load effect in the process of forming the fins 102 by etching is avoided, and the formed fins 102 have good appearance. In one embodiment, the distance between adjacent fins 102 on the substrate 101 is 5 to 100 angstroms in a direction parallel to the arrangement direction of the fins 102.
Referring to fig. 2, a first pattern layer 104 is formed on the fin 102 in the active area 10 and on the fin 102 in the first edge area 20.
The first graphic layer 104 is also located on the substrate 101 of the active area 10 and on the substrate 101 of the first edge area 20.
The first pattern layer 104 protects the fin portion 102 of the active region 10 and the fin portion 102 of the first edge region 20 during a subsequent etching process to remove the fin portion 102 with the first thickness in the second edge region 30. In this embodiment, the first pattern layer 104 is made of a photoresist material. In other embodiments, the first pattern layer may also be a stacked structure of a bottom anti-reflective coating layer and a photoresist layer.
The process steps for forming the first pattern layer 104 include: forming an initial pattern layer covering the fin portions 102 of the active region 10, the fin portions 102 of the first edge region 20 and the fin portions 102 of the second edge region 30; and performing exposure processing and development processing on the initial pattern layer, and removing the initial pattern layer on the fin portion 102 of the second edge region 30 to form the first pattern layer 104.
Referring to fig. 3, the fin 102 of the first thickness in the second edge region 30 is etched away.
Specifically, the fin portion 102 of the second edge region 30 with the first thickness is removed by etching with the first pattern layer 104 as a mask.
The fin portion 102 of the second edge region 30 is a non-effective fin portion, and the fin portion 102 with the first thickness in the second edge region 30 is removed by etching through a dry etching process. In the etching process, since the first pattern layer 104 covers the fin portion 102 of the first edge region 20 in addition to the fin portion 102 of the active region 10, even if the sidewall of the first pattern layer 104 is damaged by etching in the process of removing the fin portion 102 with the first thickness in the second edge region 30 by etching, the exposed fin portion 102 of the first edge region 20 is not exposed, and the fin portion 102 of the active region 10 is not exposed. Therefore, in the process of removing the fin portion 120 of the second edge region 30 by etching, the fin portion 102 of the active region 10 is protected by a strong enough effect, and the fin portion 102 of the active region 10 is effectively prevented from being damaged by etching.
In this embodiment, the process of removing the fin portion 102 with the first thickness in the second edge region 30 by etching includes removing the fin portion 102 with the entire thickness in the second edge region 30 by etching until the substrate 101 of the second edge region 30 is exposed. In order to ensure that the fin portion 102 of the second edge region 30 is completely etched and removed, an over-etching process may be performed on the substrate 101 of the second edge region 30.
It should be further noted that, in other embodiments, the process of removing the fin portion with the first thickness in the second edge region by etching may further be that the fin portion with a partial thickness in the second edge region is removed by etching, and the top of the subsequently formed isolation layer is higher than the top of the remaining fin portion in the second edge region. The top of the subsequently formed isolation layer is at least flush with the top of the remaining fin portion in the first edge region, and the top of the remaining fin portion in the first edge region is higher than the top of the remaining fin portion in the second edge region, so that the top of the subsequently formed isolation layer is higher than the top of the remaining fin portion in the second edge region.
Then, the first graphic layer 104 is removed. The first pattern layer 104 is removed by a wet stripping or ashing process.
Referring to fig. 4, a second pattern layer 105 is formed on the fin 102 and the substrate 101 in the active area 10. The second pattern layer 105 protects the fin portion 102 in the active area 10 during a subsequent etching process of the fin portion 102 in the first edge area 10. And in order to avoid over-etching the substrate 101 of the second edge region 30 by the subsequent etching process, the second pattern layer 105 may also be located on the substrate 101 of the second edge region 30.
In this embodiment, the second pattern layer 105 is made of photoresist; the process steps for forming the second pattern layer 105 include: forming an initial pattern film on the substrate of the active region 10, the first edge region 20 and the second edge region 30, wherein the initial pattern film is also located on the fin portion 102; and performing exposure treatment and development treatment on the initial pattern film, and removing the initial pattern film above the first edge area 20 to form the second pattern layer 105.
Referring to fig. 5, the fin 102 of the first edge region 20 with the second thickness is removed by etching, and the second thickness is smaller than the first thickness.
Specifically, the second pattern layer 105 is used as a mask to etch and remove the fin portion 102 in the first edge region 20 with the second thickness.
And etching to remove the second thickness of the fin portion 102 in the first edge region 20 by using a dry etching process. In this embodiment, the process parameters of the dry etching process include: the etching gas comprises CF4、Si2F6、HCl、HBr、Cl2He, Ar or N2The flow rate of the etching gas is 40sccm to 80sccm,the pressure of the etching reaction chamber is 5 mTorr to 50 mTorr, the etching power is 200 watts to 2000 watts, and the temperature of the etching reaction chamber is 20 ℃ to 80 ℃.
Since the second thickness is smaller than the first thickness, that is, the amount of the fin portion 102 removed in the first edge region 20 is smaller than the amount of the fin portion 102 removed in the second edge region 30, the etching process for etching and removing the fin portion 102 with the second thickness in the first edge region 20 has less etching damage to the second pattern layer 105, so as to prevent the fin portion 102 on the substrate 101 of the active region 10 from being exposed in an etching environment, in particular, prevent the fin portion 102 on the substrate 101 of the active region 10 close to the first edge region 20 from being exposed in an etching environment, and ensure that the fin portion 102 on the substrate 101 of the active region 10 keeps a good shape.
The second thickness is related to the thickness of the fin 102 in the first edge region 10 before etching and the thickness of the subsequently formed isolation layer, and the top of the subsequently formed isolation layer is flush with the top of the remaining fin 102 in the first edge region 20 or higher than the top of the remaining fin 102 in the first edge region 20.
The first thickness should not be too thin, otherwise, after the subsequent formation of the isolation layer, the top and sidewalls of the remaining fin 102 in the first edge region 20 are exposed; the second thickness is not too thick, otherwise, the etching time required for etching and removing the fin portion 102 with the second thickness is long, and the sidewall of the second pattern layer 105 is seriously damaged by etching, which is likely to cause the sidewall of the fin portion 102, which is close to the first edge region 20 on the substrate 101 of the active region 10, to be exposed to the etching environment. Therefore, in the present embodiment, after the first thickness of the fin 102 in the first edge region 20 is removed by etching, the thickness of the remaining fin 102 in the first edge region 20 is 1/5 to 2/3 of the thickness of the fin 102 in the first edge region 20 before etching.
In this embodiment, the etching rate for removing the fin portion 102 with the first thickness in the second edge region 30 by etching is a first etching rate; the etching rate of the fin portion 102 with the second thickness in the first edge region 20 is a second etching rate, and the second etching rate is equal to the first etching rate. Correspondingly, the etching time for etching and removing the fin portion 102 with the first thickness in the second edge region 30 is a first time; the etching time for removing the second thickness of the first edge region 20 by etching is a second time, and the second time is less than the first time.
In other embodiments, the first etching rate may be less than or greater than the second etching rate, and correspondingly, the second duration may be greater than or equal to the first duration.
Referring to fig. 6, the second graphic layer 105 (refer to fig. 5) is removed.
In this embodiment, the second pattern layer 105 is made of a photoresist, and the second pattern layer 105 is removed by a wet stripping or ashing process.
It should be noted that, in this embodiment, the fin portion 102 of the second edge region 30 with the first thickness is removed by etching, and then the fin portion 102 of the first edge region 20 with the second thickness is removed by etching. In other embodiments, the fin portion of the first edge region with the second thickness may be removed by etching first, and then the fin portion of the second edge region with the first thickness may be removed by etching.
The method also comprises the following steps: isolation layers are formed on the sidewalls of the fins 102 in the active area 10 and on the sidewalls of the remaining fins 102 in the first edge area 20 on the substrate 101, and the tops of the isolation layers are lower than the tops of the fins 102 in the active area 10. The process steps for forming the isolation layer will be described in detail below with reference to the accompanying drawings.
Referring to fig. 7, an isolation film 106 is formed on the substrate 101, wherein the isolation film 106 is also located on the sidewalls and on the top of the fin 102; the top surface of the isolation film 106 is planarized.
In this embodiment, the isolation film 106 is further located on the sidewall of the hard mask layer 103, and after the planarization process is performed on the top surface of the isolation film 106, the top of the isolation film 106 is flush with the top of the hard mask layer 103.
The isolation film 106 provides a process foundation for the subsequent formation of an isolation layer; the material of the isolation film 106 is an insulating material, such as silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation film 106 is made of silicon oxide.
In order to improve the gap-filling capability of the process of forming the isolation film 106, the isolation film 106 is formed by using a Flowable Chemical Vapor Deposition (FCVD) or a high aspect ratio chemical vapor deposition (HARP CVD). In one embodiment, the process of forming the isolation film 106 includes: forming a precursor isolation film by adopting a flowable chemical vapor deposition process; and carrying out annealing and curing treatment on the precursor isolation film to convert the precursor isolation film into the isolation film 106.
In this embodiment, a chemical mechanical polishing process is used to polish and remove the isolation film 106 higher than the top of the hard mask layer 103 until the top of the remaining isolation film 106 is flush with the top of the hard mask layer 103.
It should be noted that, in order to improve the interfacial performance between the fin 102 and the isolation film 106, a liner oxide layer (liner oxide layer) may be further formed on the sidewall of the fin 102 before the isolation film is formed.
Referring to fig. 8, the isolation film 106 (see fig. 7) is etched back to remove a portion of the thickness, and an isolation layer 116 is formed on the sidewalls of the fins 102 in the active area 10 and the sidewalls of the remaining fins 102 in the first edge area 20 on the substrate 101, where the top of the isolation layer 116 is lower than the top of the fins 102 in the active area 10.
The isolation layer 116 serves as an isolation structure of the finfet and serves to electrically isolate adjacent fins 102.
And etching to remove part of the thickness of the isolation film 106 by adopting a dry etching process, a wet etching process or a process combining the dry etching process and the wet etching process. In this embodiment, the isolation film 106 with a part of the thickness is removed by etching using a wet etching process, and the etching liquid used in the wet etching process is a hydrofluoric acid solution.
In this embodiment, the top of the isolation layer 116 is higher than the top of the remaining fins 102 in the first edge region 20. In other embodiments, the top of the isolation layer may be flush with the top of the remaining fins in the first edge region.
In addition, it should be noted that, in other embodiments, the process of removing the fin portion with the first thickness in the second edge region by etching is that, when the fin portion with the partial thickness in the second edge region is removed by etching, the formed isolation layer is also located on the top and the sidewall of the remaining fin portion in the second edge region.
In the process of forming the isolation layer 116, the hard mask layer 103 (refer to fig. 3) is also removed; in this embodiment, the hard mask layer 103 is made of silicon nitride, and the etching liquid used for removing the hard mask layer 103 by etching is phosphoric acid solution.
In one embodiment, the hard mask layer 103 is removed before etching back to remove a portion of the thickness of the isolation layer 106; in another embodiment, the hard mask layer 103 may be removed after etching back to remove a portion of the thickness of the isolation layer 106.
The subsequent process steps further comprise: forming a gate structure crossing the fin portion 102 of the active region 10, wherein the gate structure covers part of the top and the side wall of the fin portion 102 of the active region 10; and doping the fin parts 102 on the two sides of the grid structure to form a source-drain doped region.
Because the distance between the first edge region and the effective region is smaller than the distance between the second edge region and the effective region, under the condition that the etching process parameters are the same, the influence of etching and removing the fin part of the first edge region on the fin part of the effective region is larger than the influence of etching and removing the fin part of the second edge region on the fin part of the effective region.
In the finfet formed in this embodiment, the amount of the fin 102 removed in the first edge region 20 is different from the amount of the fin 102 removed in the second edge region 30. Specifically, compared with the first thickness of the fin portion 102 of the second edge region 30, the second thickness of the fin portion 102 of the first edge region 20 adjacent to the active region 10, which is removed by etching, is smaller, so that in the process of removing the fin portion 102 of the first edge region 20 by etching, the etching damage to the second pattern layer 105 (refer to fig. 5) on the active region 10 adjacent to the first edge region 20 is smaller, and accordingly, the adverse effect on the fin portion 102 of the active region 10 adjacent to the first edge region 20 is reduced, thereby preventing the fin portion 102 of the active region 10 from being damaged by etching, ensuring that the fin portion 102 of the active region 10 has a good appearance, and improving the electrical performance of the formed fin field effect transistor.
In a specific embodiment, under the condition that the parameters of the etching rate for etching and removing the fin portions 102 in the first edge region 20 and the etching rate for etching and removing the fin portions 102 in the second edge region 30 are the same, the etching duration required for etching and removing the fin portions 102 in the second thickness in the first edge region 20 is a second duration, the duration required for etching and removing the fin portions 102 in the first thickness in the second edge region 30 is a first duration, and the second duration is significantly shorter than the first duration; therefore, the etching time for removing the fin portion 102 in the first edge region 20 by etching is short, so that the sidewall of the second pattern layer 105 (refer to fig. 5) is prevented from being damaged, the sidewall of the fin portion 102 in the active region 10 is prevented from being exposed, the problem of damage to the fin portion 102 in the active region 10 caused by removing the fin portion 102 in the first edge region 20 by etching is reduced or even avoided, and the fin portion 102 on the substrate 101 in the active region 10 has good morphology.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (20)

1. A method for forming a fin field effect transistor (FinFET) is characterized by comprising the following steps:
providing a substrate, wherein the substrate comprises an effective area, first edge areas positioned at two opposite sides of the effective area, and a second edge area positioned at one side of the first edge area, the second edge area and the effective area are respectively positioned at two opposite sides of the first edge area, and discrete fin parts are formed on the effective area, the first edge area and the second edge area;
forming a first graph layer on the fin part of the effective area and the substrate as well as the fin part of the first edge area and the substrate;
etching and removing the fin part with the first thickness in the second edge region by taking the first pattern layer as a mask;
removing the first graphic layer;
forming a second graphic layer on the fin part of the effective area and the substrate;
etching and removing the fin part with the second thickness in the first edge area by taking the second pattern layer as a mask, wherein the second thickness is smaller than the first thickness;
and removing the second graphic layer.
2. The method of claim 1, further comprising, after the etching to remove the first thickness fin in the second edge region and the etching to remove the second thickness fin in the first edge region, the steps of: and forming isolation layers on the side walls of the fins in the effective area and the side walls of the remaining fins in the first edge area on the substrate, wherein the top of each isolation layer is lower than that of the fin in the effective area.
3. The method of claim 2, wherein the isolation layer is further located on sidewalls of remaining fins in the first edge region, and a top of the isolation layer is higher than or flush with a top of the remaining fins in the first edge region.
4. The method of claim 1, wherein after etching away the second thickness fin in the first edge region, a remaining fin thickness in the first edge region is 1/5-2/3 of a fin thickness in the first edge region before etching.
5. The method of claim 1, wherein the second thickness fin is etched away from the first edge region using a dry etching process.
6. The method of claim 5, wherein the process parameters of the dry etching process comprise: the etching gas comprises CF4、Si2F6、HCl、HBr、Cl2He, Ar or N2The flow rate of the etching gas is 40sccm to 80sccm, the pressure of the etching reaction chamber is 5 mTorr to 50 mTorr, the etching power is 200 watts to 2000 watts, and the temperature of the etching reaction chamber is 20 ℃ to 80 ℃.
7. The method of claim 1, wherein an etching rate for etching away the fin portion with the first thickness in the second edge region is a first etching rate; and the etching rate of the fin part with the second thickness in the first edge area is removed by etching is a second etching rate, and the second etching rate is equal to the first etching rate.
8. The method of claim 7, wherein a duration of etching to remove the fin portion of the first thickness in the second edge region is a first duration; and the etching time for etching and removing the fin part with the second thickness in the first edge area is a second time, and the second time is less than the first time.
9. The method of claim 1, wherein etching the fin of the first thickness in the second edge region comprises etching the fin of the entire thickness in the second edge region until the substrate in the second edge region is exposed.
10. The method of claim 1, wherein the etching to remove the fin portion with the first thickness in the second edge region comprises etching to remove the fin portion with a partial thickness in the second edge region; after the fin part with the first thickness in the second edge region is removed by etching and the fin part with the second thickness in the first edge region is removed by etching, the method further comprises the following steps: and forming isolation layers on the side walls of the fin parts in the effective region, the side walls of the remaining fin parts in the first edge region and the side walls of the remaining fin parts in the second edge region on the substrate, wherein the top of the formed isolation layer is higher than that of the remaining fin parts in the second edge region.
11. The method of claim 1, wherein a distance between adjacent fins on the substrate is equal in a direction parallel to an arrangement of fins.
12. The method of claim 11, wherein a distance between adjacent fins on the substrate in a direction parallel to the fin alignment direction is between 5 angstroms and 100 angstroms.
13. The method of claim 1, wherein the first etching removes the first thickness fin in the second edge region, and the second etching removes the second thickness fin in the first edge region.
14. The method of claim 1, wherein the second thickness of the fin in the first edge region is etched away first, and then the first thickness of the fin in the second edge region is etched away.
15. The method of claim 1, wherein the second pattern layer is further located on a second edge region substrate.
16. The method of claim 15, wherein the second pattern layer is made of a photoresist; the process for forming the second pattern layer comprises the following steps: forming an initial pattern film on the substrate of the effective area, the first edge area and the second edge area, wherein the initial pattern film is also positioned on the fin part; and removing the initial pattern film above the first edge area to form the second pattern layer.
17. The method of claim 1, wherein the number of active region fins is greater than or equal to 1.
18. The method of claim 2 or 10, wherein a hard mask layer is further formed on a top portion of the fin before the isolation layer is formed; and in the process of forming the isolation layer, the hard mask layer is also removed.
19. The method of claim 18, wherein the process step of forming the isolation layer comprises: forming an isolation film on the substrate, wherein the isolation film is positioned on the side wall and the top of the fin part; carrying out planarization treatment on the top surface of the isolation film; and etching back to remove part of the thickness of the isolation film to form the isolation layer.
20. The method of forming a fin field effect transistor of claim 1, further comprising: forming a grid electrode structure crossing the fin part of the effective region, wherein the grid electrode structure covers the top and the side wall of the fin part of the effective region; and doping the fin parts on the two sides of the grid structure to form a source drain doped region.
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