CN112151360B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112151360B CN112151360B CN201910577088.6A CN201910577088A CN112151360B CN 112151360 B CN112151360 B CN 112151360B CN 201910577088 A CN201910577088 A CN 201910577088A CN 112151360 B CN112151360 B CN 112151360B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 246
- 238000000034 method Methods 0.000 title claims abstract description 119
- 239000000758 substrate Substances 0.000 claims abstract description 88
- 238000002955 isolation Methods 0.000 claims abstract description 63
- 238000005530 etching Methods 0.000 claims abstract description 54
- 239000000463 material Substances 0.000 claims description 172
- 230000008569 process Effects 0.000 claims description 82
- 238000011049 filling Methods 0.000 claims description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 23
- 229910052710 silicon Inorganic materials 0.000 claims description 23
- 239000010703 silicon Substances 0.000 claims description 23
- 238000001312 dry etching Methods 0.000 claims description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 9
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 9
- 229910052796 boron Inorganic materials 0.000 claims description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 8
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- 229910052582 BN Inorganic materials 0.000 claims description 7
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 7
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 6
- 239000003610 charcoal Substances 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 230000000873 masking effect Effects 0.000 claims description 4
- 230000009286 beneficial effect Effects 0.000 description 10
- 238000001039 wet etching Methods 0.000 description 10
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 230000002349 favourable effect Effects 0.000 description 3
- 230000009969 flowable effect Effects 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- 238000005452 bending Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 1
- 229910018557 Si O Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Inorganic materials [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: forming a substrate, an initial semiconductor column positioned on the substrate, a first mask layer positioned on the initial semiconductor column and a second mask layer positioned on the first mask layer; etching the initial semiconductor column by taking the first mask layer and the second mask layer as masks to form a cross semiconductor column; after the semiconductor pillars are formed, an isolation layer is formed on the substrate where the semiconductor pillars are exposed. Compared with the situation that the semiconductor column is cylindrical, the height of the semiconductor column is smaller than the height and width of the semiconductor column in any crossing direction, so that the crossing semiconductor column is not easy to bend or incline when being stressed in the isolation layer, and the electrical property of the semiconductor structure is improved.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
The reduction of the transistor channel length has the benefits of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is shortened, the control capability of the gate to the channel is reduced, so that the subthreshold leakage (subthreshold leakage) phenomenon, that is, short-channel effects (SCE) is more likely to occur, and the channel leakage current of the transistor is increased.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect. The fully-surrounding Gate transistors include a Lateral Gate-all-around (lga) transistor and a Vertical Gate-all-around (VGAA) transistor, wherein the channel of VGAA extends in a direction perpendicular to the substrate surface, which is advantageous for improving the area utilization efficiency of the semiconductor structure, and thus for achieving further feature size reduction.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the electrical performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a first mask material layer in a strip shape on the substrate; etching the substrate by taking the first mask material layer as a mask to form a substrate and a semiconductor film positioned on the substrate; after the semiconductor film is formed, thinning the two sides of the first mask material layer along the vertical extending direction to form a first initial mask layer; forming a second mask material layer which is crossed with the first initial mask layer and takes the shape of a long strip on the first initial mask layer; etching the first initial mask layer and the semiconductor film by taking the second mask material layer as a mask to form an initial semiconductor column and a first mask layer positioned on the initial semiconductor column; after the first mask layer is formed, thinning the two sides of the second mask material layer perpendicular to the extending direction to form a second mask layer; etching the initial semiconductor column by taking the first mask layer and the second mask layer as masks to form a cross semiconductor column; after the semiconductor column is formed, an isolation layer is formed on the substrate exposed by the semiconductor column, and the isolation layer covers part of the side wall of the semiconductor column.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a semiconductor pillar located on the substrate; the semiconductor column comprises a first column body and a second column body, wherein the projection of the first column body in the substrate is in a strip shape, the projection of the second column body in the substrate is in a strip shape, the first column body and the second column body are intersected in a horizontal plane, and the top surface of the first column body is flush with the top surface of the second column body; and the isolation layer is positioned on the substrate exposed by the semiconductor column and covers part of the side wall of the semiconductor column.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the first mask material layer is in a strip shape, the correspondingly formed first initial mask layer is also in a strip shape, the second mask material layer is intersected with the first initial mask layer, the second mask material layer is used as a mask for etching the first initial mask layer to form the first mask layer, the second mask material layer is thinned to form the second mask layer, the first mask layer is intersected with the second mask layer, and the first mask layer and the second mask layer are used as masks for etching the initial semiconductor column to form the intersected semiconductor column. Compared with the situation that the semiconductor column is cylindrical, the height of the semiconductor column is smaller than the height and width of the semiconductor column in any crossing direction, so that the crossing type semiconductor column is not easy to bend or incline when being stressed in the isolation layer, and the electrical property of the semiconductor structure is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 16 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to an embodiment of the present invention;
fig. 17 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
As can be seen from the background art, the devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.
A schematic structural diagram of a semiconductor structure is shown with reference to fig. 1.
As shown in fig. 1, a substrate is provided; the base comprises a substrate 1 and a semiconductor column 2 positioned on the substrate 1, wherein the semiconductor column 2 is used as a channel region; an isolation layer 3 is formed on the substrate 1 where the semiconductor pillars 2 are exposed.
After the formation of the isolation layer 3, the isolation layer 3 is annealed. The annealing treatment breaks the Si-H bond and the Si-O bond in the isolation layer 3, so that the isolation layer 3 becomes denser, the volume of the isolation layer 3 changes, and correspondingly, larger stress exists in the isolation layer 3, because the semiconductor column 2 is in a columnar structure, and the semiconductor column 2 is thin and high, namely, the height and the width of the semiconductor column 2 are larger, the semiconductor column 2 is easy to bend or incline under the stress of the isolation layer 3, and the like, so that the electrical performance of the semiconductor structure is poor.
In order to solve the technical problems, the embodiment of the invention provides a substrate; forming a first mask material layer in a strip shape on the substrate; etching the substrate by taking the first mask material layer as a mask to form a substrate and a semiconductor film positioned on the substrate; after the semiconductor film is formed, thinning the two sides of the first mask material layer along the vertical extending direction to form a first initial mask layer; forming a second mask material layer which is crossed with the first initial mask layer and takes the shape of a long strip on the first initial mask layer; etching the first initial mask layer and the semiconductor film by taking the second mask material layer as a mask to form an initial semiconductor column and a first mask layer positioned on the initial semiconductor column; after the first mask layer is formed, thinning the two sides of the second mask material layer perpendicular to the extending direction to form a second mask layer; etching the initial semiconductor column by taking the first mask layer and the second mask layer as masks to form a cross semiconductor column; after the semiconductor column is formed, an isolation layer is formed on the substrate exposed by the semiconductor column, and the isolation layer covers part of the side wall of the semiconductor column.
According to the embodiment of the invention, the first mask material layer is in a strip shape, the correspondingly formed first initial mask layer is also in a strip shape, the second mask material layer is intersected with the first initial mask layer, the second mask material layer is used as a mask for etching the first initial mask layer to form the first mask layer, the second mask material layer is thinned to form the second mask layer, the first mask layer is intersected with the second mask layer, and the first mask layer and the second mask layer are used as masks for etching the initial semiconductor column to form the intersected semiconductor column. Compared with the situation that the semiconductor column is cylindrical, the height of the semiconductor column is smaller than the height and width of the semiconductor column in any crossing direction, so that the crossing type semiconductor column is not easy to bend or incline when being stressed in the isolation layer, and the electrical property of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 2 to 16 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate 100 is provided.
The substrate 100 provides a process basis for the subsequent formation of semiconductor structures.
In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and may be made of other types of substrates such as silicon-on-insulator substrates or germanium-on-insulator substrates. The material of the substrate 100 may be a material suitable for process requirements or easy integration.
Referring to fig. 3 in conjunction with fig. 2, fig. 3 is a view of fig. 2 along the AA direction, and a first mask material layer 102 (shown in fig. 3) is formed on the substrate 100 in a stripe shape.
The first mask material layer 102 serves as an etching mask for subsequently etching the base 100 to form a substrate and a semiconductor film on the substrate.
In this embodiment, the first mask material layer 102 includes a first initial mask layer 104 and an auxiliary sidewall layer 103 (shown in fig. 3) located on a sidewall of the first initial mask layer 104 (shown in fig. 2).
Specifically, the materials of the first initial mask layer 104 include: one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, amorphous carbon, amorphous germanium, and boron carbonitride. In this embodiment, the material of the first initial mask layer 104 includes silicon nitride.
Specifically, the materials of the auxiliary sidewall layer 103 include: and (3) silicon oxide. In this embodiment, the material of the auxiliary sidewall layer 103 includes silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is favorable for reducing the process difficulty and process cost of forming the auxiliary side wall layer 103, and has less damage to the first initial mask layer 104 in the process of removing the auxiliary side wall layer 103 later.
Specifically, the step of forming the first mask material layer 102 is as follows:
as shown in fig. 2, the first initial mask layer 104 is formed on the substrate 100.
As shown in fig. 3, the first initial masking material layer 104 and the auxiliary sidewall material layer (not shown) are conformally covered on the substrate 100 exposed by the first initial masking material layer 104; and removing the auxiliary side wall material layers on the substrate 100 and the first initial mask layer 104, wherein the auxiliary side wall material layers remained on the side wall of the first initial mask material layer 104 are used as auxiliary side wall layers 103, and the first initial mask layer 104 and the auxiliary side wall layers 103 are used as first mask material layers 102.
In this embodiment, an atomic layer deposition process (Atomic layer deposition, ALD) is used to form the auxiliary sidewall material layer. The atomic layer deposition process comprises multiple atomic layer deposition cycles to form an auxiliary side wall material layer with a required thickness, and the thickness uniformity of the auxiliary side wall material layer is improved by selecting the atomic layer deposition process, so that the thickness of the auxiliary side wall layer can be accurately controlled, and in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the auxiliary side wall material layer is correspondingly improved. In other embodiments, the auxiliary sidewall material layer may also be formed by a chemical vapor deposition process (Chemical Vapor Deposition, CVD).
In other embodiments, the step of forming the first mask material layer includes: forming a first mask material film on the substrate; and patterning the first mask material film to form the first mask material layer in a strip shape.
Referring to fig. 4, fig. 4 is a view based on the direction of fig. 3, and the substrate 100 is etched using the first mask material layer 102 as a mask, to form a substrate 105 and a semiconductor film 106 on the substrate 105.
The semiconductor film 106 provides for the subsequent formation of semiconductor pillars.
In this embodiment, the substrate 100 is etched by a dry etching process to form a substrate 105 and a semiconductor film 106 on the substrate 105. The dry etching process is an anisotropic etching process, has good etching profile control, enables the morphology of the semiconductor film 106 to meet the process requirements, and is beneficial to reducing damage to other film structures. And the substrate 100 is etched by a dry etching process, which is advantageous in precisely controlling the height of the semiconductor film 106.
Referring to fig. 5, fig. 5 is a view based on the direction of fig. 4, after the semiconductor film 106 is formed, thinning treatment is performed on both sides of the first mask material layer 102 along the vertical extension direction, so as to form a first initial mask layer 104.
In this embodiment, the thinning process is performed on the first mask material layer 102 to form the first initial mask layer 104, which means that the auxiliary sidewall layer 103 on the sidewall of the first initial mask layer 104 is removed. And forming a second mask material layer on the first initial mask layer 104, and removing the auxiliary side wall layer 103 to prepare for etching the first initial mask layer 104 to form a first mask layer by taking the second mask material layer as a mask.
The step of forming the first initial mask layer 104 includes: and removing the auxiliary side wall layer 103.
In this embodiment, a wet etching process is used to remove the auxiliary sidewall layer 103. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost. In the wet etching process, the etched rate of the auxiliary sidewall 103 is greater than the etched rate of the first initial mask layer 104.
Specifically, the wet etching solution is an HF solution. The HF solution is a common solution used in the semiconductor field for etching silicon oxide.
In other embodiments, the first mask material layer is an integral film structure, and the step of forming the first initial mask layer includes: forming a first hard mask layer on the first mask material layer, wherein the extending direction of the first hard mask layer is the same as that of the first mask material layer; the size of the first hard mask layer is smaller than that of the first mask material layer along the extending direction perpendicular to the first mask material layer, and the first mask material layer is exposed from two sides of the first hard mask layer; and etching the first mask material layer by taking the first hard mask layer as a mask to form the first initial mask layer.
In other embodiments, the first mask material layer is etched by a dry etching process, so as to form the first initial mask layer. The dry etching process is an anisotropic etching process, has good etching profile control, and is beneficial to improving the removal efficiency of the first mask material layer, so that the appearance of the first initial mask layer meets the process requirement.
It should be noted that, in other embodiments, the method for forming the semiconductor structure includes: and removing the first hard mask layer after the first initial mask layer is formed.
Referring to fig. 6 to 9, wherein fig. 8 is a view of fig. 7 in the BB direction, and fig. 9 is a view of fig. 7 in the CC direction. A second mask material layer 107 in an elongated shape intersecting the first initial mask layer 104 is formed on the first initial mask layer 104.
In the present invention, the second mask material layer 107 is intersected with the first initial mask layer 104, the second mask material layer 107 is used as a mask to etch the first initial mask layer 104 to form a first mask layer, the second mask material layer 107 is thinned to form a second mask layer, the first mask layer is intersected with the second mask layer, and the first mask layer and the second mask layer are used as masks to etch the initial semiconductor column to form a intersected semiconductor column. Compared with the situation that the semiconductor column is cylindrical, the height of the semiconductor column is smaller than the height and width of the semiconductor column in any crossing direction, so that the crossing type semiconductor column is not easy to bend or incline when being stressed in the isolation layer, and the electrical property of the semiconductor structure is improved.
The second mask material layer 107 is used as an etching mask for subsequently etching the first initial mask layer 104 to form a first mask layer.
Specifically, the extending direction of the second mask material layer 107 is perpendicular to the extending direction of the first initial mask layer 104, so that the first mask layer and the second mask layer formed subsequently are perpendicular to each other, and the intersecting directions of the semiconductor pillars formed subsequently are perpendicular to each other.
And forming an isolation layer covering part of the thickness of the semiconductor column, wherein the isolation layer is subjected to annealing treatment, so that the isolation layer has stress. The cross directions of the semiconductor columns are mutually perpendicular, so that the two extending directions of the semiconductor columns are circumferentially arranged at equal angles with the cross point of the semiconductor columns as the center, the semiconductor columns are stressed more uniformly when stressed in the isolating layer, the semiconductor columns are not easy to bend or incline, and the like, and the electrical property of the semiconductor structure is improved.
The step of forming the second mask material layer 107 includes: forming the second mask layer 108 on the first initial mask layer 104, wherein the second mask layer 108 covers a part of the top surface of the first initial mask layer 104; an auxiliary sidewall layer 103 is formed on the sidewall of the second mask layer 108, and the second mask layer 108 and the auxiliary sidewall layer 103 serve as a second mask material layer 107.
In this embodiment, the material of the second mask layer 108 is the same as that of the first initial mask layer 104, so that the forming process can be completed on the same machine, and the complexity of the process can be reduced.
And the material of the second mask layer 108 is different from the material of the auxiliary sidewall layer 103, so that the etching rate of the second mask layer 108 is smaller than the etching rate of the auxiliary sidewall layer 103 in the subsequent process of removing the auxiliary sidewall layer 103.
Specifically, the materials of the second mask layer 108 include: one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, amorphous carbon, amorphous germanium, and boron carbonitride. In this embodiment, the material of the first initial mask layer 104 includes silicon nitride, so the material of the second mask layer 108 includes: silicon nitride.
The auxiliary sidewall layer 103 comprises the following materials: and (3) silicon oxide. In this embodiment, the material of the auxiliary sidewall layer 103 includes silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is favorable for reducing the process difficulty and process cost of forming the auxiliary side wall layer 103, and has less damage to the first initial mask layer 104 in the process of removing the auxiliary side wall layer 103 later.
In other embodiments, the step of forming the second mask material layer may further include: forming a second mask material film on the first initial mask layer; and patterning the second mask material film to form a strip-shaped second mask material layer.
It should be noted that, during the process of etching the first initial mask layer 104 to form the first mask layer, the second mask layer 108 is partially consumed, so that the second mask layer 108 has a sufficient thickness and the first mask layer is used as a mask for forming the semiconductor pillars in the subsequent etching, and the second mask layer 108 is not too thick or too thin. If the second mask layer 108 is too thick, the process time for forming the second mask layer 108 is too long, resulting in waste of process materials and correspondingly, difficult control of process defects. If the second mask layer 108 is too thin, it is easy to be removed too early in the subsequent process of forming the semiconductor pillars, which is not beneficial to the formation of the semiconductor pillars. In this embodiment, the thickness of the second mask layer 108 is 2 to 3 times that of the first initial mask layer 104.
It should be noted that, the method for forming the semiconductor structure further includes: after forming the first initial mask layer 104, before forming the second mask material layer 107, further includes: a filling layer 110 is formed on the substrate 100 exposed by the first initial mask layer 104, the filling layer 110 covers the sidewall of the first initial mask layer 104 and exposes the top surface of the first initial mask layer 104.
The filling layer 110 provides support for the subsequent formation of the second mask material layer 107, and the filling layer 110 protects the semiconductor film 106 during the subsequent etching of the first initial mask layer 104 with the second mask material layer 107 as a mask, forming the first mask layer.
In this embodiment, the material of the filling layer 110 is an organic material. For example: one or more of BARC (bottom anti-reflective coating) material, ODL (organic dielectric layer ) material, photoresist, DARC (dielectric anti-reflective coating) material, DUO (Deep UV Light Absorbing Oxide, deep ultraviolet light absorbing oxide) material, and APF (Advanced Patterning Film, advanced patterning) material.
In other embodiments, the filling layer may be made of other materials that can function as a mask and are easy to remove, so that damage to the initial semiconductor pillar formed later is reduced when the filling layer is removed later.
Specifically, the step of forming the filling layer 110 includes: forming a filling material layer (not shown) covering the semiconductor film 106 and the first initial mask layer 104; a planarization process is used to remove the filling material layer above the first initial mask layer 104, and the remaining filling material layer serves as a filling layer 110.
In this embodiment, the filling material layer is formed by a spin coating process, and the formed filling material layer has high flatness.
Referring to fig. 10 and 11, the first initial mask layer 104 (shown in fig. 9) and the semiconductor film 106 (shown in fig. 9) are etched using the second mask material layer 107 as a mask, forming initial semiconductor pillars 109 (shown in fig. 11) and a first mask layer 111 (shown in fig. 11) on the initial semiconductor pillars 109.
The first mask layer 111 serves as an etching mask for one direction of subsequently formed cross-shaped semiconductor pillars, and the initial semiconductor pillars 109 serve as subsequently formed cross-shaped semiconductor pillars.
In this embodiment, the first initial mask layer 104 (as shown in fig. 9) and the semiconductor film 106 (as shown in fig. 9) are etched by a dry etching process, so as to form an initial semiconductor pillar 109 and a first mask layer 111 on the initial semiconductor pillar 109. The dry etching process is an anisotropic etching process, has good etching profile controllability, is easy to reduce damage to other film structures, is favorable for enabling the shapes of the initial semiconductor column 109 and the first mask layer 111 to meet the process requirements, and can etch the first initial mask layer 104 and the semiconductor film 106 in the same etching equipment by changing etching gas, thereby simplifying the process steps.
Specifically, the process parameters of the dry etching process include: the etching gas includes: CF (compact flash) 4 And SF (sulfur hexafluoride) 6 。
In the process of etching the first initial mask layer 104 and the semiconductor film 106 by using the dry etching process to form the initial semiconductor pillars 109 and the first mask layer 111 on the initial semiconductor pillars 109, the filling layer 110 exposing the second mask material layer 107 is also etched and removed, and the filling layer 110 covered by the second mask material layer 107 is retained.
The filling layer 110 covered by the second mask material layer 107 plays a role in protecting the sidewalls of the initial semiconductor pillars 109 during the subsequent etching of the second mask material layer to form the second mask layer and during the etching of the initial semiconductor pillars 109 to form the semiconductor pillars.
The extending direction of the first mask layer 111 is set as a first direction, and a direction perpendicular to the first direction is set as a second direction, and a ratio of the first direction to the second direction is not easily too large or too small. If the ratio is too large, the first mask layer 111 is too thin, which is easy to cause the first mask layer 111 to be bent or inclined when being subjected to stress in a subsequently formed isolation layer; if the ratio is too small, the aspect ratio of the subsequently formed cross-shaped semiconductor pillars along the extending direction of the first mask layer 111 is too large, so that the cross-shaped semiconductor pillars are easy to bend or incline when being stressed in the isolation layer, and the electrical performance of the semiconductor structure is not easy to be improved. In this embodiment, the ratio of the first direction to the second direction in the first mask layer 111 is 2 to 4.
Referring to fig. 12 and 13, after the first mask layer 111 is formed, thinning processing is performed on two sides of the second mask material layer 107 perpendicular to the extending direction, so as to form a second mask layer 108.
In this embodiment, the thinning process is performed on the second mask material layer 107, so that the second initial mask layer 108 is formed, which means that the auxiliary sidewall layer 103 on the sidewall of the second mask layer 108 is removed.
The step of forming the second mask layer 108 includes: and removing the auxiliary side wall layer 103.
In the process of removing the auxiliary sidewall layer 103 on the sidewall of the second mask layer 108, the etched rate of the second mask layer 108 is smaller than the etched rate of the auxiliary sidewall layer 103.
In this embodiment, a wet etching process is used to remove the auxiliary sidewall layer 103. The wet etching process is isotropic etching, has higher etching rate, and is simple to operate and low in process cost. In the wet etching process, the etched rate of the auxiliary sidewall 103 is greater than the etched rate of the second mask layer 108.
Specifically, the wet etching solution is an HF solution. The HF solution is a common solution used in the semiconductor field for etching silicon oxide.
The extending direction of the second mask layer 108 in the horizontal plane is taken as a first direction, and the horizontal plane is perpendicular to the first direction as a second direction, and the ratio of the first direction to the second direction is not easy to be too large or too small. If the ratio is too large, the portion of the semiconductor column etched by using the second mask layer 108 as a mask is too thin, and bending or tilting is easily generated when stress in the isolation layer is received; if the ratio is too small, the aspect ratio of the subsequently formed cross-shaped semiconductor pillars along the extending direction of the second mask layer 108 is too large, so that the cross-shaped semiconductor pillars are easy to bend or incline when being stressed in the isolation layer, and the electrical performance of the semiconductor structure is not easy to be improved. In this embodiment, the ratio of the first direction to the second direction in the second mask layer 108 is 2 to 4.
In other embodiments, the second mask material layer is an integral film structure, and the step of forming the second mask layer includes: forming a second hard mask layer on the second mask material layer, wherein the extending direction of the second hard mask layer is the same as that of the second mask material layer; the size of the second hard mask layer is smaller than that of the second mask material layer along the extending direction perpendicular to the second mask material layer, and the second mask material layer is exposed from two sides of the second hard mask layer; and etching the second mask material layer by taking the second hard mask layer as a mask to form the first initial mask layer.
And etching the second mask material layer by adopting a dry etching process to form the second mask layer. The dry etching process is an anisotropic etching process, has good etching profile control, and is beneficial to improving the removal efficiency of the second mask material layer, so that the appearance of the second mask layer meets the process requirement.
It should be noted that, in other embodiments, the method for forming the semiconductor structure includes: and removing the second hard mask layer after the second mask layer is formed.
Referring to fig. 14, the first mask layer 111 and the second mask layer 108 are used as masks to etch the initial semiconductor pillars 109, so as to form cross-type semiconductor pillars 112.
Because the extending direction of the first mask layer 111 is perpendicular to the extending direction of the second mask layer 108, two intersecting directions of the intersecting semiconductor pillars 112 are formed perpendicular to each other.
In this embodiment, the first mask layer 111 and the second mask layer 108 are used as masks to etch the initial semiconductor pillars 109 by using a dry etching process, so as to form the cross-shaped semiconductor pillars 112. The dry etching process is an anisotropic etching process, has good etching profile control, enables the morphology of the semiconductor column 112 to meet the process requirements, and is beneficial to reducing damage to other film structures.
In the process of etching the initial semiconductor pillars 109 to form the semiconductor pillars 112, the filling layer 110 exposing the first mask layer 111 and the second mask layer 108 is removed, and the filling layer 110 covered by the first mask layer 111 and the second mask layer 108 (as shown in fig. 8) is left.
Therefore, the method for forming the semiconductor structure further comprises the following steps: after the semiconductor pillars 112 are formed, the remaining filler layer 110 is removed.
In this embodiment, an ashing process is used to remove the remaining filling layer 110.
The method for forming the semiconductor structure further comprises the following steps: after the semiconductor pillars 112 are formed, source-drain doped regions (not shown) are formed in the substrate 105 under the semiconductor pillars 112.
The source-drain doped region is used as a source electrode or a drain electrode of the semiconductor structure. The method for forming the semiconductor structure further comprises the following steps: source and drain doped regions are also subsequently formed on the semiconductor pillars 112.
In this embodiment, a source-drain doped region is formed in the substrate 105 by ion implantation. The ion implantation direction is parallel to the normal of the substrate 105.
In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, i.e. the source/drain doped regions are doped with P-type ions. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is used to form a NMOS (Negative channel Metal Oxide Semiconductor) transistor, and the source-drain doped regions are doped with N-type ions. Specifically, the N-type ions include P, as or Sb.
Referring to fig. 15 and 16, fig. 15 is a top view of fig. 16, after forming the semiconductor 112, an isolation layer 113 is formed on the substrate 105 where the semiconductor pillars 112 are exposed, the isolation layer 113 covering a portion of the sidewalls of the semiconductor pillars 112.
The isolation layer 113 is used to electrically isolate the gate structure formed later from the source-drain doped region, so as to optimize the electrical performance of the semiconductor structure.
In this embodiment, the material of the isolation layer 113 is an insulating material. Specifically, the material of the isolation layer 113 includes one or more of silicon oxide, silicon nitride, silicon carbonitride oxide, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the material of the isolation layer 113 is silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 113; in addition, the smaller dielectric constant of the silicon oxide is also beneficial to improving the function of the subsequent isolation layer 113 for isolating adjacent devices.
The step of forming the isolation layer 113 includes: forming an isolation material layer (not shown) on the source-drain doped regions exposed by the semiconductor pillars 112, the isolation material layer covering the semiconductor pillars 112; planarizing the isolation material layer until the first mask layer 111 and the second mask layer 108 are exposed; and forming the isolation layer 113 on the substrate 105 exposed by the semiconductor column 112 by taking the first mask layer 111 and the second mask layer 108 as mask etching back part of the isolation material layer.
In this embodiment, the isolation material layer is formed using a flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process. The flowable chemical vapor deposition process has good filling capability, is beneficial to reducing the probability of forming defects such as cavities in the isolation material layer, and is correspondingly beneficial to improving the film forming quality of the isolation material layer.
After the isolation layer 113 is formed, si—h bonds and si—o bonds are typically present in the isolation layer 113, and the isolation layer 113 is annealed to break the si—h bonds and the si—o bonds, so that the material of the isolation layer 113 becomes denser, but the isolation layer 113 is also easily deformed, so that the isolation layer 113 has a larger stress. Compared with the case that the semiconductor column is cylindrical, the height of the semiconductor column 112 is smaller than the height and width of the semiconductor column 112 in any cross direction, so that the semiconductor column 112 is not easy to bend or incline when being stressed by the isolation layer 113, and the electrical performance of the semiconductor structure is improved.
The spacer 113 is preferably not too thick or too thin. If the isolation layer 113 is too thick, the gate structure formed on the semiconductor pillar 112 is too short, which may result in poor effect of controlling short channel effect of the gate structure, and is unfavorable for improving electrical performance of the semiconductor structure. If the isolation layer 113 is too thin, the distance between the gate structure and the source-drain doped region formed on the semiconductor pillar 112 is too short, which is not beneficial to optimizing the electrical performance of the semiconductor structure. In this embodiment, the thickness of the isolation layer 113 is 5 nm to 15 nm.
It should be noted that the method for forming the semiconductor structure includes: after the isolation layer 113 is formed, the first mask layer 111 (shown in fig. 14) and the second mask layer 108 (shown in fig. 14) are removed.
In this embodiment, a wet etching process is used to remove the first mask layer 111 and the second mask layer 108.
Specifically, the wet etching solution is a hot phosphoric acid solution.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Fig. 17 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.
The semiconductor structure includes: a substrate 200; a semiconductor pillar 300 crossing over the substrate 200; the semiconductor pillar 300 includes a first pillar 301 and a second pillar 302, a projection of the first pillar 301 in the substrate 200 is elongated, a projection of the second pillar 302 in the substrate 200 is elongated, the first pillar 301 and the second pillar 302 intersect in a horizontal plane, and a top surface of the first pillar 301 and a top surface of the second pillar 302 are flush; an isolation layer 400 is located on the substrate 200 where the semiconductor pillars are exposed, and the isolation layer 400 covers part of the sidewalls of the semiconductor pillars.
In this embodiment, the semiconductor pillars 300 are cross-shaped, and the semiconductor pillars 300 include: a first pillar 301 and a second pillar 302, wherein a projection of the first pillar 301 in the substrate 200 is elongated, a projection of the second pillar 302 in the substrate 200 is elongated, the first pillar 301 and the second pillar 302 intersect in a horizontal plane, and a top surface of the first pillar 301 and a top surface of the second pillar 302 are flush. Compared with the case where the semiconductor pillars 300 are cylindrical, the height of the semiconductor pillars 300 is smaller than the height and width of the dimension of the first pillars 301 or the dimension of the second pillars 302 in the extending direction, so that the cross-shaped semiconductor pillars 300 are not easy to bend or incline when being stressed in the isolation layer 400, and the electrical performance of the semiconductor structure is improved.
The substrate 200 provides a process basis for the subsequent formation of semiconductor structures.
In this embodiment, the material of the substrate 200 is silicon. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate 200 may be a material suitable for process requirements or easy integration.
In this embodiment, the semiconductor pillar 300 and the substrate 200 are integrally formed. Accordingly, the material of the semiconductor pillar 300 is the same as that of the substrate 200, and will not be described here again.
In this embodiment, the projection of the first pillar 301 in the substrate 200 is perpendicular to the projection of the second pillar 302 in the substrate 200.
The intersecting directions of the semiconductor pillars 300 are perpendicular to each other, so that the two extending directions of the first pillar 301 and the second pillar 302 are circumferentially arranged at equal angles with the intersection point of the first pillar 301 and the second pillar 302 as the center, so that the semiconductor pillars 300 are stressed more uniformly when being stressed in the isolation layer 400, and are not easy to bend or incline, and the electrical performance of the semiconductor structure is improved.
In this embodiment, the semiconductor structure further includes: a first mask layer (not shown) is located on the first pillars 301 in the semiconductor pillars, and sidewalls of the first mask layer are flush with sidewalls of the first pillars 301.
The first pillars 301 are etched using the first mask layer as a mask.
Specifically, the materials of the first mask layer include: one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, amorphous carbon, amorphous germanium, and boron carbonitride. In this embodiment, the material of the first mask layer includes silicon nitride.
The extending direction of the first column 301 in the horizontal plane is set as a first direction, and the horizontal plane is set to be perpendicular to the first direction as a second direction, and the ratio of the first direction to the second direction is not easily too large or too small. If the ratio is too large, the first column 301 is too thin, and the first column 301 is easy to bend or incline when being stressed by the isolating layer 400; if the ratio is too small, the ratio of the height of the semiconductor pillar 300 to the height of the first direction dimension of the first pillar 301 is too large, so that the semiconductor pillar is prone to bending or tilting when being stressed in the isolation layer 400, and the electrical performance of the semiconductor structure is not prone to be improved. In this embodiment, the ratio of the dimension of the first direction to the dimension of the second direction in the first column 301 is 2 to 4.
The semiconductor pillar further includes: a second mask layer (not shown) is located on the second pillars 302 in the semiconductor pillars, and sidewalls of the second mask layer are flush with sidewalls of the second pillars 302.
The second pillar 302 is etched using the second mask layer as a mask. In this embodiment, the materials of the first mask layer and the second mask layer are the same, so that the forming process can be completed on the same machine, and the complexity of the process can be reduced.
Specifically, the materials of the second mask layer include: one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, amorphous carbon, amorphous germanium, and boron carbonitride. In this embodiment, the material of the second mask layer includes silicon nitride.
The extending direction of second column 302 in the horizontal plane is taken as a first direction, and the horizontal plane is perpendicular to the first direction as a second direction, and the ratio of the first direction to the second direction is not easily too large or too small. If the ratio is too large, the second body 302 is too thin, and the second body 302 is easily bent or inclined when being subjected to the stress in the isolation layer 400; if the ratio is too small, the ratio of the height of the semiconductor pillar 300 to the height of the second pillar 302 in the first direction is too large, so that the cross-type semiconductor pillar is easy to bend or incline when being stressed in the isolation layer 400, and the electrical performance of the semiconductor structure is not easy to be improved. In this embodiment, the ratio of the dimension of the first direction to the dimension of the second direction in the second column 302 is 2 to 4.
The semiconductor structure may be formed by the forming method of the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure of the present embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the embodiments of the present invention are disclosed above, the embodiments of the present invention are not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the embodiments of the invention, and the scope of the embodiments of the invention should be pointed out in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a first mask material layer in a strip shape on the substrate;
etching the substrate by taking the first mask material layer as a mask to form a substrate and a semiconductor film positioned on the substrate;
after the semiconductor film is formed, thinning the two sides of the first mask material layer along the vertical extending direction to form a first initial mask layer;
forming a second mask material layer which is crossed with the first initial mask layer and takes the shape of a long strip on the first initial mask layer;
Etching the first initial mask layer and the semiconductor film by taking the second mask material layer as a mask to form an initial semiconductor column and a first mask layer positioned on the initial semiconductor column;
after the first mask layer is formed, thinning the two sides of the second mask material layer perpendicular to the extending direction to form a second mask layer;
etching the initial semiconductor column by taking the first mask layer and the second mask layer as masks to form a cross semiconductor column;
after the semiconductor column is formed, an isolation layer is formed on the substrate exposed by the semiconductor column, and the isolation layer covers part of the side wall of the semiconductor column.
2. The method of forming a semiconductor structure of claim 1, wherein forming the first masking material layer comprises: forming the first initial mask layer on the substrate; forming an auxiliary side wall layer on the side wall of the first initial mask layer, wherein the first initial mask layer and the auxiliary side wall layer serve as a first mask material layer;
the step of forming the first initial mask layer comprises the following steps: and removing the auxiliary side wall layer.
3. The method of forming a semiconductor structure of claim 1, wherein forming the first masking material layer comprises: forming a first mask material film on the substrate; patterning the first mask material film to form a strip-shaped first mask material layer;
The step of forming the first initial mask layer comprises the following steps: forming a first hard mask layer on the first mask material layer, wherein the extending direction of the first hard mask layer is the same as that of the first mask material layer; the size of the first hard mask layer is smaller than that of the first mask material layer along the extending direction perpendicular to the first mask material layer, and the first mask material layer is exposed from two sides of the first hard mask layer; etching the first mask material layer by taking the first hard mask layer as a mask to form the first initial mask layer;
the method for forming the semiconductor structure comprises the following steps: and removing the first hard mask layer after the first initial mask layer is formed.
4. The method of claim 3, wherein the first mask material layer is etched using a dry etching process to form the first initial mask layer.
5. The method of forming a semiconductor structure of claim 1, wherein after forming the first initial mask layer, before forming a second mask material layer, further comprising: forming a filling layer on the substrate exposed by the first initial mask layer, wherein the filling layer covers the side wall of the first initial mask layer and exposes the top surface of the first initial mask layer;
The method for forming the semiconductor structure further comprises the following steps: and removing the filling layer after the first mask layer and the second mask layer are formed.
6. The method of forming a semiconductor structure of claim 1, wherein the step of forming a second mask material layer comprises: forming a second mask layer on the first initial mask layer, wherein the second mask layer covers part of the top surface of the first initial mask layer;
forming an auxiliary side wall layer on the side wall of the second mask layer, wherein the second mask layer and the auxiliary side wall layer serve as a second mask material layer;
the step of forming the second mask layer includes: and removing the auxiliary side wall layer.
7. The method of forming a semiconductor structure of claim 2 or 6, wherein the material of the auxiliary sidewall layer comprises silicon oxide.
8. The method of forming a semiconductor structure of claim 1, wherein the step of forming a second mask material layer comprises: forming a second mask material film on the first initial mask layer; patterning the second mask material film to form a strip-shaped second mask material layer;
the step of forming the second mask layer includes: forming a second hard mask layer on the second mask material layer, wherein the extending direction of the second hard mask layer is the same as that of the second mask material layer, the size of the second hard mask layer is smaller than that of the second mask material layer in the direction perpendicular to the extending direction of the second mask material layer, and the two sides of the second hard mask layer are exposed out of the second mask material layer; etching the second mask material layer by taking the second hard mask layer as a mask to form a second mask layer;
The method for forming the semiconductor structure comprises the following steps: and removing the second hard mask layer after the second mask layer is formed.
9. The method of forming a semiconductor structure of claim 1, wherein the first initial mask layer and the semiconductor film are etched using a dry etching process to form an initial semiconductor pillar and a first mask layer on the initial semiconductor pillar.
10. The method of forming a semiconductor structure of claim 1, wherein the materials of the first mask layer and the second mask layer each comprise: one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, amorphous carbon, amorphous germanium, and boron carbonitride.
11. The method of forming a semiconductor structure of claim 1, wherein the first mask layer and the second mask layer are of the same material;
in the step of forming the second mask material layer: the thickness of the second mask layer is 2 to 3 times that of the first mask layer.
12. The method of forming a semiconductor structure of claim 1, wherein a ratio of a dimension of the first mask layer in an extension direction in a horizontal plane to a dimension of the first mask layer in a horizontal plane perpendicular to the extension direction in the horizontal plane is 2 to 4; the ratio of the dimension of the second mask layer in the extending direction in the horizontal plane to the dimension of the second mask layer in the extending direction perpendicular to the second mask layer in the horizontal plane is 2 to 4.
13. The method of claim 1, wherein the initial semiconductor pillars are etched using a dry etching process with the first mask layer and the second mask layer as masks, to form the semiconductor pillars.
14. The method of claim 1, wherein the direction of extension of the first mask layer is perpendicular to the direction of extension of the second mask layer.
15. A semiconductor structure, comprising:
a substrate;
a semiconductor pillar located on the substrate; the semiconductor column comprises a first column body and a second column body, wherein the projection of the first column body in the substrate is in a strip shape, the projection of the second column body in the substrate is in a strip shape, the first column body and the second column body are intersected in a horizontal plane, and the top surface of the first column body is flush with the top surface of the second column body;
and the isolation layer is positioned on the substrate exposed by the semiconductor column and covers part of the side wall of the semiconductor column.
16. The semiconductor structure of claim 15, wherein a projection of the first pillars into the substrate is perpendicular to a projection of the second pillars into the substrate.
17. The semiconductor structure of claim 15, wherein a ratio of a dimension of the first pillar in an extension direction in a horizontal plane to a dimension of the first pillar in a horizontal plane perpendicular to the extension direction of the first pillar in the horizontal plane is 2 to 4; the ratio of the dimension of the second column in the extending direction in the horizontal plane to the dimension of the second column in the extending direction perpendicular to the second column in the horizontal plane is 2 to 4.
18. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: the first mask layer is positioned on the first column body, and the side wall of the first mask layer is flush with the side wall of the first column body;
the semiconductor pillar further includes: the second mask layer is positioned on the second column body, and the side wall of the second mask layer is flush with the side wall of the second column body.
19. The semiconductor structure of claim 18, wherein the materials of the first mask layer and the second mask layer each comprise: one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride, amorphous carbon, amorphous germanium, and boron carbonitride.
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| JP2016171323A (en) * | 2015-03-10 | 2016-09-23 | Ｓｐｐテクノロジーズ株式会社 | Wiring board manufacturing method |
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| JP2016171323A (en) * | 2015-03-10 | 2016-09-23 | Ｓｐｐテクノロジーズ株式会社 | Wiring board manufacturing method |
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