CN113745214B - Semiconductor structure and forming method thereof - Google Patents

Semiconductor structure and forming method thereof Download PDF

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Publication number
CN113745214B
CN113745214B CN202010472421.XA CN202010472421A CN113745214B CN 113745214 B CN113745214 B CN 113745214B CN 202010472421 A CN202010472421 A CN 202010472421A CN 113745214 B CN113745214 B CN 113745214B
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layer
material layer
forming
gate material
semiconductor
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CN113745214A (en
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张海洋
陈建
柯星
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: forming a plurality of discrete stacked structures, wherein the stacked structures comprise a first doping layer, a semiconductor column positioned on the first doping layer and a second doping layer positioned on the semiconductor column; forming a gate material layer conformally covering the semiconductor column and the second doped layer; forming an interlayer dielectric layer between the semiconductor columns, wherein the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doping layer; carrying out one or more atomic layer etching treatments on the gate material layer exposed from the interlayer dielectric layer to form a gate structure, wherein the atomic layer etching treatments comprise: and forming an organic layer on the surface of the gate material layer exposed from the interlayer dielectric layer, and removing the organic layer. The organic layer further reduces the bond energy between the atoms on the outermost surface of the gate material layer and the atoms on the inner layer, and in the process of removing the organic layer, the atoms on the outermost surface of the gate material layer can be peeled off, and after multiple atomic layer etching treatments, the gate structure can be formed.

Description

Semiconductor structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration, and the development trend of semiconductor process nodes following moore's law is continuously decreasing. Transistors are currently being widely used as the most basic semiconductor devices, and therefore, as the element density and integration level of the semiconductor devices are improved, the channel length of the transistors has to be continuously shortened in order to accommodate the reduction of process nodes.
The reduction of the transistor channel length has the benefits of increasing the die density of the chip, increasing the switching speed, and the like. However, as the channel length is shortened, the distance between the source and the drain of the transistor is shortened, the control capability of the gate to the channel is reduced, so that the subthreshold leakage (subthreshold leakage) phenomenon, that is, short-channel effects (SCE) is more likely to occur, and the channel leakage current of the transistor is increased.
Accordingly, to better accommodate the demand for device scaling, semiconductor processes are increasingly beginning to transition from planar transistors to three-dimensional transistors with higher power, such as Gate-all-around (GAA) transistors. In the fully-enclosed gate transistor, the gate encloses the region where the channel is located from the periphery, and compared with a planar transistor, the gate of the fully-enclosed gate transistor has stronger control capability on the channel and can better inhibit the short channel effect.
The fully-surrounding Gate transistors include a Lateral Gate-all-around (lga) transistor and a Vertical Gate-all-around (VGAA) transistor, wherein the channel of VGAA extends in a direction perpendicular to the substrate surface, which is advantageous for improving the area utilization efficiency of the semiconductor structure, and thus for achieving further feature size reduction.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and optimizes the performance of the semiconductor structure.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises an initial substrate, a first doped material layer positioned on the initial substrate, a semiconductor material layer positioned on the first doped material layer and a second doped material layer positioned on the semiconductor material layer; etching the second doped material layer, the semiconductor material layer and the first doped material layer to form a plurality of discrete laminated structures, wherein each laminated structure comprises a first doped layer, a semiconductor column positioned on the first doped layer and a second doped layer positioned on the semiconductor column; forming a gate material layer conformally covering the semiconductor column and the second doped layer; forming an interlayer dielectric layer between the semiconductor columns after forming the gate material layer, wherein the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer; performing one or more atomic layer etching treatments on the gate material layer exposed from the interlayer dielectric layer to form a gate structure, wherein the atomic layer etching treatments comprise: and forming an organic layer on the surface of the gate material layer exposed from the interlayer dielectric layer, and removing the organic layer.
Optionally, the material of the organic layer includes a halogen element.
Optionally, the material of the organic layer includes one or more elements of chlorine, bromine and fluorine.
Optionally, in the step of forming the organic layer, a thickness of the organic layer on the surface of the gate material layer is 0.5 nm to 5 nm.
Optionally, a plasma chemical vapor deposition process is used to form the organic layer on the surface of the gate material layer.
Optionally, an anisotropic physical etching process is used to remove the organic layer.
Optionally, the anisotropic physical etching process comprises a plasma belt etching process.
Optionally, the process parameters of the plasma belt etching process for the organic layer include: the included angle between the incidence direction of etching ions and the normal line of the surface of the substrate is more than 10 degrees and less than 45 degrees, the etching ions comprise one or more of He, ar, ne, kr and Xe, the bias voltage is 50V to 1000V, and the pressure of the chamber is 5mTorr to 1000mTorr.
Optionally, in the step of forming the gate material layer, the reactant used includes a precursor of the gate material layer.
Optionally, the precursor of the gate material layer includes a precursor of tungsten.
Optionally, an atomic layer deposition process is used to form the gate material layer.
Optionally, the forming step of the interlayer dielectric layer includes: forming an interlayer material film covering the gate material layer, wherein the top surface of the interlayer material film is higher than the top surface of the gate material layer; curing the interlayer material film to form an interlayer material layer; and etching back part of the interlayer material layer with the thickness, and taking the rest of the interlayer material layer as an interlayer dielectric layer.
Optionally, the material of the interlayer material film includes silsesquioxane.
Optionally, the interlayer material film is subjected to a curing treatment by an electron beam curing treatment.
Optionally, after forming the laminated structure, etching the initial substrate with partial thickness to form a substrate and a fin part positioned on the substrate; the method for forming the semiconductor structure further comprises the following steps: after the fin part is formed, before the grid electrode material layer is formed, an isolation layer is formed on the substrate exposed by the fin part and the first doping layer, and the top surface of the isolation layer is higher than the top surface of the fin part and lower than or flush with the top surface of the first doping layer; in the step of forming the gate material layer, the gate material layer is formed on the stacked structure exposing the isolation layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a stacked structure discrete on the substrate; the laminated structure includes: a first doped layer, a semiconductor pillar on the first doped layer, and a second doped layer on the semiconductor layer; a gate material layer conformally covering the semiconductor pillars and the second doped layer; the interlayer dielectric layer covers part of the side wall of the grid electrode material layer, and the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doping layer; and the organic matter layer is positioned on the surface of the gate material layer exposing the interlayer dielectric layer.
Optionally, the material of the organic layer includes a halogen element.
Optionally, the organic layer includes one or more elements of chlorine, bromine, and fluorine.
Optionally, the thickness of the organic layer on the surface of the gate material layer is 0.5 nm to 5 nm.
Optionally, the semiconductor structure further includes: the fin part is positioned between the substrate and the first doped layer; the semiconductor structure further includes: the isolation layer is positioned on the substrate between the fin part and the first doping layer, and the top surface of the isolation layer is higher than the top surface of the fin part and lower than or flush with the top surface of the first doping layer; the gate material layer is located on the isolation layer and on the top surface and the side walls of the laminated structure higher than the isolation layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the method for forming the semiconductor structure, provided by the embodiment of the invention, one or more atomic layer etching treatments are carried out on the gate material layer exposed out of the interlayer dielectric layer to form the gate structure, and the atomic layer etching treatments comprise: and forming an organic layer on the surface of the gate material layer exposed out of the interlayer dielectric layer, wherein in the gate material layer, the bond energy between the atoms at the outermost surface and the atoms at the inner layer is generally smaller than the bond energy between the atoms at the inner layer, the organic layer is provided with free radicals (radio), and the free radicals are provided with elements capable of reacting with the gate material layer, so that the bond energy between the atoms at the outermost surface of the gate material layer and the atoms at the inner layer is further reduced, and the atoms at the outermost surface of the gate material layer can be stripped in the process of removing the organic layer, so that the gate material layer covered out of the interlayer dielectric layer is less damaged in the process of atomic layer etching treatment, and the gate material layer exposed out of the interlayer dielectric layer can be removed after multiple times of atomic layer etching treatment, and the gate structure has better formation quality, thereby improving the electrical property of the semiconductor structure.
Drawings
Fig. 1 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
As known from the background art, the channel of the vertical fully-enclosed gate transistor extends in the direction perpendicular to the surface normal of the substrate, and the source and the drain of the vertical fully-enclosed gate transistor are correspondingly arranged in the longitudinal direction, so that the area utilization efficiency of the semiconductor structure can be improved, and the semiconductor structure can be reduced to realize further feature size reduction. In a fin field effect transistor (FinFET) and a lateral full-surrounding gate transistor (LGAA), a dummy gate structure occupying a space position is formed first, then the dummy gate structure is removed, a gate opening is formed at a position of an original dummy gate structure, then a gate structure is formed in the gate opening, if the gate structure in the vertical full-surrounding gate transistor also occupies the space position by adopting the dummy gate structure, in a process of removing the dummy gate structure to form the gate opening, an aspect ratio of the gate opening is high, residues are easily present in the dummy gate structure, a gate structure formed subsequently is formed on the dummy gate structure, and when the semiconductor structure works, the gate structure cannot directly control a channel, so that electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a base, wherein the base comprises an initial substrate, a first doped material layer positioned on the initial substrate, a semiconductor material layer positioned on the first doped material layer and a second doped material layer positioned on the semiconductor material layer; etching the second doped material layer, the semiconductor material layer and the first doped material layer to form a plurality of discrete laminated structures, wherein each laminated structure comprises a first doped layer, a semiconductor column positioned on the first doped layer and a second doped layer positioned on the semiconductor column; forming a gate material layer conformally covering the semiconductor column and the second doped layer; forming an interlayer dielectric layer between the semiconductor columns after forming the gate material layer, wherein the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer; performing one or more atomic layer etching treatments on the gate material layer exposed from the interlayer dielectric layer to form a gate structure, wherein the atomic layer etching treatments comprise: and forming an organic layer on the surface of the gate material layer exposed from the interlayer dielectric layer, and removing the organic layer.
According to the method for forming the semiconductor structure, provided by the embodiment of the invention, one or more atomic layer etching treatments are carried out on the gate material layer exposed out of the interlayer dielectric layer to form the gate structure, and the atomic layer etching treatments comprise: and forming an organic layer on the surface of the gate material layer exposed out of the interlayer dielectric layer, wherein in the gate material layer, the bond energy between the atoms at the outermost surface and the atoms at the inner layer is generally smaller than the bond energy between the atoms at the inner layer, the organic layer is provided with free radicals (radio), and the free radicals are provided with elements capable of reacting with the gate material layer, so that the bond energy between the atoms at the outermost surface of the gate material layer and the atoms at the inner layer is further reduced, and the atoms at the outermost surface of the gate material layer can be stripped in the process of removing the organic layer, so that the gate material layer covered out of the interlayer dielectric layer is less damaged in the process of atomic layer etching treatment, and the gate material layer exposed out of the interlayer dielectric layer can be removed after multiple times of atomic layer etching treatment, and the gate structure has better formation quality, thereby improving the electrical property of the semiconductor structure.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, a detailed description of specific embodiments of the present invention is provided below with reference to the accompanying drawings.
Fig. 1 to 10 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 1, a base is provided, the base comprising an initial substrate 100, a first doped material layer 101 on the initial substrate 100, a semiconductor material layer 102 on the first doped material layer 101, and a second doped material layer 103 on the semiconductor material layer 102.
The initial substrate 100 provides a process platform for the subsequent formation of semiconductor structures.
In this embodiment, the material of the initial substrate 100 is silicon. In other embodiments, the starting substrate material may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the starting substrate may also be silicon on insulator or germanium on insulator.
The first doped material layer 101 provides for the subsequent formation of a first doped layer.
In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, when the PMOS transistor works, carriers in a channel are holes, and when the lattice structure of the channel is subjected to compressive stress, the migration speed of the holes becomes faster, so that the electrical performance of the PMOS transistor can be improved, and the material of the first doped material layer 101 is silicon germanium doped with P-type ions. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is used to form a NMOS (Negative channel Metal Oxide Semiconductor) transistor, when the NMOS transistor works, carriers in the channel are electrons, and when the lattice structure of the channel is subjected to compressive stress, the migration speed of the electrons becomes faster, so that the electrical performance of the NMOS transistor can be improved, and the material of the first doped material layer is silicon carbide or silicon phosphide doped with N-type ions correspondingly. Specifically, the N-type ions include P, as or Sb.
The semiconductor material layer 102 is used to prepare for the subsequent formation of semiconductor pillars.
In this embodiment, the material of the semiconductor material layer 102 is silicon. In other embodiments, the material of the semiconductor material layer may be germanium, silicon carbide, gallium arsenide, or gallium indium arsenide.
The second doped material layer 103 is used to prepare for the subsequent formation of the second doped layer.
In this embodiment, the semiconductor structure is used to form a PMOS transistor, when the PMOS transistor works, carriers in a channel are holes, and when the lattice structure of the channel is subjected to compressive stress, the migration speed of the holes becomes faster, so that the electrical performance of the PMOS transistor can be improved, and the material of the second doped material layer 103 is silicon germanium doped with P-type ions. Specifically, the P-type ions include B, ga or In.
In other embodiments, the semiconductor structure is used to form an NMOS transistor, when the NMOS transistor works, carriers in a channel are electrons, and when the lattice structure of the channel is subjected to compressive stress, the migration speed of the electrons becomes faster, so that the electrical performance of the NMOS transistor can be improved, and the material of the second doped material layer 103 is silicon carbide or silicon phosphide doped with N-type ions correspondingly. Specifically, the N-type ions include P, as or Sb.
Note that, a mask layer 104 is further formed on the second doped material layer 103.
The mask layer 104 is used as an etching mask for subsequently etching the second doped material layer 103, the semiconductor material layer 102 and the first doped material layer 101 to form a laminated structure, and the laminated structure comprises a first doped layer, a semiconductor column located on the first doped layer and a second doped layer located on the semiconductor column.
Specifically, the material of the mask layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon. In this embodiment, the material of the mask layer 104 is silicon nitride.
Referring to fig. 2, the second doped material layer 103, the semiconductor material layer 102, and the first doped material layer 101 are etched to form a plurality of discrete stacked structures including a first doped layer 105, a semiconductor pillar 106 on the first doped layer 105, and a second doped layer 107 on the semiconductor pillar 106.
The stacked structure provides for a subsequently formed fully surrounding gate structure.
Specifically, when the semiconductor structure is in operation, the semiconductor column 106 is used as a channel, and the first doped layer 105 and the second doped layer 107 are used as source-drain doped layers of the semiconductor column 106, so as to provide stress for the channel and improve the migration rate of carriers in the channel.
In this embodiment, the second doped material layer 103, the semiconductor material layer 102 and the first doped material layer 101 are etched by using the mask layer 104 as a mask and adopting a dry etching process, so as to form a discrete stacked structure. The dry etching process has anisotropic etching characteristics and good etching profile controllability, is favorable for enabling the shape of the laminated structure to meet the process requirements, and can etch the second doped material layer 103, the semiconductor material layer 102 and the first doped material layer 101 in the same etching equipment by changing etching gas, so that the process steps are simplified.
It should be noted that, the method for forming the semiconductor structure further includes: after the laminated structure is formed, etching a part of the initial substrate 100 with a thickness to form a substrate 108 and a fin 109 on the substrate 108. The first doped layer 105, the second doped layer 107 and the semiconductor pillar 106 are located on the fin 109, and then an isolation layer is formed on the substrate 108 between the fin 109 and the first doped layer 105, where the thickness of the isolation layer is larger, which is more beneficial to electrically isolating adjacent devices formed subsequently. In other embodiments, in the step of forming the laminated structure, the top of the initial substrate may be used as an etching stop position, and the initial substrate may not be etched after the laminated structure is formed correspondingly.
Referring to fig. 3 and 4, a gate material layer 110 is formed conformally covering the semiconductor pillars 106 and the second doped layer 107 (as shown in fig. 4).
The gate material layer 110 provides for the subsequent formation of a gate structure.
In this embodiment, the material of the gate material layer 110 is magnesium-tungsten alloy. In other embodiments, the material of the gate material layer may also be W, al, cu, ag, au, pt, ni or Ti.
In this embodiment, the gate material layer 110 is formed using an atomic layer deposition (Atomic Layer Deposition, ALD) process. The atomic layer deposition process refers to a deposition process in which surface reactions occur by chemisorption on the semiconductor pillars 106 and the second doped layer 107 by alternately introducing pulses of a vapor precursor into the reaction chamber. The gate material layer 110 is formed on the surfaces of the semiconductor pillars 106 and the second doped layer 107 in an atomic layer manner by an atomic layer deposition process, so that uniformity of deposition rate and thickness uniformity are improved, and the gate material layer 110 has good formation quality; in addition, the process temperature of the atomic layer deposition process is generally lower, so that the Thermal Budget (Wafer) is also reduced, and the probability of Wafer deformation and device performance deviation is reduced. In other embodiments, the gate material layer may also be formed using a chemical vapor deposition (Chemical Vapor Deposition, CVD) process.
In this embodiment, in the step of forming the gate material layer 110 by using an atomic layer deposition process, the reactant used includes a precursor of the gate material layer 110. In the step of forming the gate material layer 110 on the surfaces of the semiconductor pillars 106 and the second doped layer 107 using the precursor of the gate material layer 110, the precursor of the atomic layer deposited gate material layer 110 is rapidly cured into the gate material layer 110 in the chamber.
Specifically, the precursor of the gate material layer 110 includes a precursor of tungsten, and the corresponding gate material layer 110 includes tungsten.
In this embodiment, the method for forming a semiconductor structure further includes: after the fin 109 is formed, before the gate material layer 110 is formed, an isolation layer 111 is formed on the substrate 108 exposed by the fin 109 and the first doped layer 105, and the top surface of the isolation layer 111 is higher than the top surface of the fin 109 and lower than or flush with the top surface of the first doped layer 105.
The top surface of the isolation layer 111 is higher than the top surface of the fin 109 and lower than or flush with the top surface of the first doped layer 105, that is, the isolation layer 111 covers a part of the sidewall of the first doped layer 105 or covers all the sidewalls of the first doped layer 105, which can better electrically isolate adjacent devices. In addition, the isolation layer 111 also completely exposes the semiconductor pillar 106, so that the subsequently formed gate material layer can completely cover the sidewall of the semiconductor pillar 106, and the corresponding subsequently formed gate structure can completely cover the sidewall of the semiconductor pillar 106, so that the channel can be controlled with higher control force.
In other embodiments, the isolation layer may further cover the sidewalls of the first doped layer, and in the corresponding step of forming the gate material layer, the gate material layer does not cover the sidewalls of the first doped layer.
In this embodiment, the material of the isolation layer 111 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 111; in addition, the silicon oxide has smaller dielectric constant, which is beneficial to improving the effect of isolating adjacent devices subsequently.
In the step of forming the gate material layer 110, the gate material layer 110 is formed on the stacked structure where the isolation layer 111 is exposed.
Specifically, the gate material layer 110 covers the semiconductor pillar 106, the second doped layer 107, the mask layer 104, a portion of the sidewall of the first doped layer 105, and the surface of the isolation layer 111.
It should be noted that, the method for forming the semiconductor structure further includes: forming a gate dielectric material layer (not shown) on the stacked structure and the isolation layer 111 where the stacked structure is exposed before forming the gate material layer 110 after forming the isolation layer 111; and removing the surface of the isolation layer 111 and the gate dielectric material layer right above the laminated structure, and taking the gate dielectric material layer left on the side wall of the laminated structure as a gate dielectric layer 112.
The gate material layer 110 is then subjected to one or more atomic layer etching processes to form a gate structure surrounding the sidewalls of the semiconductor pillars, and the gate dielectric layer 112 is used to electrically isolate the semiconductor pillars 106 from the gate structure.
In this embodiment, the material of the gate dielectric layer 112 includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of them.
In this embodiment, an atomic layer deposition process is used to form the gate dielectric material layer, and in other embodiments, an organometallic chemical vapor deposition (metal-organic chemical vapor deposition, MOCVD) may be used to form the gate dielectric material layer.
Specifically, in the step of forming the gate dielectric material layer, the gate dielectric material layer is further formed on the top wall and the side wall of the mask layer 104; and in the step of removing the surface of the isolation layer 111 and the gate dielectric material layer right above the laminated structure, removing the gate dielectric material layer on top of the mask layer 104.
Referring to fig. 5 to 7, after the gate material layer 110 is formed, an interlayer dielectric layer 113 (as shown in fig. 7) is formed between the semiconductor pillars 106, and a top surface of the interlayer dielectric layer 113 is lower than a bottom surface of the second doped layer 107.
The interlayer dielectric layer 113 exposes the gate material layer 110 to be removed, and in the step of subsequently removing the gate material layer 110 exposing the interlayer dielectric layer 113, the gate material layer 110 covered by the interlayer dielectric layer 113 serves as a gate structure. In addition, the interlayer dielectric layer 113 is also used to electrically isolate adjacent devices.
In this embodiment, the material of the interlayer dielectric layer 113 includes silicon oxide. Silicon oxide is a dielectric material with common process and lower cost, and has higher process compatibility. In other embodiments, the material of the interlayer dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
Specifically, the forming step of the interlayer dielectric layer 113 includes:
as shown in fig. 5, an interlayer material film 114 is formed to cover the gate material layer 110, and a top surface of the interlayer material film 114 is higher than a top surface of the gate material layer 110.
In this embodiment, the material of the interlayer material film 114 includes a silsesquioxane (hydrogen silse squioxane, HSQ), which is an inorganic spin-on glass (inorganic spin-on glass) material, and has the characteristic of achieving better flatness without etching back, so that the flatness of the top surface of the formed interlayer material film 114 is higher, and the silsesquioxane can be converted into silicon dioxide after electron beam curing (Electron Beam Curing), which is favorable for improving the flatness of the subsequently formed interlayer material layer, and the flatness of the top surface of the formed interlayer dielectric layer is higher, which is favorable for making the dimensions of the gate structures subsequently formed on the sidewalls of the stacked structures in the normal direction of the surface of the substrate 108 identical, and for improving the uniformity of the performance of the semiconductor structure.
In this embodiment, the interlayer material film 114 is formed by spin coating (spin coating). The spin coating process has the advantages of mild process conditions, simple operation and the like, and has remarkable convenient effects of reducing pollution, saving energy, improving cost performance and the like.
As shown in fig. 6, the interlayer material film 114 is cured to form an interlayer material layer 115.
Interlayer material layer 115 provides for the subsequent formation of an interlayer dielectric layer.
In this embodiment, the interlayer material film 114 is subjected to a curing treatment using an electron beam curing treatment (Electron Beam Curing, EBC). In the process of electron beam curing treatment, high-energy electron beam is emitted to the silsesquioxane to initiate polymerization and crosslinking reaction of the silsesquioxane to form silicon oxide.
As shown in fig. 7, a part of the interlayer material layer 115 is etched back, and the remaining interlayer material layer 115 serves as an interlayer dielectric layer 113.
And etching back part of the interlayer material layer 115 to form an interlayer dielectric layer 113, wherein part of the gate material layer 110 is exposed from the interlayer dielectric layer 113, and in the subsequent process, the gate material layer 110 exposed from the interlayer dielectric layer 113 is removed, and the rest of the gate material layer 110 is used as a gate structure.
In this embodiment, a dry etching process is used to etch back a portion of the interlayer material layer 115 to form the interlayer dielectric layer 113. The dry etching process is used to facilitate precise control of the removal thickness of the interlayer material layer 115 and control of the height of the gate material layer 110 covered by the interlayer dielectric layer 113.
In this embodiment, the material of the interlayer dielectric layer 113 is silicon oxide, and the etching gas is HF gas in the corresponding dry etching process.
Referring to fig. 8 to 10, the gate material layer 110 exposed by the interlayer dielectric layer 113 is subjected to one or more atomic layer etching processes to form a gate structure 116, where the atomic layer etching processes include: an organic layer 117 is formed on the surface of the gate material layer 110 where the interlayer dielectric layer 115 is exposed, and the organic layer 117 is removed.
And performing one or more atomic layer etching processes on the gate material layer 110 exposing the interlayer dielectric layer 113 to form a gate structure 116, where the atomic layer etching processes include: the organic layer 117 is formed on the surface of the gate material layer 110 where the interlayer dielectric layer 113 is exposed, in general, in the gate material layer 110, the bond energy between the outermost atoms and the inner atoms is smaller than the bond energy between the inner atoms, the organic layer 117 has free radicals (chemical), the free radicals have elements capable of reacting with the sidewalls of the gate material layer 110, so that the bond energy between the outermost atoms and the inner atoms of the gate material layer 110 is further reduced, and in the process of removing the organic layer 117, the outermost atoms of the gate material layer 110 can be peeled off, so that in the process of atomic layer etching, the gate material layer 110 covered by the interlayer dielectric layer 113 is less damaged, and after multiple atomic layer etching, the gate material layer 110 where the interlayer dielectric layer 113 is exposed can be removed, and the gate structure 116 has better formation quality, and further, the electrical performance of the semiconductor structure can be improved.
Specifically, the step of atomic layer etching treatment includes:
as shown in fig. 8, an organic layer 117 is formed on the surface of the gate material layer 110 where the interlayer dielectric layer 115 is exposed.
The organic layer 117 has a radical (chemical) therein, and the radical band has an element capable of reacting with the gate material layer 110, and the organic layer 117 can react with an atom on the outermost layer of the gate material layer 110 exposed from the interlayer dielectric layer 115, so that the bond energy between the atom on the outermost surface of the gate material layer 110 and an atom on the inner layer is further reduced, and the atom on the outermost surface of the gate material layer 110 can be peeled off in the process of removing the organic layer 117 later.
In this embodiment, the material of the organic layer 117 includes a halogen element. Specifically, the material of the organic layer 117 includes one or more elements of chlorine, bromine, and fluorine.
In this embodiment, an organic layer 117 is formed on the surface of the gate material layer 110 exposing the interlayer dielectric layer 115 by using a plasma chemical vapor deposition (plasma chemical vapor deposition, PCVD). The plasma chemical vapor deposition process has good step coverage, can control the deposition thickness of the organic layer 117, and can make the thin film purity of the silicide blocking material layer 106 higher. In other embodiments, the organic layer may also be formed using an atomic layer deposition process.
In this embodiment, in the process of forming the organic layer 117 by using the plasma chemical vapor deposition process, the reactant gas is one or both of fluorocarbon gas and fluorocarbon gas, and HBr and Cl 2 And one or more of HCl.
Specifically, the fluorocarbon gas includes: CF (compact flash) 4 、C 4 F 6 、C 4 F 8 And C 5 F 8 One or more of the following; the hydrocarbon fluorine gas includes: CH (CH) 2 F 2 And CHF 3 One or two of them.
It should be noted that the organic layer 117 on the surface of the gate material layer 110 is not too thick or too thin. If the organic layer 117 on the surface of the gate material layer 110 is too thick, it takes too much process time to form the organic layer 117, and accordingly, in the subsequent process of removing the organic layer 117, the process time spent is too long, which is not beneficial to improving the formation efficiency of the gate structure. If the organic layer 117 on the surface of the gate material layer 110 is too thin, a weak area (week point) that does not cover the organic layer 117 is easily present on the surface of the gate material layer 110, the atoms on the outermost surface of the gate material layer 110 are not easy to fully contact with the organic layer 117, and accordingly, the bond energy between the atoms on the outermost surface of the gate material layer 110 and the atoms on the inner layer in the weak area is not easy to be reduced, and after multiple atomic layer etching treatments, the gate material layer 110 in the weak area is not removed, resulting in poor formation quality of the gate structure. In this embodiment, the thickness of the organic layer 117 on the surface of the gate material layer 110 is 0.5 nm to 5 nm. For example, 1 nm, 2 nm, or 3 nm.
In the step of forming the organic layer 117 on the surface of the gate material layer 110 exposing the interlayer dielectric layer 115, the organic layer 117 is further formed on the top surface of the interlayer dielectric layer 113.
As shown in fig. 9, the organic layer 117 is removed.
In this embodiment, the organic layer 117 is removed by using an anisotropic physical etching process. The physical etching process can provide high-speed ions, and the high-speed ions can remove atoms on the outermost surface of the gate material layer 110 exposed from the interlayer dielectric layer 113 while physically removing the organic layer 117, so as to achieve the purpose of removing the gate material layer 110 exposed from the interlayer dielectric layer 113 and forming a gate structure.
In this embodiment, the anisotropic etching process is performed using a plasma belt etching process (Plasma Ribbon Beam). The etching ions in the plasma belt etching process have no selectivity to the etched material, and the etching directivity is good.
During the removal of the organic layer 117 using an anisotropic physical etching process, etching ions include one or more of He, ar, ne, kr and Xe. He. Ar, ne, kr and Xe are all inert ions, and in the process of etching the organic layer 117, the etching ions are not easy to react with the material of the interlayer dielectric layer 113 and the material of the gate material layer 110, so that impurity polymers are not easy to exist in the chamber, and the organic layer 117 on the surface of the gate material layer 110 is not disturbed.
In addition, the bias voltage should not be too large or too small during the process of removing the organic layer 117 by using the anisotropic physical etching process. If the bias voltage is too large, the etching rate of the organic layer 117 is too fast, the process controllability and the reaction rate uniformity of the etching process are small, the interlayer dielectric layer 113 is easily damaged after multiple atomic layer etching treatments, the corresponding gate material layer 110 covered by the interlayer dielectric layer 113 is easily mistakenly etched, and when the semiconductor structure works, the control capability of the gate structure 116 on the channel is not strong, so that the electrical performance of the semiconductor structure is poor. If the bias voltage is too small, the etching rate of the organic layer 117 is too slow, which is not easy to improve the formation efficiency of the gate structure 116. In this embodiment, the bias voltage is 50V to 1000V during the process of removing the organic layer 117 by using an anisotropic physical etching process. For example 100V,200V, or 500V.
It should be noted that, in the process of removing the organic layer 117 by using the anisotropic physical etching process, the chamber pressure should not be too high or too low. If the chamber pressure is too high, the etching ions tend to have a low etching rate, and have no anisotropy, the organic layer 117 is not easy to be removed, and the atoms on the outermost surface of the corresponding gate material layer 110 are not easy to be removed, so that the organic layer 117 exposed from the interlayer dielectric layer 113 is not easy to be removed. If the pressure of the chamber is too small, the etching rate of the organic layer 117 is too fast, the process controllability and the reaction rate uniformity of the etching process are small, the interlayer dielectric layer 113 is easily damaged after multiple atomic layer etching treatments, the corresponding gate material layer 110 covered by the interlayer dielectric layer 113 is easily mistakenly etched, and when the semiconductor structure works, the control capability of the gate structure 116 on the channel is not strong, so that the electrical performance of the semiconductor structure is poor. In this embodiment, the chamber pressure is 5mTorr to 1000mTorr, such as 100mTorr,200mTorr, or 300mTorr, during the process of removing the organic layer 117 using an anisotropic physical etching process.
In addition, in the process of removing the organic layer 117 by using the anisotropic physical etching process, the included angle between the incident direction of the etching ions and the normal line of the surface of the substrate should not be too large or too small, and in particular, the included angle between the incident direction of the etching ions and the normal line of the surface of the substrate 100 should not be too large or too small. If the included angle is too small, and accordingly, in the process of etching the organic layer 117, the removal rate of the gate material layer 110 on the top of the stacked structure is too much greater than the etching rate of the gate material layer 110 on the side wall of the stacked structure, after the gate material layer 110 on the top of the stacked structure is removed, the second doped layer 107 is easily damaged by mistake, and when the semiconductor structure works, the second doped layer 107 is not easy to provide enough stress for the semiconductor column 106, so that the migration rate of carriers in the channel is not high. In the process of removing the organic layer 117 by using an anisotropic physical etching process, if the included angle between the incidence direction of etching ions and the normal line of the surface of the substrate 100 is too large, a shadow effect (shadow effect) is likely to occur, and a portion of the gate material layer 110 on the sidewall of the stacked structure, which is close to the interlayer dielectric layer 113, cannot be removed smoothly, and an additional step is required to remove the gate structure 116 exposed from the interlayer dielectric layer 113, which is not beneficial to improving the formation rate of the gate structure 116. In this embodiment, in the process of removing the organic layer 117 by using an anisotropic physical etching process, an included angle between an incident direction of etching ions and a normal line of the surface of the substrate 100 is greater than 10 ° and less than 45 °, for example, 20 °,30 °, or 40 °.
It should be noted that, during the process of removing the organic layer 117, the mask layer 104 is used to protect the top of the second doped layer 107, so that the second doped layer 107 has good formation quality, and when the semiconductor structure is in operation, the second doped layer 107 can provide sufficient stress to the channel, so as to increase the migration rate of carriers in the channel.
As shown in fig. 10, after one or more atomic layer etching processes are performed on the gate material layer 110 exposed by the interlayer dielectric layer 113, a gate structure 116 is formed.
In this embodiment, the mask layer 104 is removed in the step of removing the gate material layer 110 exposing the interlayer dielectric layer 113, and removing the mask layer 104 provides for the subsequent formation of a contact plug connected to the second doped layer 107. In other embodiments, after the gate material layer exposing the interlayer dielectric layer is removed, a portion of the thickness of the mask layer may remain, and additional processing is required to remove the mask layer.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 8, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 108; a stacked structure, discrete on the substrate 108; the laminated structure includes: a first doped layer 105, a semiconductor pillar 106 located on the first doped layer 105, and a second doped layer 107 located on the semiconductor pillar 106; a gate material layer 110 conformally covering the semiconductor pillars 106 and the second doped layer 107; an interlayer dielectric layer 113 covering a portion of the sidewall of the gate material layer 110, and a top surface of the interlayer dielectric layer 113 is lower than a bottom surface of the second doped layer 107; an organic layer 117 is disposed on a surface of the gate material layer 110 where the interlayer dielectric layer 113 is exposed.
In the semiconductor structure provided in the embodiment of the present invention, the organic layer 117 is located on the surface of the gate material layer 110 where the interlayer dielectric layer 113 is exposed, in general, in the gate material layer 110, the bond energy between the outermost atom and the inner atom is smaller than the bond energy between the inner atom, and the organic layer 117 has a free radical (chemical), and the free radical has an element capable of reacting with the gate material layer 110, so that the bond energy between the outermost atom and the inner atom of the gate material layer 110 is further reduced, and in the subsequent process of removing the organic layer 117, the outermost atom of the gate material layer 110 can be peeled off, and the gate material layer 110 covered by the interlayer dielectric layer 113 is less damaged, so that the gate structure has better formation quality, and further, the electrical performance of the semiconductor structure can be improved.
In this embodiment, the material of the substrate 108 is silicon. In other embodiments, the material of the substrate may also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate may also be silicon on insulator or germanium on insulator.
The semiconductor structure further includes: a fin 109 is located between the substrate 108 and the first doped layer 105.
In this embodiment, the fin 109 is made of the same material as the substrate 108.
The semiconductor structure further includes: an isolation layer 111 is located on the substrate 108 between the fin 109 and the first doped layer 105, and a top surface of the isolation layer 111 is higher than a top surface of the fin 109 and lower than or flush with a top surface of the first doped layer 105.
The top surface of the isolation layer 111 is higher than the top surface of the fin 109 and lower than or flush with the top surface of the first doped layer 105, that is, the isolation layer 111 covers a part of the sidewall of the first doped layer 105 or covers all the sidewalls of the first doped layer 105, which can better electrically isolate adjacent devices. In addition, the isolation layer 111 may also completely expose the semiconductor pillar 106, the gate material layer 110 may completely cover the sidewall of the semiconductor pillar 106, and a corresponding gate structure formed by subsequently removing the gate material layer 110 higher than the interlayer dielectric layer 113 may completely cover the sidewall of the semiconductor pillar 106, so as to have a higher control force on the channel.
In this embodiment, the material of the isolation layer 111 includes silicon oxide. Silicon oxide is a dielectric material with common process and low cost, has high process compatibility, and is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 111; in addition, the silicon oxide has smaller dielectric constant, which is beneficial to improving the effect of isolating adjacent devices subsequently.
The semiconductor pillars 106 serve as channel regions when the semiconductor structure is in operation.
In this embodiment, the material of the semiconductor pillars 106 is silicon. In other embodiments, the semiconductor pillar material may also be germanium, silicon carbide, gallium arsenide, or gallium indium arsenide.
The first doped layer 105 and the second doped layer 107 serve as source-drain doped layers of the semiconductor pillars 106.
In this embodiment, the semiconductor structure is used to form a PMOS (Positive Channel Metal Oxide Semiconductor) transistor, when the PMOS transistor works, carriers in a channel are holes, and when the lattice structure of the channel is subjected to compressive stress, the migration speed of the holes becomes faster, so that the electrical performance of the PMOS transistor can be improved, i.e., the material of the first doped layer 105 is P-type ion doped silicon germanium. Specifically, the P-type ions include B, ga or In. In other embodiments, the semiconductor structure is used to form a NMOS (Negative channel Metal Oxide Semiconductor) transistor, when the NMOS transistor works, carriers in the channel are electrons, and when the lattice structure of the channel is subjected to compressive stress, the migration speed of the electrons becomes faster, so that the electrical performance of the NMOS transistor can be improved, and the material of the first doped layer is silicon carbide or silicon phosphide doped with N-type ions. Specifically, the N-type ions include P, as or Sb.
In this embodiment, the material of the semiconductor structure used to form the PMOS transistor, i.e., the second doped layer 107 is P-type ion doped silicon germanium. Specifically, the P-type ions include B, ga or In. In other embodiments, the semiconductor structure is used to form an NMOS transistor, and the material of the second doped layer is silicon carbide or silicon phosphide doped with N-type ions, respectively. Specifically, the N-type ions include P, as or Sb.
It should be noted that the semiconductor structure further includes: a mask layer 104 is located on the second doped layer 107. The mask layer 104 is an etching mask for etching to form a laminated structure.
Specifically, the material of the mask layer 104 includes one or more of silicon nitride, silicon oxynitride, silicon carbide nitride, boron nitride silicon and boron carbon nitride silicon. In this embodiment, the material of the mask layer 104 is silicon nitride.
The gate material layer 110 provides for the subsequent formation of a gate structure.
Specifically, the gate material layer 110 is located on the isolation layer 111, and on the top surface and the sidewalls of the stacked structure higher than the isolation layer 111. In this embodiment, the semiconductor pillar 106, the second doped layer 107 and a part of the thickness of the first doped layer 105 are higher than the isolation layer 111, and the corresponding gate material layer 110 is located on the semiconductor pillar 106, the second doped layer 107 and a part of the height of the first doped layer 105.
In this embodiment, the material of the gate material layer 110 is tungsten. In other embodiments, the material of the gate material layer may also be W, al, cu, ag, au, pt, ni or Ti.
Note that the gate material layer 110 is located on the isolation layer 111, and on the top surface and the side walls of the stacked structure higher than the isolation layer 111.
Specifically, the gate material layer 110 is formed on the sidewalls of the stacked structure, the top and side walls of the mask layer 104, and the surface of the isolation layer 111.
The semiconductor structure further includes: a gate dielectric layer 112 is located between the gate material layer 110 and the stacked structure.
The gate dielectric layer 112 is used to electrically isolate the semiconductor pillars 106 from subsequently formed gate structures.
In this embodiment, the material of the gate dielectric layer 112 includes HfO 2 、ZrO 2 HfSiO, hfSiON, hfTaO, hfTiO, hfZrO and Al 2 O 3 One or more of them.
Specifically, the gate dielectric layer 112 is located on the sidewall of the bottom of the mask layer 104, the sidewall of the second doped layer 107, the sidewall of the semiconductor pillar 106, and the sidewall of the first doped layer 105 higher than the isolation layer 111.
The interlayer dielectric layer 113 exposes the gate material layer 110 to be removed, so as to prepare for forming a gate structure later, and reduce the probability of damage to the gate material layer 110 covered by the interlayer dielectric layer 113. In addition, the interlayer dielectric layer 113 is also used for electrically isolating devices formed later.
In this embodiment, the material of the interlayer dielectric layer 113 includes silicon oxide. Silicon oxide is a dielectric material with common process and lower cost, and has higher process compatibility. In other embodiments, the material of the interlayer dielectric layer may be another insulating material such as silicon nitride or silicon oxynitride.
The organic layer 117 has a radical (chemical) therein, and the radical band has an element capable of reacting with the gate material layer 110, and the organic layer 117 can react with an atom on the outermost layer of the gate material layer 110 exposed from the interlayer dielectric layer 115, so that the bond energy between the atom on the outermost surface of the gate material layer 110 and an atom on the inner layer is further reduced, and the atom on the outermost surface of the gate material layer 110 can be peeled off in the process of removing the organic layer 117 later.
In this embodiment, the material of the organic layer 117 includes a halogen element. Specifically, the material of the organic layer 117 includes one or more elements of chlorine, bromine, and fluorine.
It should be noted that the organic layer 117 on the surface of the gate material layer 110 is not too thick or too thin. If the organic layer 117 on the surface of the gate material layer 110 is too thick, the process time spent in the subsequent process of removing the organic layer 117 is too long, which is not beneficial to improving the formation efficiency of the gate structure. If the organic layer 117 on the surface of the gate material layer 110 is too thin, a weak area (week point) that does not cover the organic layer 117 is easily present on the surface of the gate material layer 110, the atoms on the outermost surface of the gate material layer 110 are not easily fully contacted with the organic layer 117, and accordingly, the bond energy between the atoms on the outermost surface of the gate material layer 110 and the atoms on the inner layer in the weak area is not easily reduced, and in the subsequent process of removing the organic layer 117, the atoms on the outermost surface of the gate material layer 110 are not easily removed. In this embodiment, the thickness of the organic layer 117 on the surface of the gate material layer 110 is 0.5 nm to 5 nm.
The organic layer 117 is also located on the top surface of the interlayer dielectric layer 113.
The semiconductor structure may be formed by the forming method of the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure of the present embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (20)

1. A method of forming a semiconductor structure, comprising:
providing a base, wherein the base comprises an initial substrate, a first doped material layer positioned on the initial substrate, a semiconductor material layer positioned on the first doped material layer and a second doped material layer positioned on the semiconductor material layer;
etching the second doped material layer, the semiconductor material layer and the first doped material layer to form a plurality of discrete laminated structures, wherein each laminated structure comprises a first doped layer, a semiconductor column positioned on the first doped layer and a second doped layer positioned on the semiconductor column;
Forming a gate material layer conformally covering the semiconductor column and the second doped layer;
forming an interlayer dielectric layer between the semiconductor columns after forming the gate material layer, wherein the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doped layer;
performing one or more atomic layer etching treatments on the gate material layer exposed from the interlayer dielectric layer to form a gate structure, wherein the atomic layer etching treatments comprise: and forming an organic layer on the surface of the gate material layer exposed out of the interlayer dielectric layer, removing the organic layer, wherein the organic layer is provided with free radicals, the free radicals are provided with elements capable of reacting with the gate material layer, and atoms on the outermost surface of the gate material layer can be stripped in the process of removing the organic layer.
2. The method of claim 1, wherein the material of the organic layer comprises a halogen element.
3. The method of forming a semiconductor structure according to claim 1 or 2, wherein the material of the organic layer includes one or more of chlorine, bromine, and fluorine.
4. The method of forming a semiconductor structure according to claim 1, wherein in the step of forming the organic layer, a thickness of the organic layer on the surface of the gate material layer is 0.5 nm to 5 nm.
5. The method of claim 1, wherein the organic layer is formed on a surface of the gate material layer using a plasma chemical vapor deposition process.
6. The method of forming a semiconductor structure of claim 1, wherein the organic layer is removed using an anisotropic physical etching process.
7. The method of forming a semiconductor structure of claim 6, wherein the anisotropic physical etching process comprises a plasma belt etching process.
8. The method of forming a semiconductor structure of claim 7, wherein performing process parameters of a plasma belt etch process comprises: the included angle between the incidence direction of etching ions and the normal line of the surface of the substrate is more than 10 degrees and less than 45 degrees, the etching ions comprise one or more of He, ar, ne, kr and Xe, the bias voltage is 50V to 1000V, and the pressure of the chamber is 5mTorr to 1000mTorr.
9. The method of forming a semiconductor structure of claim 1, wherein the step of forming the layer of gate material comprises using a reactant comprising a precursor of the layer of gate material.
10. The method of forming a semiconductor structure of claim 9, wherein the precursor of the gate material layer comprises a precursor of tungsten.
11. The method of forming a semiconductor structure of claim 1, wherein the gate material layer is formed using an atomic layer deposition process.
12. The method of forming a semiconductor structure of claim 1, wherein the step of forming an interlayer dielectric layer comprises:
forming an interlayer material film covering the gate material layer, wherein the top surface of the interlayer material film is higher than the top surface of the gate material layer;
curing the interlayer material film to form an interlayer material layer;
and etching back part of the interlayer material layer with the thickness, and taking the rest of the interlayer material layer as an interlayer dielectric layer.
13. The method of forming a semiconductor structure of claim 12, wherein the material of the interlayer material film comprises a silsesquioxane.
14. The method for forming a semiconductor structure according to claim 12, wherein the interlayer material film is subjected to a curing treatment by an electron beam curing treatment.
15. The method of forming a semiconductor structure of claim 1, wherein after forming the stacked structure, etching a portion of the initial substrate to form a substrate and a fin on the substrate; the method for forming the semiconductor structure further comprises the following steps: after the fin part is formed, before the grid electrode material layer is formed, an isolation layer is formed on the substrate exposed by the fin part and the first doping layer, and the top surface of the isolation layer is higher than the top surface of the fin part and lower than or flush with the top surface of the first doping layer;
In the step of forming the gate material layer, the gate material layer is formed on the stacked structure exposing the isolation layer.
16. A semiconductor structure, comprising:
a substrate;
a stacked structure discrete on the substrate; the laminated structure includes: a first doped layer, a semiconductor pillar on the first doped layer, and a second doped layer on the semiconductor layer;
a gate material layer conformally covering the semiconductor pillars and the second doped layer;
the interlayer dielectric layer covers part of the side wall of the grid electrode material layer, and the top surface of the interlayer dielectric layer is lower than the bottom surface of the second doping layer;
the organic layer is positioned on the surface of the gate material layer exposed out of the interlayer dielectric layer, free radicals are arranged in the organic layer, the free radicals are provided with elements capable of reacting with the gate material layer, and atoms on the outermost surface of the gate material layer can be stripped in the process of removing the organic matters.
17. The semiconductor structure of claim 16, wherein the material of the organic layer comprises a halogen element.
18. The semiconductor structure of claim 16 or 17, wherein the organic layer comprises one or more of chlorine, bromine, and fluorine.
19. The semiconductor structure of claim 16, wherein a thickness of the organic layer at a surface of the gate material layer is 0.5 nm to 5 nm.
20. The semiconductor structure of claim 16, wherein the semiconductor structure further comprises: the fin part is positioned between the substrate and the first doped layer;
the semiconductor structure further includes: the isolation layer is positioned on the substrate between the fin part and the first doping layer, and the top surface of the isolation layer is higher than the top surface of the fin part and lower than or flush with the top surface of the first doping layer;
the gate material layer is located on the isolation layer and on the top surface and the side walls of the laminated structure higher than the isolation layer.
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CN110808250A (en) * 2019-10-12 2020-02-18 长江存储科技有限责任公司 Three-dimensional memory structure and preparation method thereof

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