CN113745112B - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
- Publication number
- CN113745112B CN113745112B CN202010469285.9A CN202010469285A CN113745112B CN 113745112 B CN113745112 B CN 113745112B CN 202010469285 A CN202010469285 A CN 202010469285A CN 113745112 B CN113745112 B CN 113745112B
- Authority
- CN
- China
- Prior art keywords
- layer
- forming
- channel
- semiconductor device
- isolation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 95
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 238000002955 isolation Methods 0.000 claims abstract description 87
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000005530 etching Methods 0.000 claims abstract description 28
- 230000002093 peripheral effect Effects 0.000 claims abstract description 27
- 239000010410 layer Substances 0.000 claims description 264
- 239000000463 material Substances 0.000 claims description 30
- 238000000231 atomic layer deposition Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- -1 silicon carbide nitride Chemical class 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 239000011241 protective layer Substances 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 230000005669 field effect Effects 0.000 description 11
- 238000006243 chemical reaction Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 3
- 238000011065 in-situ storage Methods 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000009969 flowable effect Effects 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 229910001449 indium ion Inorganic materials 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
- H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A method of forming a semiconductor device, comprising: the substrate comprises a peripheral area and a core area, wherein the peripheral area is provided with a plurality of first channel columns which are arranged separately, and the core area is provided with a plurality of second channel columns which are arranged separately; forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the first channel column and the second channel column; forming a sacrificial layer on the isolation layer of the core region and on the side wall and the top of the second channel column, wherein the etching rate of the sacrificial layer is greater than that of the isolation layer; forming a first gate oxide layer on the sacrificial layer, on the isolation layer of the peripheral region and on the side wall and the top of the first channel column; forming a patterned layer, wherein the patterned layer exposes the first gate oxide layer on the sacrificial layer; removing the exposed first gate oxide layer and the sacrificial layer at the bottom of the first gate oxide layer until the surface of the isolating layer of the core region and the top and side wall surfaces of the second channel column are exposed; to enhance the performance of the semiconductor device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a method for forming a semiconductor device.
Background
Fin field effect transistors (Fin FETs) are an emerging type of multi-gate device that generally include a Fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on either side of the gate structure. Compared with a planar metal-oxide semiconductor field effect transistor, the fin field effect transistor has stronger short channel inhibition capability and stronger working current.
With further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and conventional fin field effect transistors have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a fin field effect transistor of a gate-all-around (GAA) structure is proposed, so that the volume for serving as a channel region is increased, and the operating current of the fin field effect transistor of the gate-around structure is further increased.
However, the performance of the fin field effect transistor with the channel gate surrounding structure in the prior art needs to be improved.
Disclosure of Invention
The invention solves the technical problem of providing a method for forming a semiconductor device, which can effectively improve the performance of the finally formed semiconductor device.
In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a substrate, wherein the substrate comprises a peripheral area and a core area, the peripheral area is provided with a plurality of first channel columns which are arranged separately, and the core area is provided with a plurality of second channel columns which are arranged separately; forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the first channel column and the second channel column; forming a sacrificial layer on the isolation layer of the core region and on the side wall and the top of the second channel column, wherein the etching rate of the sacrificial layer is greater than that of the isolation layer; forming a first gate oxide layer on the sacrificial layer, on the isolation layer of the peripheral region, and on the sidewalls and top of the first channel pillar; forming a patterned layer, wherein the patterned layer exposes the first gate oxide layer on the sacrificial layer; and removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer until the surface of the isolating layer of the core region and the top and side wall surfaces of the second channel column are exposed.
Optionally, the ratio of the etching rate of the sacrificial layer to the etching rate of the isolation layer is 10:1-100:1.
Optionally, the material of the isolation layer is silicon oxide, silicon nitride, silicon oxynitride or silicon carbide nitride.
Optionally, the material of the sacrificial layer is SiN, siOCN or SiBCN.
Optionally, the process of forming the first gate oxide layer is an atomic layer deposition process or a thermal oxidation process.
Optionally, after removing the exposed first gate oxide layer and the sacrificial layer at the bottom of the first gate oxide layer to expose the surface of the isolation layer of the core region, the top and sidewall surfaces of the second channel pillars, the patterned layer is removed.
Optionally, the step of forming a sacrificial layer on the isolation layer of the core region and on the sidewalls and top of the second channel pillar includes: forming an initial sacrificial layer on the isolation layer, the side wall and the top surface of the first channel column and the side wall and the top surface of the second channel column; and etching to remove the initial sacrificial layer on the isolation layer of the peripheral region, the top of the first channel column and the side wall, and forming a sacrificial layer on the isolation layer of the core region and the side wall and the top of the second channel column.
Optionally, after removing the patterned layer, a second gate oxide layer is on a surface of the isolation layer of the core region, on top of and on sidewalls of the second channel pillars.
Optionally, the base includes a substrate and a source doped layer formed on the substrate, and the first channel pillar and the second channel pillar are formed on the source doped layer.
Optionally, forming a protective layer is further included, wherein the protective layer is located on top surfaces of the first channel pillar and the second channel pillar.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the process of removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer until the surface of the isolation layer of the core region and the top and side wall surfaces of the second channel column are exposed, on one hand, the surface of the isolation layer of the core region cannot be damaged due to the protection effect of the sacrificial layer in the process of removing the first gate oxide layer; on the other hand, in the process of removing the sacrificial layer, the etching rate of the sacrificial layer is larger than that of the isolation layer, so that the surface of the isolation layer of the core region is not damaged or hardly damaged in the etching process, the surface quality of the isolation layer of the core region is improved, and the quality of a formed semiconductor device is improved.
Drawings
Fig. 1 to 4 are schematic structural views of a semiconductor device;
fig. 5 to 12 are schematic structural views illustrating steps of a method for forming a semiconductor device according to an embodiment of the present invention.
Detailed Description
The performance of the fin field effect transistor with the channel gate surrounding structure in the prior art needs to be improved. The following will make a detailed description with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, wherein the substrate 100 includes a core region I and a peripheral region II adjacent to each other, the peripheral region II has a first channel pillar 101 thereon, and the core region I has a second channel pillar 102 thereon.
Referring to fig. 2, an isolation layer 103 is formed on the substrate 100, the isolation layer 103 covers a portion of sidewall surfaces of the first channel pillar 101 and the second channel pillar 102, and a top surface of the isolation layer 103 is lower than top surfaces of the first channel pillar 101 and the second channel pillar 102.
Referring to fig. 3, after the isolation layer 103 is formed, a first gate oxide layer 104 is formed on the isolation layer 103, on the sidewalls and tops of the first channel pillars 101, and on the tops and sidewalls of the second channel pillars 102.
Referring to fig. 4, after forming the first gate oxide layer 104, the first gate oxide layer 104 on the isolation layer 103 of the core region I and on the top and side walls of the second channel pillar 102 is removed to expose the surface of the isolation layer 103 of the core region I and the top and side wall surfaces of the second channel pillar 102.
The inventors have found that, when the first gate oxide layer 104 on the isolation layer 103 of the core region I and on the top and side walls of the second channel pillar 102 are removed until the surface of the isolation layer 103 of the core region I and the top and side wall surfaces of the second channel pillar 102 are exposed, a portion of the isolation layer 103 on the core region I is removed at the same time, so that the surface of the isolation layer 103 is damaged, and thus the performance of the device is deteriorated when the device is formed in the core region I later.
The inventor researches and finds that in the process of removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer until the surface of the isolating layer of the core region and the top and side wall surfaces of the second channel column are exposed, on one hand, the surface of the isolating layer of the core region is not damaged in the process of removing the first gate oxide layer by utilizing the protection effect of the sacrificial layer; on the other hand, when the sacrificial layer is removed, the etching rate of the sacrificial layer is larger than that of the isolation layer, so that the surface of the isolation layer of the core region can be prevented from being damaged or hardly damaged in the etching process, the surface quality of the isolation layer of the core region is improved, and the electrical property of a finally formed semiconductor device is further improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 5 to 12 are schematic structural views of a forming process of a semiconductor device according to an embodiment of the present invention.
Referring to fig. 5, a substrate 200 is provided, wherein the substrate 200 includes a peripheral region II having a first channel pillar 201 thereon and a core region I having a second channel pillar 202 thereon.
The base includes a substrate 203 and a source doped layer 204 formed on the substrate 203, and the first channel pillar 201 and the second channel pillar 202 are formed on the source doped layer 204.
In this embodiment, the substrate 203 is a silicon substrate; in other embodiments, the substrate may also be a germanium substrate, a silicon-on-insulator substrate, or a semiconductor substrate such as germanium-on-insulator.
The source doped layer 204 is the source of the semiconductor device. The source doped layer 204 has doped ions therein, and the type of the doped ions is N-type or P-type; the N-type ions comprise phosphorus ions or arsenic ions; the P-type ions include boron ions or indium ions.
In this embodiment, the forming process of the source doped layer 204 includes an ion implantation process, and the method of the ion implantation process includes: ion implantation is performed on the substrate 203 to form the source doped layer 204.
In other embodiments, the forming process of the source doped layer may further use an in-situ doping process, where a method of the in-situ doping process includes: and forming an epitaxial layer on the substrate, and carrying out in-situ doping on the epitaxial layer to form the source doping layer.
The method for forming the first channel pillar 201 and the second channel pillar 202 includes: forming a channel material layer (not shown) on the source doping layer 204; forming a first mask layer (not shown) on the surface of the channel material layer, wherein the first mask layer exposes a part of the surface of the channel material layer; and etching the channel material layer by taking the first mask layer as a mask until the surface of the source doping layer 204 is exposed, forming the first channel column 201 and the second channel column 202 on the source doping layer 204, wherein the first channel column 201 is positioned on the peripheral region II, and the second channel column 202 is positioned on the core region I.
In this embodiment, the process of etching the channel material layer includes a dry etching process.
In this embodiment, the materials of the first channel pillar 201 and the second channel pillar 202 include silicon; in other embodiments, the materials of the first channel pillar and the second channel pillar may further include semiconductor materials such as germanium, silicon germanium, gallium arsenide, and the like.
In this embodiment, the process of forming the channel material layer includes an epitaxial growth process; in other embodiments, the process of forming the channel material layer includes a physical vapor deposition process or an atomic layer deposition process.
In this embodiment, the material of the first mask layer includes photoresist; in other embodiments, the material of the first mask layer comprises a hard mask material comprising silicon oxide or silicon nitride.
In this embodiment, the process of forming the first mask layer uses a spin-coating process.
After forming the first channel pillars 201 and the second channel pillars 202, the first mask layer is removed. In this embodiment, the process of removing the first mask layer includes an ashing process.
In this embodiment, a protective layer 205 is further formed on top surfaces of the first channel pillar 201 and the second channel pillar 202.
In this embodiment, the material of the protection layer 205 is silicon nitride.
The protection layer 205 is used to protect the top surfaces of the first channel pillar 201 and the second channel pillar 202 from damage during the subsequent process.
In this embodiment, the fin field effect transistor formed in the peripheral region II is used to form an input/output circuit, and the fin field effect transistor formed in the core region I is used to form a core device of an integrated circuit.
In this embodiment, the peripheral region II and the core region I are contiguous.
Referring to fig. 6, an isolation layer 206 is formed on the substrate 200, wherein the isolation layer 206 covers part of the sidewalls of the first channel pillar 201 and the second channel pillar 202.
The isolation layer 206 is used to electrically isolate the device.
The method for forming the isolation layer 206 includes: forming an initial isolation layer (not shown) on the substrate 203, the initial isolation layer covering the top and sidewalls of the first channel pillars 201 and the second channel pillars 202; planarizing the initial isolation layer until top surfaces of the first channel pillars 201 and the second channel pillars 202 are exposed; after the planarization process, portions of the initial spacer are etched to form the spacer 206.
The material of the isolation layer 206 includes silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride; the process of forming the initial isolation layer includes a chemical vapor deposition process or an atomic layer deposition process or a physical vapor deposition process.
In this embodiment, the material of the isolation layer 206 includes silicon oxide; the process for forming the initial isolation material layer comprises a chemical vapor deposition process, in particular a flowable chemical vapor deposition process, wherein the flowable chemical vapor deposition process can form the initial isolation layer with better structural compactness.
A sacrificial layer 207 is formed on the isolation layer 206 of the core region I and on the sidewalls and top of the second channel pillar 202, the sacrificial layer 207 having an etch rate greater than the etch rate of the isolation layer 206.
The step of forming the sacrificial layer 207 on the isolation layer 206 of the core region and on the sidewalls and top of the second channel pillars 202 is shown in fig. 7-8.
Referring to fig. 7, an initial sacrificial layer 214 is formed on the isolation layer 206, the sidewalls and top surfaces of the first channel pillars 201, and the sidewalls and top surfaces of the second channel pillars 202.
In this embodiment, the material of the initial sacrificial layer 214 is silicon nitride; in other embodiments, the material of the initial sacrificial layer 214 may also be SiOCN or SiBCN.
In this embodiment, the process of forming the initial sacrificial layer 214 is an Atomic Layer Deposition (ALD), and specific parameters include: using SiH 2 Cl 2 Or NH 3 As the reaction gas, the flow rate of the reaction gas is 1000 sccm-5000 sccm, the reaction temperature is 200 ℃ to 600 ℃, the reaction pressure is 10 mTorr-150 mTorr, and the reaction period is 15 s-100 s.
In the present embodiment, the process of forming the initial sacrificial layer 214 is an Atomic Layer Deposition (ALD) process, because the ALD process can form the initial sacrificial layer 214 with better thickness uniformity, and the formation thickness of the initial sacrificial layer 214 is better controlled.
Referring to fig. 8, the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and side walls of the first channel pillar 201 is etched away, and a sacrificial layer 207 is formed on the isolation layer 206 of the core region I and on the side walls and top of the second channel pillar 202.
In this embodiment, the process of etching and removing the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and the sidewall of the first channel pillar 201 is a wet etching process; in other embodiments, the process of etching away the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and sidewalls of the first channel pillar 201 may also be a dry etching process.
In the present embodiment, the reason for adopting the wet etching process is that the wet etching process has a higher selective etching ratio.
In the present embodiment, the thickness of the sacrificial layer 207 isTo->When the thickness of the sacrificial layer 207 is less than +>The sacrificial layer 207 cannot effectively protect the function of the second channel pillar; when the thickness of the sacrificial layer 207 is greater thanThe space between adjacent channel columns is smaller, the subsequent process window is smaller, and the process difficulty is increased.
In this embodiment, the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and the side walls of the first channel pillar 201 is etched away, and during the formation of the sacrificial layer 207 on the isolation layer 206 of the core region I and on the side walls and the top of the second channel pillar 202, since the etching rate of the sacrificial layer 207 is greater than the etching rate of the isolation layer 206, during the removal of the initial sacrificial layer 214 on the isolation layer 206 of the peripheral region II and on the top and the side walls of the first channel pillar 201, little or no damage is generated to the isolation layer 206 of the peripheral region II, ensuring the surface quality of the isolation layer 206 of the peripheral region II, thereby providing for the subsequent formation of a good quality semiconductor device.
Referring to fig. 9, a first gate oxide layer 208 is formed on the sacrificial layer 207, on the isolation layer 206 of the peripheral region II, and on the sidewalls and top of the first channel pillar 201.
In this embodiment, a first gate oxide layer 208 is formed on the exposed top and sidewall of the first channel pillar 201, on the isolation layer 206 of the peripheral region II, and on the sacrificial layer 207 of the core region I.
In this embodiment, the material of the first gate oxide layer 208 includes silicon oxide.
In this embodiment, the formation process of the first gate oxide layer 208 is an atomic layer deposition process; in other embodiments, the first gate oxide layer 208 may be formed by a thermal oxidation process.
Referring to fig. 10, a patterned layer 209 is formed, and the patterned layer 209 exposes the first gate oxide layer 208 on the sacrificial layer 207.
In this embodiment, a patterned layer 209 is formed on the substrate 200, and the patterned layer 209 exposes a surface of the first gate oxide layer 208 of the core region I.
In this embodiment, the patterned layer 209 is a photoresist.
In this embodiment, the patterned layer 209 can function to protect the first gate oxide layer 208 on the sidewall and top of the first channel pillar 201, the first gate oxide layer 208 on the isolation layer 206 of the peripheral region II in a subsequent process.
Referring to fig. 11, the exposed first gate oxide layer 208 and the sacrificial layer 207 at the bottom of the first gate oxide layer 208 are removed until the surface of the isolation layer 206 of the core region I and the top and sidewall surfaces of the second channel pillar 202 are exposed.
In this embodiment, the process of removing the exposed first gate oxide layer 208 and the sacrificial layer 207 located at the bottom of the first gate oxide layer 208 is a wet etching process.
In other embodiments, the process of removing the exposed first gate oxide layer 208 and the sacrificial layer 207 located at the bottom of the first gate oxide layer 208 may also be a dry etching process.
In this embodiment, the first gate oxide layer 208 and the sacrificial layer 207 are removed in one etching process, which is convenient for saving cost and controlling etching quality.
In this embodiment, the ratio of the etching rate of the sacrificial layer 207 to the etching rate of the isolation layer 206 is 10:1-100:1.
In this embodiment, in the process of removing the exposed first gate oxide layer 208 and the sacrificial layer 207 located at the bottom of the first gate oxide layer 208, on the one hand, in the process of removing the first gate oxide layer 208, since the sacrificial layer 207 is provided on the top and sidewall surfaces of the first channel pillar 201 and on the isolation layer 206 of the core region I, the surface of the first channel pillar 201 and the isolation layer 206 of the core region I is not damaged in the process of removing the first gate oxide layer 208; meanwhile, in the process of removing the sacrificial layer 207, since the etching rate of the sacrificial layer 207 is greater than that of the isolation layer 206, in the etching process, the etching reaction basically acts on the sacrificial layer 207, and the isolation layer 206 is hardly subjected to chemical reaction, so that the quality of the isolation layer 206 on the core region I is ensured, the surface of the isolation layer 206 is not damaged in the etching process, and the quality of a finally formed semiconductor device is further improved.
In this embodiment, after the exposed first gate oxide layer 208 and the sacrificial layer 207 located at the bottom of the first gate oxide layer 208 are removed to expose the surface of the isolation layer 206 of the core region I and the top and sidewall surfaces of the second channel pillar 202, the patterned layer 209 is removed.
In this embodiment, the process of removing the patterned layer 209 is an ashing process.
Referring to fig. 12, after removing the patterning layer 209, a first gate structure 210 is formed on the first channel pillar 201; a second gate structure 211 is formed on the second channel pillar 202.
The first gate structure 210 and the second gate structure 211 respectively include a gate dielectric layer 212 located on sidewalls of the first channel pillar 201 and the second channel pillar 202, a work function layer 213 located on a surface of the gate dielectric layer, and a gate layer (not shown) located on a surface of the work function layer.
In this embodiment, before forming the gate dielectric layer 212, an interface layer (not shown) is formed on the sidewalls and top of the second channel pillar 202.
In this embodiment, the material of the gate dielectric layer 212 includes a high dielectric constant material, and the dielectric constant of the high dielectric constant material is greater than 3.9; the high dielectric constant material comprises hafnium oxide or aluminum oxide; in other embodiments, the material of the gate dielectric layer 212 includes silicon oxide.
In this embodiment, the process of forming the gate dielectric material layer includes a chemical vapor deposition process; in other embodiments, the process of forming the gate dielectric material layer includes an atomic layer deposition process.
The material of the work function layer 213 includes titanium nitride, aluminum titanium, or tantalum nitride.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate comprises a peripheral area and a core area, the peripheral area is provided with a plurality of first channel columns which are arranged separately, and the core area is provided with a plurality of second channel columns which are arranged separately;
forming an isolation layer on the substrate, wherein the isolation layer covers partial side walls of the first channel column and the second channel column;
forming a sacrificial layer on the isolation layer of the core region and on the side wall and the top of the second channel column, wherein the etching rate of the sacrificial layer is greater than that of the isolation layer;
forming a first gate oxide layer on the sacrificial layer, on the isolation layer of the peripheral region, and on the sidewalls and top of the first channel pillar;
forming a patterned layer, wherein the patterned layer exposes the first gate oxide layer on the sacrificial layer;
and removing the exposed first gate oxide layer and the sacrificial layer positioned at the bottom of the first gate oxide layer until the surface of the isolating layer of the core region and the top and side wall surfaces of the second channel column are exposed.
2. The method of forming a semiconductor device according to claim 1, wherein a ratio of an etching rate of the sacrificial layer to an etching rate of the isolation layer is 10:1 to 100:1.
3. The method of forming a semiconductor device of claim 1, wherein the material of the isolation layer is silicon oxide, silicon nitride, silicon oxynitride, or silicon carbide nitride.
4. The method of forming a semiconductor device according to claim 1, wherein a material of the sacrificial layer is SiN, siOCN, or SiBCN.
5. The method of forming a semiconductor device of claim 1, wherein the process of forming the first gate oxide layer is an atomic layer deposition process or a thermal oxidation process.
6. The method of forming a semiconductor device of claim 1, wherein said patterned layer is removed after removing said exposed first gate oxide layer and said sacrificial layer at the bottom of said first gate oxide layer to expose the surface of said isolation layer of said core region and the top and sidewall surfaces of said second channel pillars.
7. The method of forming a semiconductor device of claim 1, wherein forming a sacrificial layer on the isolation layer of the core region and on sidewalls and top of the second channel pillar comprises:
forming an initial sacrificial layer on the isolation layer, the side wall and the top surface of the first channel column and the side wall and the top surface of the second channel column;
and etching to remove the initial sacrificial layer on the isolation layer of the peripheral region and the top and the side wall of the first channel column, and forming a sacrificial layer on the isolation layer of the core region and the side wall and the top of the second channel column.
8. The method of forming a semiconductor device of claim 6, wherein a first gate structure is formed on the first channel pillar and a second gate structure is formed on the second channel pillar after removing the patterned layer.
9. The method of forming a semiconductor device according to claim 1, wherein the base includes a substrate and a source doped layer formed on the substrate, and the first channel pillar and the second channel pillar are formed on the source doped layer.
10. The method of forming a semiconductor device of claim 9, further comprising forming a protective layer on top surfaces of the first channel pillar and the second channel pillar.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010469285.9A CN113745112B (en) | 2020-05-28 | 2020-05-28 | Method for forming semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010469285.9A CN113745112B (en) | 2020-05-28 | 2020-05-28 | Method for forming semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113745112A CN113745112A (en) | 2021-12-03 |
| CN113745112B true CN113745112B (en) | 2023-08-18 |
Family
ID=78724183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010469285.9A Active CN113745112B (en) | 2020-05-28 | 2020-05-28 | Method for forming semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113745112B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN105304489A (en) * | 2014-07-01 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN105826365A (en) * | 2015-01-08 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
| CN106952816A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
| CN109979880A (en) * | 2017-12-28 | 2019-07-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
-
2020
- 2020-05-28 CN CN202010469285.9A patent/CN113745112B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104795332A (en) * | 2014-01-21 | 2015-07-22 | 中芯国际集成电路制造(上海)有限公司 | Fin-type field effect transistor forming method |
| CN105304489A (en) * | 2014-07-01 | 2016-02-03 | 中芯国际集成电路制造(上海)有限公司 | Forming method of semiconductor device |
| CN105826365A (en) * | 2015-01-08 | 2016-08-03 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device and manufacturing method thereof, and electronic device |
| CN106952816A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of fin transistor |
| CN109979880A (en) * | 2017-12-28 | 2019-07-05 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113745112A (en) | 2021-12-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11721763B2 (en) | Semiconductor device and manufacturing method thereof | |
| US11264483B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN109979880B (en) | Semiconductor structure and forming method thereof | |
| CN112530943A (en) | Semiconductor device and method for manufacturing the same | |
| US11973129B2 (en) | Semiconductor device structure with inner spacer layer and method for forming the same | |
| TWI746165B (en) | Methods for forming semiconductor devices | |
| CN113555285A (en) | Method for forming semiconductor structure | |
| US11437287B2 (en) | Transistor gates and methods of forming thereof | |
| US10164097B2 (en) | Semiconductor device and manufacturing method thereof | |
| KR102045357B1 (en) | Wrapped-around epitaxial structure and method | |
| US10748816B2 (en) | Semiconductor device and fabrication method thereof | |
| CN108538724B (en) | Semiconductor structure and forming method thereof | |
| KR20220043829A (en) | Etch profile control of via opening | |
| CN110581173A (en) | Semiconductor structure and forming method thereof | |
| CN106972054B (en) | Semiconductor device and method for manufacturing the same | |
| CN111863609B (en) | Semiconductor structure and forming method thereof | |
| CN109003899B (en) | Semiconductor structure, forming method thereof and forming method of fin field effect transistor | |
| CN113745112B (en) | Method for forming semiconductor device | |
| CN113314605B (en) | Semiconductor structure and forming method thereof | |
| CN112951765B (en) | Semiconductor structure and forming method thereof | |
| CN113745113B (en) | Semiconductor device and method of forming the same | |
| CN113903805B (en) | Semiconductor structure and forming method thereof | |
| CN113745111B (en) | Semiconductor device and method of forming the same | |
| CN112928025B (en) | Semiconductor structure and forming method thereof | |
| US20230387261A1 (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |