CN109979880A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN109979880A CN109979880A CN201711458578.1A CN201711458578A CN109979880A CN 109979880 A CN109979880 A CN 109979880A CN 201711458578 A CN201711458578 A CN 201711458578A CN 109979880 A CN109979880 A CN 109979880A
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- 238000000034 method Methods 0.000 title claims abstract description 196
- 239000004065 semiconductor Substances 0.000 title claims abstract description 100
- 238000000926 separation method Methods 0.000 claims abstract description 141
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 239000000463 material Substances 0.000 claims description 73
- 230000008569 process Effects 0.000 claims description 65
- 238000005530 etching Methods 0.000 claims description 59
- 230000003647 oxidation Effects 0.000 claims description 57
- 238000007254 oxidation reaction Methods 0.000 claims description 57
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 230000004888 barrier function Effects 0.000 claims description 15
- 238000002955 isolation Methods 0.000 claims description 15
- 238000006243 chemical reaction Methods 0.000 claims description 11
- 239000003989 dielectric material Substances 0.000 claims description 11
- 239000000377 silicon dioxide Substances 0.000 claims description 11
- 239000013589 supplement Substances 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 238000011065 in-situ storage Methods 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052760 oxygen Inorganic materials 0.000 claims description 7
- 239000001301 oxygen Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 4
- 230000008859 change Effects 0.000 claims description 4
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 510
- 150000002500 ions Chemical class 0.000 description 30
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- 230000015556 catabolic process Effects 0.000 description 9
- 230000005669 field effect Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
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- 238000000151 deposition Methods 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- 229910052732 germanium Inorganic materials 0.000 description 7
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- 238000010586 diagram Methods 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
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- 239000002070 nanowire Substances 0.000 description 5
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- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
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- 229920005591 polysilicon Polymers 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 3
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910018503 SF6 Inorganic materials 0.000 description 2
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 2
- HAYXDMNJJFVXCI-UHFFFAOYSA-N arsenic(5+) Chemical compound [As+5] HAYXDMNJJFVXCI-UHFFFAOYSA-N 0.000 description 2
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- 229910052796 boron Inorganic materials 0.000 description 2
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- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 2
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- 239000012495 reaction gas Substances 0.000 description 2
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- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- AIOWANYIHSOXQY-UHFFFAOYSA-N cobalt silicon Chemical compound [Si].[Co] AIOWANYIHSOXQY-UHFFFAOYSA-N 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
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- 229910052593 corundum Inorganic materials 0.000 description 1
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- WRQGPGZATPOHHX-UHFFFAOYSA-N ethyl 2-oxohexanoate Chemical compound CCCCC(=O)C(=O)OCC WRQGPGZATPOHHX-UHFFFAOYSA-N 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 239000007792 gaseous phase Substances 0.000 description 1
- TXFYZJQDQJUDED-UHFFFAOYSA-N germanium nickel Chemical compound [Ni].[Ge] TXFYZJQDQJUDED-UHFFFAOYSA-N 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910000167 hafnon Inorganic materials 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum oxide Inorganic materials [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- 238000001465 metallisation Methods 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- KTUFCUMIWABKDW-UHFFFAOYSA-N oxo(oxolanthaniooxy)lanthanum Chemical compound O=[La]O[La]=O KTUFCUMIWABKDW-UHFFFAOYSA-N 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 229960004065 perflutren Drugs 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 1
- 229960000909 sulfur hexafluoride Drugs 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910001845 yogo sapphire Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
A kind of semiconductor structure and forming method thereof, wherein forming method includes: offer substrate, has fin column on the substrate, the fin column includes bottom zone, the channel region on the bottom zone and the top region on the channel region；The first separation layer is formed over the substrate, and first separation layer covers fin column bottom area；The first gate oxide and the second gate oxide are formed in the fin column channel region sidewall surfaces, and second gate oxide is located at the first gate oxide top surface, and the thickness of first gate oxide and the second gate oxide is not identical；Gate structure is formed in the first separation layer top surface, the gate structure covers first gate oxide and the second gate oxide；The second separation layer is formed in the gate structure top surface, second separation layer covers fin column top area side wall.The forming method can improve semiconductor structure performance.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of semiconductor structure and forming method thereof.
Background technique
With the rapid development of semiconductor processing technology, semiconductor devices is towards higher component density, and higher collection
The direction of Cheng Du is developed.With the raising of the component density and integrated level of semiconductor devices, the size of transistor is also smaller and smaller,
The reduction of transistor size keeps short-channel effect more and more significant.
In order to reduce short-channel effect, fin formula field effect transistor is operated and is given birth to.The grid of fin formula field effect transistor at
The forked 3D framework of similar fin.The grid of fin formula field effect transistor can connect through and off in more side control circuits of fin column
It opens, so as to inhibit the short-channel effect of transistor well.
The integrated level of either planar transistor or fin formula field effect transistor is still lower.In order to improve semiconductor junction
The integrated level of structure proposes a kind of vertical nanowire transistor.
However the performance of existing vertical nanowire transistor is poor.
Summary of the invention
Problems solved by the invention is to provide a kind of semiconductor structure and forming method thereof, can be improved formed semiconductor
The performance of structure.
To solve the above problems, the present invention provides a kind of forming method of semiconductor structure, comprising: substrate is provided, it is described
On substrate have fin column, the fin column include bottom zone, the channel region on the bottom zone and be located at the ditch
Top region in road area；The first gate oxide and the second gate oxide are formed in the fin column channel region sidewall surfaces, it is described
Second gate oxide is located at the first gate oxide top surface, the thickness of first gate oxide and the second gate oxide
It is not identical；Form the gate structure for covering first gate oxide and the second gate oxide side wall.
Optionally, the substrate bottom zone is for connecing the first current potential, and fin column top area is for connecing the second current potential；Institute
The first current potential is stated greater than the second current potential, the thickness of first gate oxide is greater than the thickness of the second gate oxide；Alternatively, described
Second current potential is greater than the first current potential, the thickness of the thickness of first gate oxide less than the second gate oxide.
Optionally, the thickness of first gate oxide is greater than the thickness of second gate oxide, forms described first
After gate oxide, the second gate oxide is formed；The method for forming first gate oxide includes: to fin stria road
Area and top region carry out the first oxidation processes, form the first initial gate oxidation in the fin column channel region and top region surface
Layer；The the first initial gate oxide of part channel region for removing the top region and contacting with top region forms the first gate oxidation
Layer；The method for forming second gate oxide includes: to carry out the second oxidation processes to fin column, in the fin column table exposed
Face forms the second gate oxide.
Optionally, further includes: form the first separation layer over the substrate, first separation layer covers the fin column
Bottom zone, the gate structure are located at the first separation layer top surface；Second is formed in the gate structure top surface
Separation layer, second separation layer cover fin column top area side wall；It removes the top region and is contacted with top region
The method of the initial gate oxide of part channel region first includes: to form sacrificial layer in the first separation layer top surface, described
The first separation layer top surface, and the initial gate oxidation of the sacrificial layer covering part channel region first is completely covered in sacrificial layer
Layer, the sacrificial layer top surface are lower than the channel region top surface, the material of the sacrificial layer and first separation layer
Material it is not identical；Using the sacrificial layer as exposure mask, the described first initial gate oxide is performed etching, removes exposed
One initial gate oxide forms the first gate oxide.
Optionally, the material of the sacrificial layer is polysilicon, amorphous silicon, amorphous carbon or organic dielectric material；Described
The material of one separation layer is silica, silicon nitride or low k dielectric materials.
Optionally, the technique of first oxidation processes includes moisture-generation process in situ；First oxidation processes
Technological parameter includes that reaction temperature is 850 DEG C~1050 DEG C；The technique of second oxidation processes includes that steam in situ generates work
Skill；The technological parameter of second oxidation processes includes that reaction temperature is 850 DEG C~1050 DEG C.
Optionally, first gate oxide with a thickness of 35 angstroms~45 angstroms；Second gate oxide with a thickness of 13
Angstrom~17 angstroms.
Optionally, the side of the first initial gate oxide of part channel region for removing the top region and being contacted with top region
Method includes: the protection side wall to form the initial gate oxide side wall of covering part first, and the ditch is lower than at the top of the protection side wall
Road area top surface；The described first initial gate oxide is performed etching using the protection side wall as exposure mask, removes the protection
The first initial gate oxide that side wall is exposed forms the first gate oxide.
Optionally, the thickness of first gate oxide is less than the thickness of second gate oxide；Form described first
The method of gate oxide and the second gate oxide includes: to carry out third oxidation processes to the fin column channel region and top region,
The first gate oxide is formed in the fin column channel region and top region sidewall surfaces；It is formed and covers first gate oxide
Graph layer, the graph layer top surface are lower than the channel region top surface；Using the graph layer as exposure mask, to the fin
Column carries out the 4th oxidation processes, increases the thickness of the first gate oxide exposed, forms the second gate oxide.
Optionally, it is formed after the gate structure, further includes: remove the second gate oxide of the top region.
Optionally, it is formed before the gate structure, further includes: the first source and drain doping layer is formed in the substrate surface,
The first source and drain doping floor covers fin column bottom area side wall；The gate structure is located at the first source and drain doping layer
Top.
Optionally, it is formed before the gate structure, further includes: form the first conductive structure, institute in the substrate surface
The first conductive structure is stated to be electrically connected with fin column bottom area；The gate structure is located at the top of first conductive structure.
Optionally, it is formed after the first gate oxide and the second gate oxide, further includes: form medium over the substrate
Layer；The dielectric layer covers the gate structure sidewall；The method for forming the gate structure and dielectric layer includes: to form covering
The dummy gate structure of first gate oxide, the second gate oxide and fin column top area side wall；In the substrate
Upper formation dielectric layer, the dielectric layer covers the dummy gate structure side wall, and exposes the dummy gate structure top surface；
The dummy gate structure is removed, forms gate openings in the dielectric layer；First grid knot is formed in the gate openings
Structure layer；The top region first grid structure sheaf is removed, gate structure is formed.
Optionally, the number of the fin column is multiple, and the gate structure on multiple fin columns surface is mutually discrete；Form institute
The method for stating dummy gate structure includes: to form dummy gate layer over the substrate, and the dummy gate layer covers the fin stria
Road area side wall and top region side wall and top surface；The dummy gate layer is performed etching, part dummy gate layer, shape are removed
At dummy gate structure, the pseudo- grid structure for covering adjacent fin column is mutually discrete.
Optionally, further includes: form the first source and drain doping layer, the first source and drain doping layer covering in the substrate surface
Fin column bottom area side wall；The gate structure is located at the top of the first source and drain doping layer；Form the gate structure
Later, further includes: the first contact hole is formed in the dielectric layer, the first contact hole bottom-exposed goes out first source and drain
Doped layer；It is formed after first contact hole, to the first source and drain doping layer that the first contact hole bottom-exposed goes out, is carried out
First supplement ion implanting, forms the first high-doped zone in the first source and drain doping layer；The first supplement ion implanting
Later, the first interconnection structure is formed in first contact hole.
Optionally, the method for forming the gate structure includes: the formation second grid structure sheaf in the substrate top,
The second grid structure sheaf covers first gate oxide, the second gate oxide and fin column top area side wall；It is right
The second grid structure sheaf performs etching, and removes the second grid structure sheaf of the top region, forms gate structure.
Optionally, it is formed before gate structure, further includes: form the first source in the area of the fin column bottom or in substrate
Leak doped region；It is formed after the gate structure, further includes: ion implanting is carried out to fin column top area, in the fin
The second source and drain doping area is formed in column top area, portion；Alternatively, being formed before the gate structure, further includes: in the fin column
Channel region sidewall surfaces form barrier layer；Ion implanting is carried out to the fin column using the barrier layer as exposure mask, in the fin
The first source and drain doping area is formed in column bottom area, portion, and the second source and drain doping area is formed in the area of the fin column top；Alternatively,
Further include: the second separation layer is formed in the gate structure top surface, second separation layer covers the fin column top
Area's side wall removes fin column top area, and source and drain groove is formed in second separation layer；The shape in the source and drain groove
At the second source and drain doping layer.
Correspondingly, technical solution of the present invention also provides a kind of semiconductor structure, comprising: substrate has fin on the substrate
Portion's column, the fin column includes bottom zone, the channel region on the bottom zone and the top on the channel region
Area；Positioned at the first gate oxide and the second gate oxide of the fin column channel region sidewall surfaces, first gate oxide
It is not identical with the thickness of the second gate oxide；Cover the gate structure of first gate oxide and the second gate oxide.
Optionally, further includes: the first separation layer on the substrate, first separation layer cover the fin column
Bottom zone；Dielectric layer on first separation layer, the dielectric layer cover the gate structure sidewall；The dielectric layer
Top surface is higher than or is flush to fin column top surface；There is isolation opening, the isolation opening in the dielectric layer
Bottom-exposed goes out at the top of the gate structure；The second separation layer in the isolation opening, second separation layer are located at
The gate structure top surface, and cover fin column top area side wall.
Optionally, further includes: positioned at the first source and drain doping layer of the substrate surface, the first source and drain doping layer covering
Fin column bottom area, first separation layer cover the first source and drain doping layer top surface；Positioned at the dielectric layer
In the first contact hole, the first contact hole bottom-exposed goes out the first source and drain doping layer；Positioned at first contact hole
The first high-doped zone in the first source and drain doping layer of bottom；The first interconnection structure in first contact hole.
Compared with prior art, technical solution of the present invention has the advantage that
In the forming method for the semiconductor structure that technical solution of the present invention provides, the bottom zone, channel region and top region
Orientation perpendicular to substrate surface, bottom zone and top region are for respectively forming source region and the drain region of semiconductor structure, because
This, the orientation of the source region of formed semiconductor structure, drain region and grid is perpendicular to substrate surface, formed semiconductor structure
The area of the substrate surface occupied is smaller, and therefore, the integrated level of formed semiconductor structure is higher.In addition, forming gate structure
Before, the first gate oxide and the second gate oxide, first gate oxidation are formed in the fin column channel region sidewall surfaces
The thickness of layer and the second gate oxide is not identical.Since the current potential that fin column bottom area and top region apply is not identical, described the
The thickness of one gate oxide and the second gate oxide is not identical, and the gate oxide of the higher side of fin column current potential can be made thicker,
It is breakdown to make first gate oxide and the second gate oxide be not easy；In addition, making the gate oxidation of the lower side of current potential
Layer is relatively thin, to be not easy to increase the threshold voltage of formed semiconductor structure, and then can reduce energy consumption.
Further, the first separation layer top surface is completely covered in the sacrificial layer, then is etching described first initially
During gate oxide, the sacrificial layer can protect first separation layer, reduce the loss of the first separation layer.It is described sacrificial
Domestic animal layer material it is not identical with the material of first separation layer, then during removing the sacrificial layer, the sacrificial layer and
The etching selection of first separation layer is bigger, so as to reduce the loss of first separation layer, improves formed semiconductor
The performance of structure.
Further, since the protection side wall covers the first initial gate oxidation of the fin column channel region sidewall surfaces
The thickness of layer, the protection side wall is smaller, during the first initial gate oxide described in subsequent etching, the protection side wall
Also loss can be generated, is formed by the top of the first gate oxide the distance between protection side wall top so as to reduce, from
And the removal amount for the first initial gate oxide for covering the protection side wall is larger, and then can increase the first gate oxide thickness
The uniformity of degree.
Further, it is formed before the second conductive structure, the shape in the first source and drain doping layer of first contact hole bottom
At the first high-doped zone, since the concentration of Doped ions in first high-doped zone is higher, then first high-doped zone with
The first interconnection structure Ohmic contact easy to form is mixed so as to reduce by first interconnection structure with first source and drain
Contact resistance between diamicton, and then improve the performance of formed semiconductor structure.
Further, the gate structure of adjacent fin column side wall is discrete, to make to have not on different gate structures
Same current potential, to realize different function.
Further, it is formed before dielectric layer, forms dummy gate structure, can be made by the etching of dummy gate structure subsequent
Gate structure is discrete, so as to reduce the etching to gate structure.Since the material of the dummy gate structure can be partly to lead
Body material, it is simpler to the etching technics of semiconductor material, so as to simplify technique.
In the semiconductor structure that technical solution of the present invention provides, there is the first grid in the fin column channel region sidewall surfaces
The thickness of oxide layer and the second gate oxide, first gate oxide and the second gate oxide is not identical, then the semiconductor
The threshold voltage of structure is unlikely to lower, and the first gate oxide of the semiconductor structure and the second gate oxide be not easy by
Breakdown.
Detailed description of the invention
Fig. 1 and Fig. 2 is a kind of structural schematic diagram of each step of forming method of vertical nanowire transistor；
Fig. 3 to Figure 24 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention；
Figure 25 to Figure 30 is the structural schematic diagram of each step of another embodiment of forming method of semiconductor structure of the present invention.
Specific embodiment
There are problems for the semiconductor structure of the prior art, such as: the performance of the semiconductor structure is poor.
Now in conjunction with a kind of semiconductor structure, the poor reason of the performance of the semiconductor structure is analyzed:
Since the substrate surface that traditional planar transistor occupies is larger, so as to cause semiconductor structure integrated level compared with
It is low.In order to improve the integrated level of formed semiconductor structure, a kind of vertical nanowire transistor is proposed.
Fig. 1 and Fig. 2 is a kind of structural schematic diagram of each step of forming method of vertical nanowire transistor.
Referring to FIG. 1, providing substrate 130,130 surface of substrate has fin column 131, and the fin column 131 includes
Bottom zone I, the channel region II on the I of bottom zone and the top region III on the channel region II.
It continues to refer to figure 1, oxidation processes is carried out to 131 side wall of fin column, form grid in 131 sidewall surfaces of fin column
Oxide layer 110；It is formed after gate oxide 110, forms the first metal silicide for connecting the 131 bottom zone I of fin column
141；The second metal silicide 142 is formed in 131 top surface of fin column.
Referring to FIG. 2, forming the first separation layer 150 on the substrate 130, first separation layer 150 covers described
131 bottom zone I side wall of fin column and 141 surface of the first metal compound；Grid is formed at the top of first separation layer 150
Structure 151, the gate structure 151 are located at the channel region II sidewall surfaces；Second is formed at the top of the gate structure 151
Separation layer 152, second separation layer 152 cover the top region III side wall, and expose second metal silicide
142。
It is subsequently formed the first plug for connecting first metal silicide 141；It is formed and connects second metal silication
Second plug of object 142.
Wherein, the gate oxide 110 is formed by oxidation processing technique.The grid oxygen of the 231 channel region II of fin column
Change layer 110 to be formed by same oxidation processing technique, therefore the gate oxide 110 on 231 surface channel region II of the fin column
Thickness is identical.Due to the current potential difference that the source region of transistor applies with drain region, drain region current potential is higher.If the gate oxide
110 thickness is smaller, when the voltage that the drain region connects is higher, since the electric field in drain region is stronger, is easy to cause neighbouring drain region
Gate oxide 110 is breakdown；If the thickness of the gate oxide 110 is excessive, it is easy to cause threshold voltage larger, energy consumption increases
Add.
To solve the technical problem, the present invention provides a kind of forming methods of semiconductor structure, comprising: provides lining
Bottom has fin column on the substrate, and the fin column includes bottom zone, channel region on the bottom zone and is located at
Top region on the channel region；The first gate oxide and the second gate oxidation are formed in the fin column channel region sidewall surfaces
Layer, second gate oxide are located at the first gate oxide top surface, first gate oxide and the second gate oxidation
The thickness of layer is not identical.Since the thickness of first gate oxide and the second gate oxide is not identical, by adjusting described the
The thickness of one gate oxide and the second gate oxide can make the threshold voltage of the semiconductor structure lower, and the first gate oxidation
Layer and the second gate oxide are not easy breakdown.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 3 to Figure 24 is the structural schematic diagram of each step of one embodiment of forming method of semiconductor structure of the present invention.
Referring to FIG. 3, providing substrate 200, there is fin column 201, the fin column 201 includes: bottom on the substrate 200
Area, portion A, the channel region B on the bottom zone A and the top region C on the channel region B.
In the present embodiment, the material of the substrate 200 and fin column 201 is silicon, germanium, SiGe or silicon carbide.In other realities
It applies in example, the material of the substrate and fin column can also be the monocrystal of iii-v element material.
The shape of the fin column 201 is cylinder.Specifically, the shape of the fin column 201 is cylinder in the present embodiment
Body.In other embodiments, the fin column can be square body.
In the present embodiment, 200 surface of substrate is (100) crystal orientation.
The step of forming the substrate 200 and fin column 201 includes: offer initial substrate；The shape in the initial substrate
At patterned first mask layer；The initial substrate is performed etching using first mask layer as exposure mask, forms substrate 200
With the fin column 201 being located on the substrate 200.
It is formed before first mask layer, further includes: form adhesion layer in the initial substrate.
The adhesion layer is used to improve the adhesive attraction of contact surface between the first mask layer and initial substrate.
In our department's embodiment, the material of the initial substrate is the monocrystal of silicon, germanium, SiGe or iii-v element material.
The material of first mask layer is silicon nitride or silicon oxynitride.The material of the adhesion layer is silica.
The technique performed etching to the initial substrate includes dry etch process.Dry etch process has good line
Wide control action is easy to control the size of fin column 201, and the fin column 201 formed and the up rightness on 200 surface of substrate are good.
In other embodiments, the technique performed etching to the initial substrate includes wet etching.
In the present embodiment, the bottom zone A of the fin column 201 is used to form drain region or the source region of MOS transistor；The ditch
Road area B is used to form the channel of MOS transistor；The top region C is used to form source region or the drain region of MOS transistor.
In other embodiments, formed semiconductor structure is tunnel field effect transistor.The bottom zone is used to form
The source region of tunnel field effect transistor or drain region；The channel region is used to form the channel of tunnel field effect transistor.The top
Area, portion is used to form source region or the drain region of tunnel field effect transistor.
In the present embodiment, the number of the fin column 201 is multiple.In other embodiments, the number of the fin column
It can also be one.
If the height of the fin column 201 is too small, be easy to cause the first doped region being subsequently formed, the second doped region or
Gate structure is undersized in 201 short transverse of fin column, to influence the performance of formed semiconductor structure；If institute
The height for stating fin column 201 is excessive, is easy to increase technology difficulty.Specifically, in the present embodiment, the height of the fin column 201
For 90nm~110nm, such as 100nm.
If the height of the fin column 201 is too small, it is easy to increase technology difficulty；If the diameter of the fin column 201
It is excessive, it is easily reduced the integrated level of formed semiconductor structure.Specifically, in the present embodiment, the diameter of the fin column 201 is
7nm~9nm.
In other embodiments, the forming method further include: undergauge processing is carried out to the fin column, reduces the fin
The diameter of portion's column.The step of undergauge processing includes: to carry out undergauge oxidation processes to the fin column side wall, in the fin
Column sidewall surfaces form reduction oxide layer；Remove the reduction oxide layer.The step of repeating undergauge processing, reduces the fin
The diameter of portion's column.The diameter of the fin column can be 4.8nm~5.2nm, such as 5nm.Alternatively, the fin column can also lead to
The method for crossing induced growth is formed, such as forms gold nano grain in the substrate surface, is lured by catalyst of gold nano grain
Fin column material nucleation is led, and forms fin column along axial growth since epipole.
Subsequent to form the first source and drain doping layer 211 on 200 surface of substrate, the first source and drain doping layer 211 covers
The 201 bottom zone A of fin column.
In the present embodiment, the first source and drain doping layer 211 is used as the drain region of formed semiconductor structure.First source
Leakage doped layer 211 is for connecing the first current potential.Specifically, the step of forming the first source and drain doping layer 211 is such as Fig. 4 and Fig. 5 institute
Show.
Referring to FIG. 4, forming initial source at 201 top of fin column and sidewall surfaces and 200 surface of the substrate
Leak doped layer 210.
The material of the initial source and drain doped layer 210 is silicon, germanium or SiGe.
The step of forming initial source and drain doped layer 210 include: by epitaxial growth at 201 top of the fin column and
Sidewall surfaces and 200 surface of the substrate form epitaxial layer, and are doped to the epitaxial layer, in the epitaxial layer
The first Doped ions are mixed, initial source and drain doped layer 210 is formed.
It include doping process in situ to the technique that the epitaxial layer is doped in the present embodiment.In other embodiments,
The technique being doped to the epitaxial layer includes ion implantation technology.
It should be noted that due in epitaxial process, growth speed of the epitaxial layer along<100>crystal orientation of substrate 200
Rate is most fast, and the growth rate along other crystal orientation is respectively less than<100>crystal orientation.Since 200 surface of substrate is (100) crystal face.Institute
Stating 201 sidewall surfaces of fin column includes multiple crystal plane directions, therefore, 201 side of fin column described in the epitaxial process
The growth rate of the epitaxial layer of wall is smaller, and the growth rate of the epitaxial layer on 200 surface of substrate is larger.
Again due to during etching the initial substrate and forming substrate 200 and fin column 201, the fin column 201
The turning that top is in contact with side wall is easy to be etched, and the diameter of the fin column 201 is smaller, leads to the fin column 201
Top and the 200 uneven surface row of substrate, cause the crystal plane direction of 201 top surface of fin column more diversified.?
During forming the epitaxial layer, the growth rate of the epitaxial layer of the fin column 201 is less than the outer of 200 surface of substrate
Prolong the growth rate of layer.
To sum up, the thickness of the epitaxial layer of 201 side wall of fin column and top surface is less than the outer of 200 surface of substrate
Prolong the thickness of layer.
When formed semiconductor structure is PMOS transistor, first Doped ions are P-type ion, such as boron ion
Or HB2 +Ion；When formed semiconductor structure be NMOS transistor when, first Doped ions be N-type ion, such as phosphorus from
Son or arsenic ion.
Referring to FIG. 5, performing etching to the initial source and drain doped layer 210, the initial of 201 side wall of fin column is removed
Source and drain doping layer 210 forms the first source and drain doping layer 211.
In the present embodiment, the first source and drain doping layer 211 is used as the drain region of formed semiconductor structure.First source
Leakage doped layer 211 is for connecing the first current potential.
In the present embodiment, the technique for removing the initial source and drain doped layer 210 of 201 side wall of fin column includes dry etching
The combination of technique and wet-etching technology.
Since the thickness at 201 top of fin column and the initial source and drain doped layer 210 of side wall is smaller, to described initial
During source and drain doping layer 210 performs etching, the initial source and drain doped layer 210 of 201 top of fin column and side wall is easy
It is completely removed, the initial source and drain doped layer 210 on 200 surface of section substrate is easy to be retained to form the first source and drain doping layer
211。
In the present embodiment, during the initial source and drain doped layer 210 for removing 201 side wall of fin column, institute is also removed
State the initial source and drain doped layer 210 of 201 top surface of fin column.In other embodiments, the fin capital can not be removed
The initial source and drain doped layer on portion surface.
In the case where 201 height of fin column is certain, if the first source and drain doping layer on 200 surface of the substrate
211 thickness is excessive, is easy to increase technology difficulty；If the thickness mistake of the first source and drain doping layer 211 on 200 surface of substrate
It is small, it is easy to increase the resistance of the first source and drain doping layer 211, to influence the performance of semiconductor structure.Specifically, this implementation
Example in, the first source and drain doping layer 211 on 200 surface of substrate with a thickness of 60 angstroms~100 angstroms.
Referring to FIG. 6, forming the first separation layer 220 on the substrate 200, first separation layer 220 covers described
201 bottom zone A of fin column.
In the present embodiment, first separation layer 220 covers 211 top surface of the first source and drain doping layer.
First separation layer 220 for realizing the first source and drain doping layer 211 and the gate structure that is subsequently formed it
Between electric isolution.
The material of first separation layer 220 is silica.In other embodiments, the material of first separation layer 220
Material can also be silicon oxynitride or low k (k is less than 3.9) dielectric material.
The step of forming the first separation layer 220 includes: that the first initial seal coat, institute are formed on the substrate 200
It states the first initial seal coat surface and is higher than or is flush to 201 top surface of fin column；To first initial seal coat into
Row etching, forms the first separation layer 220, and 220 surface of the first separation layer is lower than or is flush to table at the top of the bottom zone A
Face.
The technique for forming first initial seal coat includes fluid chemistry gas-phase deposition.Fluid chemistry gaseous phase deposition
The specific good clearance filling capability of technique.
The technique performed etching to first initial seal coat includes one or both of dry or wet etch group
It closes.
If the thickness of first separation layer 220 is too small, being unfavorable for first source and drain doping layer 211 and the grid that are subsequently formed
Electric isolution between the structure of pole；If the thickness of first separation layer 220 is excessive, in the certain situation of 201 height of fin column
Under, it is easy to reduce the size of gate structure or the first source and drain doping layer 211, influences the performance of formed semiconductor structure.Specifically
, first separation layer 220 with a thickness of 180 angstroms~220 angstroms.
It is subsequent to form the first gate oxide 231 and the second gate oxide in the 201 channel region B sidewall surfaces of fin column
232, second gate oxide 232 is located at 231 top surface of the first gate oxide, 231 He of the first gate oxide
The thickness of second gate oxide 232 is not identical.
In the present embodiment, the step of forming first gate oxide 231 and the second gate oxide 232 such as Fig. 7 to Figure 14
It is shown.
It in the present embodiment, is formed after first gate oxide 231, forms second gate oxide 232.
In the present embodiment, formed the first gate oxide 231 the step of as shown in Fig. 7 to Figure 14.
Referring to FIG. 7, the first oxidation processes are carried out to the 201 channel region B of fin column and top region C, in the fin
201 channel region B of column and top region C Surface form the first initial gate oxide 230.
The first initial gate oxide 230 is for being subsequently formed the first gate oxide.
In the present embodiment, the material of the fin column 201 is silicon, correspondingly, the material of the first initial gate oxide 230
Material is silica.
In other embodiments, the material of the fin column is germanium, then the material of first initial oxide layer is oxidation
Germanium；The material of the fin column is SiGe, then the material of first initial oxide layer is silicon germanium oxide.
If the thickness of the first initial gate oxide 230 is too small, when what is applied on the first source and drain doping layer 211
When current potential is higher, electric field strength locating for the first initial gate oxide 230 is larger, to be easy to cause the first gate oxide
231 is breakdown；If the thickness of the first initial gate oxide 230 is excessive, it is easy to increase the threshold of formed semiconductor structure
Threshold voltage.Specifically, the first initial gate oxide 230 with a thickness of 35 angstroms~45 angstroms.
In the present embodiment, the technique of first oxidation processes includes moisture-generation process in situ.In other embodiments,
The technique of first oxidation processes includes thermal oxidation technology.
The reaction gas of first oxidation processes includes vapor.
If the reaction temperature of first oxidation processes is excessively high, it is easy to cause reaction rate too fast, to be unfavorable for controlling
Make the thickness of the described first initial gate oxide 230；If the reaction temperature of first oxidation processes is too low, it is easily reduced life
Produce efficiency.Specifically, the reaction temperature of first oxidation processes is 850 DEG C~1050 DEG C, such as 950 DEG C.
The first initial gate oxide of subsequent removal the top region C and the part channel region B contacted with the top region C
230, the first gate oxide 231 is formed, 231 top surface of the first gate oxide is lower than the channel region B top surface.
In the present embodiment, the first of part channel region B for removing the top region C and contacting with the top region C is initial
The step of gate oxide 230, is as shown in Fig. 8 to Figure 14.
It is subsequent to form sacrificial layer 241, the 241 covering part ditch of sacrificial layer in 220 top surface of the first separation layer
The initial gate oxide 230 of road area B first, 241 top surface of sacrificial layer is lower than the channel region B top surface, described sacrificial
The material of domestic animal layer 241 is not identical as the material of first separation layer 220.
In the present embodiment, the step of forming sacrificial layer 241, is as shown in Figure 8 and Figure 9.
Referring to FIG. 8, forming initial sacrificial layer 240, the initial sacrificial layer in 220 top surface of the first separation layer
240 material is not identical as the material of first separation layer 220, and the initial sacrificial layer 240 covers 201 ditch of fin column
Road area B and the initial gate oxide 230 of top region C first.
The initial sacrificial layer 240 is located at 220 top surface of the first separation layer.The initial sacrificial layer 240 is completely
Cover 220 top surface of the first separation layer.
In the present embodiment, the material of the initial sacrificial layer 240 is polysilicon.In other embodiments, described initial sacrificial
The material of domestic animal layer can be amorphous silicon, agraphitic carbon or organic dielectric material.
In the present embodiment, the technique for forming the initial sacrificial layer 240 includes chemical vapor deposition process.In other implementations
In example, when the material of the initial sacrificial layer is organic dielectric material, the technique for forming the initial sacrificial layer includes spin coating
Technique.
Referring to FIG. 9, the initial sacrificial layer 240 of removal top region C and part channel region B, form sacrificial layer 241, it is described
241 top surface of sacrificial layer is lower than the channel region B top surface.
220 top surface of the first separation layer, the first grid oxygen described in subsequent etching is completely covered in the sacrificial layer 241
During changing layer 231, first separation layer 220 and part the first gate oxide of channel region B 231 can be protected, reduce the
The loss of one separation layer 220.The material of the sacrificial layer 241 is not identical as the material of first separation layer 220, then removes institute
During stating sacrificial layer 241, the etching selection of the sacrificial layer 241 and the first separation layer 220 is bigger, so as to reduce
The loss of first separation layer 220 improves the performance of formed semiconductor structure.
If the thickness of the sacrificial layer 241 is excessive, be easy to cause the first gate oxide 231 for being subsequently formed along perpendicular to
Oversized in 200 surface direction of substrate, the threshold voltage of formed semiconductor structure is excessively high, increases energy consumption；If described
The thickness of sacrificial layer 241 is too small, is unfavorable for the protection to first separation layer 220.Specifically, the thickness of the sacrificial layer 241
Degree is 270 angstroms~330 angstroms, such as 300 angstroms.
In the present embodiment, the technique for removing the initial sacrificial layer 240 of top region C and part channel region B includes dry etching.
In other embodiments, the technique for removing the initial sacrificial layer of the top region and part channel region includes wet etching.
Specifically, removing the technological parameter packet of the initial sacrificial layer 240 of top region C and part channel region B in the present embodiment
It includes: sulfur hexafluoride (SF6) and tetrachloro silicane (SiCl4) and chloroform (CHCl3) one of or multiple combinations.
In the present embodiment, the forming method further include: form protection side wall 251 in the channel region B sidewall surfaces.
In the present embodiment, the 251 covering part channel region B side wall of protection side wall, the protection side wall 251 is located at described
241 top surface of sacrificial layer.
In other embodiments, the protection side wall can not be formed.
In the present embodiment, formed protection side wall 251 the step of it is as shown in Figure 10 and Figure 11.
First initial 230 side wall of gate oxide and top and the sacrificial layer are covered referring to FIG. 10, being formed
The protection side wall layer 250 of 241 top surfaces.
The protection side wall layer 250 is for being subsequently formed protection side wall.
It is described to protect side wall layer 250 not identical as the material of the described first initial gate oxide 230 in the present embodiment.?
During subsequent removal protection side wall layer 250, the loss to rear thick first gate oxide can be reduced, guarantee to be subsequently formed
The uniformity of first gate oxide thickness.
In the present embodiment, the material of the protection side wall layer 250 is silicon nitride.In other embodiments, the protection side
The material of wall layers is silicon oxynitride.
If the thickness of the protection side wall layer 250 is excessive, it is easy to increase the technology difficulty of subsequent removal protection side wall；Such as
It protects the thickness of side wall layer 250 too small described in fruit, is unfavorable for the protection side wall being subsequently formed to the first initial gate oxide side wall
230 protection.Specifically, in the present embodiment, the protection side wall layer 250 with a thickness of 70 angstroms~90 angstroms, such as 80 angstroms.
The technique for forming the protection side wall layer 250 includes chemical vapor deposition process, physical gas-phase deposition or original
Sublayer depositing operation.
Figure 11 is please referred to, removal covers the 201 top region C side wall of fin column and top and the sacrificial layer 241 pushes up
The protection side wall layer 250 (as shown in Figure 10) on portion surface forms protection side wall 251.
The protection side wall 251 is protected for protecting the described first initial 230 partial sidewall of gate oxide so as to reduce
The loss of 250 side wall of side wall layer is protected, so as to keep the thickness for the first gate oxide being subsequently formed more uniform.Due to the guarantor
The thickness for protecting side wall 251 is smaller, during the first initial gate oxide 230 described in subsequent etching, the protection side wall 251
Also loss can be generated, so as to reduce the distance between 231 top of the first gate oxide and 251 top of protection side wall,
To which the removal amount for the first initial gate oxide 230 for covering the protection side wall 251 is larger, and then the first grid can be increased
The uniformity of 231 thickness of oxide layer.
In the present embodiment, removal covers the 201 top region C side wall of fin column and top and the sacrificial layer 241 pushes up
The technique of the protection side wall layer 250 on portion surface includes: anisotropic dry etch process.Anisotropic dry etch process is vertical
To etch rate be greater than lateral etch rate, so as to reduce the loss of protection 250 side wall of side wall layer, form protection side
Wall 251.
Specifically, removal covers the 201 top region C side wall of fin column and 241 top table of top and the sacrificial layer
The etching gas of the protection side wall layer 250 in face includes CF4。
If the height of the protection side wall 251 is excessive, the height for being easy to make to be formed by the first gate oxide 231 is spent
Greatly, to be easy to increase the threshold voltage of formed semiconductor structure；If the height of the protection side wall 251 is too small, unfavorable
In the uniformity of increase by 231 thickness of the first gate oxide, and the height for the first gate oxide 231 being subsequently formed is easy to cause to spend
It is small, keep the second gate oxide 232 being subsequently formed relatively close apart from the first source and drain doping layer 211, thus when the first source and drain is mixed
When current potential on diamicton 211 is higher, second gate oxide 232 is easy breakdown.Specifically, in the present embodiment, the guarantor
The height for protecting side wall 251 is 9nm~11nm.
In other embodiments, the sacrificial layer can also be formed, but does not form the protection side wall；Alternatively, forming institute
Protection side wall is stated, does not form the sacrificial layer；The protection side wall is located at the first separation layer top surface.
Figure 12 is please referred to, is exposure mask with the sacrificial layer 241 and the protection side wall 251, to the described first initial grid oxygen
Change layer 230 to perform etching, forms the first gate oxide 231.
In the present embodiment, also with the protection side wall during being performed etching to the described first initial gate oxide 230
251 be exposure mask.In other embodiments, the forming method does not include the steps that forming the protection side wall, then described in etching
Using the sacrificial layer as exposure mask during first initial gate oxide；Alternatively, when the forming method does not include forming sacrifice
When the step of layer, using the protection side wall as exposure mask during the etching first initial gate oxide.
In the present embodiment, the technique performed etching to the described first initial gate oxide 230 includes dry etch process.It is dry
Method etching technics is controlled with good line width, can effectively control the height of the first gate oxide.
In other embodiments, the technique performed etching to the described first initial gate oxide includes wet-etching technology.
In the present embodiment, the etching gas performed etching to the described first initial gate oxide 230 includes: carbon tetrafluoride
(CF4), octafluoropropane (C3F8) and fluoroform (CHF3) one of or multiple combinations.
First gate oxide 231 along perpendicular to the size in 200 surface direction of substrate be first gate oxide
231 height.
If the height of first gate oxide 231 is excessive, it is easy to increase the threshold voltage of formed semiconductor structure；
If the height of first gate oxide 231 is too small, it is easy second the first source and drain doping of gate oxide distance formed after making
Layer 211 is excessively close, when the current potential of the first source and drain doping layer 211 is higher, is easy to cause the second gate oxide 232 breakdown.
Specifically, in the present embodiment, the height of first gate oxide 231 is 400 angstroms~500 angstroms, such as 450 angstroms.
It please refers to Figure 13, is formed after first gate oxide 231, remove the protection side wall 251 (such as Figure 12 institute
Show).
In the present embodiment, the technique for removing the protection side wall 251 includes wet-etching technology.In other embodiments,
The technique for removing the protection side wall can also include isotropic dry etch technique.
Specifically, the etching liquid for removing the protection side wall 251 includes phosphoric acid in the present embodiment.
In the present embodiment, it is 720 DEG C~880 DEG C that the technological parameter for removing the protection side wall 251, which includes: reaction temperature,
Such as 800 DEG C.
Figure 14 is please referred to, is formed after first gate oxide 231, removes the sacrificial layer 241 (as shown in figure 13).
In the present embodiment, after removing the protection side wall 251 (as shown in figure 13), the sacrificial layer 241 is removed.
In the present embodiment, the technique for removing the sacrificial layer 241 includes wet-etching technology.The selectivity of wet etching
It is good, the loss of fin column 201 can be reduced.In other embodiments, the technique for removing the sacrificial layer includes dry etching work
Skill.
Specifically, in the present embodiment, remove the sacrificial layer 241 etching liquid include hydrofluoric acid and nitric acid mixing it is molten
Liquid.
During being performed etching to the described first initial gate oxide 230 (as shown in figure 11), it is easy to described
241 surface of sacrificial layer causes to damage, and causes the sacrificial layer 241 decrystallized, to be easy to make the removal of subsequent dummy gate structure
In the process, residual 241 material of sacrificial layer in 1 is opened in the grid, and then influences the performance of formed semiconductor structure, this implementation
In example, is formed after the first gate oxide 231, remove the sacrificial layer 241.
In other embodiments, the sacrificial layer is not removed, and the sacrificial layer is for being subsequently formed dummy gate structure.
Figure 15 is please referred to, forms the second gate oxidation in the channel region B sidewall surfaces that first gate oxide 231 exposes
Layer 232.
In the present embodiment, the method for forming second gate oxide 232 includes: to carry out the second oxidation to fin column 201
Processing forms the second gate oxide 232 on 201 surface of fin column that first gate oxide 231 exposes.
In the present embodiment, second gate oxide 232 is located at the fin column that first gate oxide 231 exposes
201 channel region B side walls and 201 top region C side wall of fin column and top surface.
Second oxidation processes are used to form the second gate oxide 232.
In the present embodiment, second oxidation processes are exposure mask with first separation layer 220.Second gate oxide
232 are also located at the top 201 top region C of fin column and sidewall surfaces.In second oxidation processes, described first
Separation layer 220 can protect the first source and drain doping layer 211, and the first source and drain doping layer 211 is prevented to be oxidized.
In the present embodiment, the technique of second oxidation processes includes moisture-generation process in situ.In other embodiments,
The technique of second oxidation processes includes thermal oxidation technology.
In the present embodiment, the reaction gas of second oxidation processes includes vapor.
In the present embodiment, the technological parameter of second oxidation processes includes: that reaction temperature is 850 DEG C~1050 DEG C, example
Such as 950 DEG C.
Second gate oxide 232 with a thickness of the second gate oxide 232 along perpendicular to 201 sidewall direction of fin column
On size.
If the thickness of second gate oxide 232 is excessive, it is easy to increase the threshold voltage of formed semiconductor structure；
If the thickness of second gate oxide 232 is too small, it is easy breakdown.Specifically, the thickness of second gate oxide 232
For 12 angstroms~14 angstroms, such as 15 angstroms.
The height of second gate oxide 232 is ruler of second gate oxide 232 in 201 short transverse of fin column
It is very little.
Height of the height of second gate oxide 232 equal to channel region B subtracts the height of the first gate oxide 231.
Specifically, the height of second gate oxide 232 is equal to 130 angstroms~160 angstroms in the present embodiment.
In the present embodiment, after removing the protection side wall 251 and the sacrificial layer 241, carry out at second oxidation
Reason.In other embodiments, before the protection side wall and the sacrificial layer can also be removed, formed the first gate oxide it
Afterwards, second oxidation processes are carried out.
In the present embodiment, the thickness of first gate oxide 231 is greater than the thickness of second gate oxide 232.
In other embodiments, for connecing the first current potential, fin column top area is used for the first source and drain doping layer
Connect the second current potential；Second current potential is greater than the first current potential, and the thickness of first gate oxide is less than the second gate oxide
Thickness.
The step of forming first gate oxide and the second gate oxide includes: to the fin column channel region and top
Area carries out third oxidation processes, forms the first gate oxide in the fin column channel region and top region sidewall surfaces；Formation is covered
The graph layer of first gate oxide is covered, the graph layer top surface is lower than the channel region top surface；With the figure
Shape layer is exposure mask, carries out the 4th oxidation processes to the fin column, increases the first gate oxide that the graph layer exposes
Thickness forms the second gate oxide.
Subsequent to form gate structure in 220 top surface of the first separation layer, the gate structure covers the channel
Area B the first gate oxide 231 and the second gate oxide 232；Dielectric layer, the medium are formed on first separation layer 220
Layer covers the gate structure sidewall.
In the present embodiment, the step of forming the gate structure and dielectric layer, is as shown in Figure 16 to Figure 21.
It is subsequently formed 201 top of covering first gate oxide 231, the second gate oxide 232 and the fin column
The dummy gate structure of area C.
The step of in the present embodiment, adjacent dummy gate structure is mutually discrete, then forms the dummy gate structure such as Figure 16 and
Shown in Figure 17.
Figure 16 is please referred to, forms dummy gate layer 242 on first separation layer 220, the dummy gate layer 242 covers institute
State 231 side wall of the first gate oxide and second gate oxide, 232 top and sidewall surfaces.
The dummy gate layer 242 is for being subsequently formed dummy gate structure, to occupy sky for the gate structure being subsequently formed
Between.
In the present embodiment, 242 top surface of dummy gate layer is higher than 201 top surface of fin column.The puppet grid
Pole 242 top surface of layer are higher than 201 top surface of fin column, and the dielectric layer being subsequently formed can be made to be higher than the fin column
201 top surfaces, to enable the dielectric layer as the support for the isolation opening being subsequently formed.In other embodiments,
The dummy gate layer top surface is flush to fin column top surface.
The material of the dummy gate layer 242 is polysilicon.In other embodiments, the material of the dummy gate layer can be
Polycrystalline germanium or polycrystalline silicon germanium.It by etching technics to the removal simple process of semiconductor material, is formed before gate structure, is formed
Pseudo- grid structure can reduce technology difficulty.
The technique for forming the dummy gate layer 242 includes chemical vapor deposition process, physical gas-phase deposition or atom
Layer depositing operation.
It is formed after the dummy gate layer 242, further includes: 242 top surface of dummy gate layer is planarized, is increased
Add the flatness of dummy gate structure top surface.
Figure 17 is please referred to, the dummy gate layer 242 (as shown in figure 16) is performed etching, removes part dummy gate layer 242,
Dummy gate structure 243 is formed, the pseudo- grid structure 243 for covering adjacent fin column 201 is mutually discrete.
Dummy gate structure 243 is used to take up space for the gate structure being subsequently formed.
The step of performing etching to the dummy gate layer 242 includes: that patterned is formed in the dummy gate layer 242
Two mask layers, second mask layer cover 201 top of first gate oxide 231, the second gate oxide 232 and fin column
Dummy gate layer 242；The dummy gate layer 242 is performed etching using second mask layer as exposure mask, removes part dummy grid
Layer 242, forms the dummy gate structure 243；It is formed after the dummy gate structure 243, removes second mask layer.
Second mask material is silicon nitride.
Since the material of the dummy gate layer 242 is semiconductor material, the etching technics of the dummy gate layer 242 is simpler
It is single, so as to simplification of flowsheet.
In the present embodiment, the technique performed etching to the dummy gate layer 242 includes dry etch process.Dry etching work
Skill is controlled with good line width, can accurately control the width of dummy gate structure 243, and can make formed dummy gate structure
The up rightness of 243 side walls is good.
Specifically, the etching gas performed etching to the dummy gate layer 242 includes: SF in the present embodiment6、CF4Or
CF4With O2Combination.
It should be noted that performing etching in the present embodiment to the dummy gate layer 242, dummy gate structure 243 is formed,
The dummy gate structure 243 at adjacent 201 side wall of fin column and top can be made mutually discrete, to make the gate structure being subsequently formed
It is mutually discrete, and then can make can have different current potentials on different gate structures, to realize different function.
In addition, being formed before dielectric layer, dummy gate structure 243 is formed, after can making by the etching of dummy gate structure 243
Continuous gate structure is mutually discrete, so as to reduce the etching technics to the gate structure being subsequently formed.Due to the pseudo- grid
The material of pole structure 243 can be semiconductor material, simpler to the etching technics of semiconductor material, so as to simplify work
Skill.
Figure 18 is please referred to, forms dielectric layer 260 on first separation layer 220, the dielectric layer 260 covers the puppet
243 side wall of gate structure, and expose 243 top surface of dummy gate structure.
The dielectric layer 260 is for realizing the electric isolution between the neighboring gate structures being subsequently formed.
In the present embodiment, the material of the dielectric layer 260 is silica.
In other embodiments, the material of the dielectric layer can also be low k (k is less than 3.9) dielectric material.
In the present embodiment, the step of forming dielectric layer 260 include: formed on first separation layer 220 it is initial
Dielectric layer, the initial medium layer cover 243 side wall of dummy gate structure and top；First is carried out to the initial medium layer
Planarization process forms dielectric layer 260 until exposing 243 top surface of dummy gate structure.
In the present embodiment, the technique for forming initial medium layer includes chemical vapor deposition process.To the beginning dielectric layer into
The technique of the first planarization process of row includes chemical mechanical grinding.
Figure 19 is please referred to, the dummy gate structure 243 (as shown in figure 18) is removed, forms grid in the dielectric layer 260
Pole opening 261.
The gate openings 261 are used for subsequent receiving gate structure 263.
In the present embodiment, the technique for removing the dummy gate structure 243 includes: wet-etching technology.The wet etching
The selectivity of technique is good, small to the damage of first gate oxide 231 and the second gate oxide 232.
In other embodiments, the technique for removing the dummy gate structure includes dry etch process.
Specifically, in the present embodiment, the etching liquid for removing the dummy gate structure 243 includes: the mixed of nitric acid and hydrofluoric acid
Close solution.
Figure 20 is please referred to, forms gate structure layer 262 in the gate openings 261 (as shown in figure 19).
The gate structure layer 262 is for being subsequently formed gate structure.
In the present embodiment, the step of forming gate structure layer 262 includes: in the gate openings 261 and to be given an account of
Initial gate structure sheaf is formed on matter layer 260；Second planarization process is carried out to the initial gate structure sheaf, until described in removal
Initial gate structure sheaf on dielectric layer 260 forms gate structure layer 262.
The technique of second planarization process includes chemical mechanical milling tech.Chemical mechanical milling tech is to metal material
The removal simple process of material, so as to reduce technology difficulty.
The initial gate structure sheaf includes: positioned at 261 side wall of gate openings and bottom surface and the medium
The initial high-k dielectric layer of 260 top surface of layer；Cover the grid layer on the initial high-k dielectric layer surface.
The step of forming the initial gate structure sheaf include: on the 261 bottom and side wall surface of gate openings and
260 top surface of dielectric layer forms initial high K medium film；It is formed after the forth day of a lunar month high-k dielectric layer, is opened in the grid
Mouth 261, which neutralizes, forms initial gate layer on the dielectric layers 260.
The gate structure layer includes: the high K medium film positioned at the 261 bottom and side wall surface of gate openings；Covering
The grid layer of the high-k dielectric layer.
The step of removing the initial gate structure sheaf on the dielectric layer 260, forming gate structure layer includes: described in removal
Initial high K medium film on gate structure 263 forms high K medium film；Remove the initial gate layer on the dielectric layer 260, shape
At grid layer.
The material of the high K medium film is HfO2、La2O3、HfSiON、HfAlO2、ZrO2、Al2O3Or HfSiO4。
In the present embodiment, the material of the grid layer is W.In other embodiments, the material of the grid layer be Al,
Cu, Ag, Au, Ni, Ti, WN or WSi.
Figure 21 is please referred to, the top region C gate structure layer 262 (as shown in figure 20) is removed, forms gate structure 263.
Due to the dummy gate structure 243 at adjacent 201 side wall of fin column and top mutually it is discrete, neighboring gates opening 261 it
Between have dielectric layer 260, then the gate structure 263 is discrete, and then makes to have on different gate structures 263 different
Current potential, to realize different function.
In the present embodiment, after the gate structure 263 for removing the top region C, isolation is formed in the dielectric layer 260
Opening.
In the present embodiment, the gate structure includes: the high k positioned at 261 bottom and side wall of channel region B gate openings
Dielectric layer；Cover the grid of the high-k dielectric layer.
The method for forming the gate structure includes: the removal top region C grid layer, forms grid；Remove the top
C high K medium film in area, portion forms high-k dielectric layer.
Since the thickness of the gate structure layer 262 of removal is smaller, so that the technique of the gate structure layer 262 of removal is simpler
It is single.Specifically, removal part of grid pole structure sheaf 262 makes 232 surface of gate structure lower than the fin in the present embodiment
201 top surfaces, and make 232 top surface of gate structure 70 angstroms~90 at a distance from 201 top surface of fin
Angstrom, such as 80 angstroms.Specifically, removal the gate structure layer 262 with a thickness of 430 angstroms~530 angstroms, such as 480 angstroms.
The technique for removing the top region C gate structure layer 262 includes dry etch process.Remove the top region C grid
The etching gas of pole structure sheaf 262 includes fluorine-based or chlorine-based gas.
In the present embodiment, after the gate structure 263 for removing the top region C, further includes: remove the top top region C
First gate oxide 231 in portion and sidewall surfaces.
Remove at the top of the top region C and the first gate oxide 231 of sidewall surfaces for making at the top of the top region C and
Side wall is exposed, to make subsequent to form the second source and drain doping area in the top region C.
It removes at the top of the top region C and the technique of the first gate oxide 231 of sidewall surfaces includes wet-etching technology
Or one or both of dry etch process combination.
Specifically, removing the work at the top of the top region C with the first gate oxide 231 of sidewall surfaces in the present embodiment
Skill includes isotropic dry etch technique.Isotropic dry etch can reduce the corrosion to grid.
Specifically, removing the quarter at the top of the top region C with the first gate oxide 231 of sidewall surfaces in the present embodiment
Losing gas includes: CF4And oxygen, wherein oxygen concentration is about 20%~40%.Oxygen can consume fluorine during the reaction,
Improve the etching selection ratio of the first gate oxide 231 and gate structure 263.
Figure 22 is please referred to, is formed after the gate structure 263, forms the second source in the top region C fin column 201
Doped region 280 is leaked, there are the second Doped ions in second source and drain doping area 280.
In the present embodiment, second source and drain doping area 280 is used to form the source region of semiconductor structure, second source and drain
Doped region 280 is for connecing the second current potential.Second current potential is less than first current potential.
In the present embodiment, formed in the top region C fin column 201 second source and drain doping area 280 technique include from
Sub- injection technology.
In other embodiments, the forming method does not include the steps that forming the second source and drain doping area.The formation side
Method further include: in the top region or top region surface forms the second source and drain doping layer.
The method for forming the second source and drain doping floor includes: the formation source and drain groove in the area of the fin column top；?
The second source and drain doping layer is formed in the source and drain groove；Alternatively, the method for forming the second source and drain doping layer includes: described
At the top of the area of fin column top and surface forms the second source and drain doping floor.The technique for forming the second source and drain doping layer includes extension
Growth technique.
When formed semiconductor structure is NMOS transistor, second Doped ions are N-type ion, such as phosphonium ion
Or arsenic ion；When formed semiconductor structure be PMOS transistor when, second Doped ions be P-type ion, such as boron from
Son or BF2 +Ion.
Figure 23 is please referred to, forms the second separation layer 262, second separation layer in 263 top surface of gate structure
The 262 covering 201 top region C side walls of fin column.
Second separation layer 262 for realizing the gate structure 263 and external circuit electric isolution.
In the present embodiment, the material of second separation layer 262 is silica.In other embodiments, described second every
The material of absciss layer can also be low k dielectric materials.
In the present embodiment, the technique for forming second separation layer 262 includes chemical vapor deposition process.
In the present embodiment, second separation layer 262 is located in the opening of the isolation in the dielectric layer 260, and described second
262 top surface of separation layer is flushed with 260 top surface of dielectric layer.In other embodiments, second separation layer is also
The dielectric layer top surface can be located at.
If the thickness of second separation layer 262 is excessive, it is easy to increase technology difficulty；If second separation layer
262 thickness is too small, is unfavorable for the electric isolution of gate structure 263 Yu external circuit.Second separation layer, 262 top surface with
The difference in height of 201 top surface of fin is 350 angstroms~450 angstroms, such as 400 angstroms.Specifically, in the present embodiment, described
Two separation layers 262 with a thickness of 550 angstroms~650 angstroms.
Please refer to Figure 24, form the first interconnection structure 270 in the dielectric layer 260, first interconnection structure 270 with
The first source and drain doping layer 211 is electrically connected.
First interconnection structure 270 is electrically connected for realizing the first source and drain doping layer 211 and external circuit.
In the present embodiment, the method for forming first interconnection structure 270 includes: that the is formed in the dielectric layer 260
One contact hole, the first contact hole bottom-exposed go out the first source and drain doping layer 211；It is formed in first contact hole
First interconnection structure 270.
It in the present embodiment, is formed in first contact hole before the first interconnection structure 270, further includes: to described
The first source and drain doping layer 211 that one contact hole bottom-exposed goes out carries out the first supplement ion implanting, in first source and drain doping
The first high-doped zone is formed in layer 211.
The injection ion of the first supplement ion implanting is identical as the conduction type of first Doped ions.
The first supplement ion implanting can make the concentration of Doped ions in first high-doped zone higher, to make
It is capable of forming Ohmic contact between first interconnection structure 270 and first high-doped zone, to reduce the first mutually connection
Contact resistance between structure 270 and the first source and drain doping layer 211 improves the performance of formed semiconductor structure.
First interconnection structure 270 includes: the first high-doped zone table gone out positioned at the first contact hole bottom-exposed
First metal layer in face；The first plug in first contact hole, first metal layer are located at described
Between first plug and the first heavily doped layer.
The method that the first interconnection structure 270 is formed in first contact hole includes: in first contact hole bottom
The the first high-doped zone surface exposed forms the first metal layer；It is formed after the first metal layer, described first
The first plug is formed in contact hole.
The method for forming first metal layer includes: to form gold on the first contact hole bottom and side wall surface
Belong to layer；First annealing is carried out to the metal layer, metal layer is reacted with first high-doped zone, forms the first metal
Compound layer；After first annealing, remaining metal layer is removed.
The material of the metal layer is nickel or cobalt.
The forming method further include: the second interconnection structure, second interconnection are formed in second separation layer 262
Structure is electrically connected with second source and drain doping area 280.
The method for forming second interconnection structure includes: that the second contact hole, institute are formed in second separation layer 262
It states the second contact hole bottom-exposed and goes out second source and drain doping area, 280 top surface；Is formed in second contact hole
Two interconnection structures.
Second interconnection structure includes: positioned at the second source and drain doping area 280 that the second contact hole bottom-exposed goes out
Second metal layer on surface；The second plug in second contact hole, second metal layer are located at institute
It states between the second plug and the second source and drain doping area 280.
In the present embodiment, formed before second interconnection structure further include: the second contact hole bottom-exposed is gone out
The second source and drain doping area 280 carry out second supplement ion implanting, in the second source and drain doping area of second contact hole bottom
The second high-doped zone is formed in 280.
The ion and the second Doped ions in second source and drain doping area 280 of the second supplement ion implanting injection
Conduction type it is identical.
Figure 25 to Figure 30 is the structural schematic diagram of each step of the another embodiment of forming method of semiconductor structure of the invention.
The something in common of the present embodiment and a upper embodiment, does not repeat herein, the difference is that:
Figure 25 is please referred to, forms the first source and drain doping area 361 in 201 bottom zone of fin column.
The method for forming the first source and drain doping area 361 includes: to form covering 201 top region of fin column and bottom zone
Barrier layer 301；It is that exposure mask carries out ion implanting to 201 bottom zone of fin column with the barrier layer 301, in the fin column
The first source and drain doping area 361 is formed in 201 bottom zones.
The step of forming barrier layer 301 includes: that the first peeling layer is formed on the substrate 200, first stripping
Absciss layer covers the 201 bottom zone I side wall of fin column；In the first removing layer surface and 201 channel region II of the fin column
Side wall and top region III side wall and top surface form initial resistance layer；Remove first peeling layer and first removing
The initial resistance layer of layer surface forms barrier layer 301.
The material on the barrier layer 301 is polysilicon, amorphous silicon, silicon nitride or polycrystalline germanium.
It in the present embodiment, is formed after first source and drain doping area 361, forms subsequent second source and drain doping area 362.
In other embodiments, during forming the first source and drain doping area, the second source and drain doping area is formed；It is then described
Barrier layer also exposes fin column top area's side wall and top surface.
The method for forming the barrier layer further include: removal first peeling layer and described first removes the first of layer surface
After beginning barrier layer, the initial resistance floor in fin column top area is removed, forms barrier layer.
The method for removing the initial resistance floor in fin column top area includes: to form covering fin column bottom area side
Second peeling layer of the initial resistance of wall and the channel region；Using second peeling layer as exposure mask, to the initial resistance
It performs etching, removes the top region initial resistance layer, form barrier layer.
It is exposure mask to described that the method for forming the first source and drain doping area and the second source and drain doping area, which includes: using the barrier layer,
Fin column carries out ion implanting, forms the second source and drain doping area in fin column top area, and in the bottom of the fin column
The first source and drain doping area is formed in area.
Figure 26 is please referred to, the first conductive structure 311 for connecting the 201 bottom zone I of fin column is formed.
In the present embodiment, first conductive structure 311 is for realizing the 201 bottom zone I of fin column and external circuit
Electrical connection.
It is formed after first source and drain doping area 361, forms first conductive structure 311, the described first conductive knot
Structure 311 is contacted with first source and drain doping area 361.
In the present embodiment, the method for forming first conductive structure 311 includes: in 201 sidewall surfaces of fin column
Form protective layer；Metal is carried out to 200 surface of substrate and 201 top surface of fin column using the protective layer as exposure mask
Change processing, forms the first conductive structure 311.
In the present embodiment, the step of forming the protective layer includes: to carry out at the 5th oxidation to 201 side wall of fin column
Reason forms initial protective layers in 201 side wall of fin column and top surface；Anisotropy quarter is carried out to the initial protective layers
Erosion processing removes the initial protective layers at fin column 201 top and 200 surface of substrate, forms protective layer.
The step of five oxidation processes includes: thermal oxidation technology or moisture-generation process in situ.
In the present embodiment, the material of the protective layer is silica.In other embodiments, the work of the protective layer is formed
Skill includes chemical gas deposition process, atom layer deposition process or physical gas-phase deposition.The material of the protective layer is nitrogen
SiClx, silica or silicon oxynitride.
The step of metalized includes: in 200 surface of substrate, 201 top of the fin column and side wall table
Face and the protective layer form metal layer；Second annealing is carried out to the metal layer, makes the metal layer and institute
It states and is reacted at the top of substrate 200 and fin column 201, form first conductive structure 311 on 200 surface of substrate, and in institute
It states 201 top surface of fin column and forms first conductive structure 311.
In the present embodiment, the material of the metal layer is nickel or cobalt.The material of first conductive structure 311 be nisiloy,
Nickel germanium, nickel cobalt or silicon cobalt.
In other embodiments, do not have the first conductive structure at the top of the fin.Form first conductive structure
Step includes: to form the first initial conduction structure over the substrate, and the first initial conduction structure covers the fin column
Top region, channel region and top region side wall；The first initial conduction structure is performed etching, the top region and channel are removed
The first initial conduction structure in area forms the first conductive structure for covering the bottom zone side wall.
The first initial conduction structure includes: positioned at 201 side wall of fin column and top surface and the substrate
The third metal layer on surface；The first conductive layer positioned at third metal layer surface, the first conductive layer table
Face is higher than 201 top surface of fin column.
The method for removing the first initial conduction structure of the top region and channel region includes: the removal top region and ditch
First conductive layer in road area；Remove the first metal layer of the top region and channel region.
In the present embodiment, the forming method further include: at 311 top of the first conductive structure on 200 surface of substrate
Form the first separation layer 312.
First separation layer, 312 forming step is identical as a upper embodiment, does not repeat herein.
Figure 27 is please referred to, is formed after first separation layer 312, in the 201 channel region II sidewall surfaces of fin column
Form the first gate oxide 321 and the second gate oxide 322, the thickness of first gate oxide 321 and the second gate oxide 322
It spends not identical.
The forming step of first gate oxide 321 and the second gate oxide 322 and upper embodiment something in common exist
This is not repeated them here, the difference is that: it is formed before the gate structure 330, does not have the first grid at the top of the fin column 201
Oxide layer 321.
Figure 28 is please referred to, the gate structure of covering channel region II the first gate oxide 321 and the second gate oxide 322 is formed
330。
In the present embodiment, the gate structure 330 includes: covering first gate oxide of channel region II 321 and second
The gate dielectric layer of gate oxide 322；Cover the grid of the gate dielectric layer.
The gate structure 330 is located at 312 top surface of the first separation layer.
The step of forming gate structure 330 includes: to form the first grid for covering the channel region II and top region III
The initial high-k dielectric layer of oxide layer 321 and the second gate oxide 322；The grid layer for covering the initial high-k dielectric layer is formed,
The grid layer top surface is higher than 201 top surface of fin column；The grid layer and initial high-k dielectric layer are returned
Etching removes the initial high-k dielectric layer of the top region III, forms high-k dielectric layer, and remove the grid of the top region III
Layer forms grid.
The material of the high-k dielectric layer is high K medium material；The material of the grid is metal.
The processing step that the gate structure 330 is formed in the present embodiment is few, can simplify technique.
In addition, the gate structure 330 of adjacent 201 sidewall surfaces of fin column contacts with each other in the present embodiment, formation one is whole
Body can make the grid current potential having the same on adjacent 201 surface of fin column.
In other embodiments, formed after the gate structure, further includes: formed cover the gate structure and
Patterned first graph layer of fin column top area's side wall and top；It is exposure mask to the grid knot using first graph layer
Structure performs etching, and keeps the gate structure of adjacent fin column sidewall surfaces discrete；Or, further includes: in the grid layer and initially
High-k dielectric layer top surface forms patterned second graph layer；Using the second graph layer as exposure mask to the grid layer and
Initial high-k dielectric layer performs etching, and forms initial gate structure, and the initial gate structure of adjacent fin column sidewall surfaces is mutually divided
It is vertical；The initial gate structure is performed etching, the initial gate structure of the top region is removed, forms gate structure.
Figure 29 is please referred to, is formed after the gate structure 330, the second gate oxide of the top region III is removed
322；The second separation layer 340 is formed in 330 top surface of gate structure.
In the present embodiment, 340 top surface of the second separation layer is lower than 201 top surface of fin column；Form institute
After stating the second separation layer 340, the first gate oxide of top region III 321 that second separation layer 340 exposes is removed.
It is formed after second separation layer 340, removes the top region III first that second separation layer 340 exposes
Gate oxide 321.During removing the first gate oxide of top region III 321 that second separation layer 340 exposes,
Second separation layer 340 can protect the gate structure 330, reduce the loss of the gate structure 330.
In other embodiments, it is formed before second separation layer, remove that the gate structure exposes described the
One gate oxide；The second separation layer top surface is lower than, is flush to or is higher than fin column top surface.
In the present embodiment, the minimizing technology of first gate oxide of top region III 321 is identical as a upper embodiment.
With continued reference to Figure 29, the second source and drain doping area 362 is formed in the 201 top region III of fin column.
It in the present embodiment, is formed after second separation layer 340, forms second source and drain doping area 362.
It is formed after second separation layer 340, forms second source and drain doping area 362, can reduced and form the
Damage during two source and drain doping areas 362 to gate structure 330.
In the present embodiment, it is to cover that the method for forming the second source and drain doping area 362, which includes: with second isolation structure 340,
Film carries out ion implanting to the 201 top region III of fin column, forms the second source and drain doping area 362.
In other embodiments, it can also be formed after gate structure before forming second separation layer, form institute
State the second source and drain doping area.
In other embodiments, the forming method, which is not included in the area of the fin column top, forms the second source and drain doping
The step of area.The second separation layer top surface is higher than or is flush to fin column top area；The forming method is also wrapped
It includes: removing fin column top area, form source and drain groove in second separation layer；Is formed in the source and drain groove
Two source and drain doping layers；Alternatively, the forming method includes: at the top of the area of the fin column top and sidewall surfaces form the second source
Leak doped layer.The technique for forming the second source and drain doping layer includes epitaxial growth technology.
The material of second separation layer 340 is silica or low k dielectric materials.
Figure 30 is please referred to, is formed after first source and drain doping area 361, it is formed and 201 top region of fin column
Second conductive structure 350 of III electrical connection.
In the present embodiment, the first conductive structure of second conductive structure 350 and 201 top surface of fin column
311 contacts.
The step of forming the second conductive structure 350 includes: to be formed to cover the fin on second separation layer 340
The third separation layer 341 at portion's column 201 top and side wall；Form the second contact hole in the third separation layer 341, described second
Contact hole bottom-exposed goes out first conductive structure 311 at 201 top of fin column；Second is formed in second contact hole
Conductive structure 350.
In the present embodiment, the material of the third separation layer 341 is silica or low k dielectric materials.
In other embodiments, the second separation layer top surface is higher than the first conductive structure of the fin column top
Surface；The forming method can not form the third separation layer.The step of forming second conductive structure includes: in institute
Formation third contact hole in the second separation layer is stated, the first conductive knot that third contact hole bottom-exposed goes out the fin column top is stated
Structure；The second conductive structure is formed in the third contact hole.Alternatively, the second separation layer top surface is lower than or is flush to
First conductive structure surfaces of the fin column top；Second conductive structure is located at the second separation layer top surface,
Second conductive structure covers fin column top area side wall, and second conductive structure is located at the fin column top
The first conductive structure surfaces.
In other embodiments, the second separation layer top surface is lower than fin column top surface, the fin
Column top surface does not have the first conductive structure.Second conductive structure covering fin column top area's side wall and top table
Face.Second conductive structure includes: the 4th metal layer positioned at second source and drain doping area's side wall and top surface；
Cover the second conductive layer of the 4th metal layer.
The step of forming the second conductive structure includes: to form the 4th in second source and drain doping area's side wall and top surface
Metal layer；The second conductive layer, the second conductive layer covering the 4th metallization are formed on second separation layer
Nitride layer surface.
With continued reference to Figure 24, the embodiment of the present invention also provides a kind of semiconductor structure, comprising: substrate 200, the substrate
There is fin column 201, the fin column 201 includes bottom zone A, channel region B and position on the bottom zone A on 200
Top region C on the channel region B；Positioned at 231 He of the first gate oxide of the 201 channel region B sidewall surfaces of fin column
Second gate oxide 232, second gate oxide 232 are located at 231 top surface of the first gate oxide, the first grid
The thickness of oxide layer 231 and the second gate oxide 232 is not identical；Cover first gate oxide 231 and the second gate oxide
232 gate structure 263.
The semiconductor structure further include: the first separation layer 220 on the substrate 200, first separation layer
The 220 covering 201 bottom zone A of fin column；Positioned at the second separation layer 262 of 263 top surface of gate structure, described
Two separation layers 262 cover the 201 top region C side wall of fin column.
It should be noted that the orientation of the bottom zone A, channel region B and top region C is perpendicular to 200 surface of substrate,
The orientation of the source region of formed semiconductor structure, drain region and grid is perpendicular to 200 surface of substrate, formed semiconductor structure
The area on 200 surface of substrate occupied is smaller, and therefore, the integrated level of formed semiconductor structure is higher.In addition, in the fin
201 channel region B sidewall surfaces of column have the first gate oxide 231 and the second gate oxide 232, first gate oxide 231
Not identical with the thickness of the second gate oxide 232, then the threshold voltage of the semiconductor structure is unlikely to excessively high, and described partly leads
The first gate oxide 231 and the second gate oxide 232 of body structure be not easy it is breakdown, so as to improve formed semiconductor
The performance of structure.
In the present embodiment, the semiconductor structure further include: the first source and drain doping layer positioned at 200 surface of substrate
211, the first source and drain doping layer 211 covers the 201 top region C Surface of fin column.In other embodiments, described partly to lead
Body structure further include: the first source and drain doping in the substrate and in the combination of one or both of fin column bottom area
Area.
In the present embodiment, the semiconductor structure further include: the dielectric layer 260 on first separation layer 220, institute
It states dielectric layer 260 and covers 263 side wall of gate structure；260 top surface of dielectric layer is higher than or is flush to the fin
201 top surface of column；There is isolation opening, the isolation opening bottom-exposed goes out the gate structure in the dielectric layer 260
263 tops；Second separation layer 262 is located in isolation opening.
In other embodiments, the semiconductor structure does not include the dielectric layer.Cover the fin column channel region
The gate structure of first gate oxide and the second gate oxide contacts with each other.
In the present embodiment, the semiconductor structure further include: the second interconnection structure in second isolation structure,
Second interconnection structure is contacted with the 201 top region C of fin column.
In other embodiments, the semiconductor structure does not include second interconnection structure.And second separation layer
Surface is lower than or is flush to the top region top surface.The semiconductor structure further include: be located at second structural top
The second conductive structure, second conductive structure covers fin column top area surface.
In the present embodiment, the semiconductor structure further include: the second source and drain in the 201 top region C of fin column
Doped region.In other embodiments, the semiconductor structure includes: in the area of the fin column top or the area of fin column top
The second source and drain doping layer on surface.
In other embodiments, the second separation layer top surface is lower than fin column top area.The semiconductor
Structure further include: the third separation layer on second separation layer, the third separation layer cover at the top of the top region
And side wall.Alternatively, the semiconductor structure further include: positioned at the second conductive structure of the second separation layer top surface, institute
It states the second conductive structure and covers the top region side wall and top surface.
The semiconductor structure further include: the first source and drain doping layer 211 positioned at 200 surface of substrate, described first
Source and drain doping layer 211 covers the 201 bottom zone A of fin column, and first separation layer 220 covers the first source and drain doping layer
211 top surfaces；The first contact hole in the dielectric layer 260, the first contact hole bottom-exposed go out described first
Source and drain doping layer 211；The first high-doped zone in first contact hole bottom the first source and drain doping layer 211；Positioned at institute
State the first interconnection structure 270 in the first contact hole.
The 200 bottom zone A of substrate is for connecing the first current potential, and the 201 top region C of fin column is for connecing the second current potential；
First current potential is greater than the second current potential, and the thickness of first gate oxide 321 is greater than the thickness of the second gate oxide 322；
Alternatively, second current potential is greater than the first current potential, the thickness of first gate oxide 321 is less than the second gate oxide 322
Thickness.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (20)
1. a kind of forming method of semiconductor structure characterized by comprising
Substrate is provided, there is fin column on the substrate, the fin column includes bottom zone, the channel on the bottom zone
Area and the top region on the channel region；
The first gate oxide and the second gate oxide, second gate oxide are formed in the fin column channel region sidewall surfaces
Positioned at the first gate oxide top surface, the thickness of first gate oxide and the second gate oxide is not identical；
Form the gate structure for covering first gate oxide and the second gate oxide side wall.
2. the forming method of semiconductor structure as described in claim 1, which is characterized in that the substrate bottom zone is for connecing the
One current potential, fin column top area is for connecing the second current potential；First current potential is greater than the second current potential, first gate oxidation
The thickness of layer is greater than the thickness of the second gate oxide；Alternatively, second current potential is greater than the first current potential, first gate oxide
Thickness less than the second gate oxide thickness.
3. the forming method of semiconductor structure as described in claim 1, which is characterized in that the thickness of first gate oxide
It greater than the thickness of second gate oxide, is formed after first gate oxide, forms the second gate oxide；
The method for forming first gate oxide includes: to carry out at the first oxidation to the fin column channel region and top region
Reason forms the first initial gate oxide in the fin column channel region and top region surface；
The the first initial gate oxide of part channel region for removing the top region and contacting with top region forms the first gate oxidation
Layer；
The method for forming second gate oxide includes: to carry out the second oxidation processes to fin column, in the fin column exposed
Surface forms the second gate oxide.
4. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that further include: shape over the substrate
At the first separation layer, first separation layer covers fin column bottom area, and the gate structure is located at first isolation
Layer top surface；The second separation layer is formed in the gate structure top surface, second separation layer covers the fin column
Top region side wall；
The method for the initial gate oxide of part channel region first for removing the top region and contacting with top region includes: described
First separation layer top surface forms sacrificial layer, and the first separation layer top surface is completely covered in the sacrificial layer, and described
The initial gate oxide of sacrificial layer covering part channel region first, the sacrificial layer top surface is lower than table at the top of the channel region
Face, the material of the sacrificial layer be not identical as the material of first separation layer；Using the sacrificial layer as exposure mask, to described first
Initial gate oxide performs etching, and removes the initial gate oxide of first exposed, forms the first gate oxide.
5. the forming method of semiconductor structure as claimed in claim 4, which is characterized in that the material of the sacrificial layer is polycrystalline
Silicon, amorphous silicon, amorphous carbon or organic dielectric material；The material of first separation layer is silica, silicon nitride or low k dielectric
Material.
6. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the technique of first oxidation processes
Including moisture-generation process in situ；The technological parameter of first oxidation processes includes that reaction temperature is 850 DEG C~1050 DEG C；
The technique of second oxidation processes includes moisture-generation process in situ；The technological parameter of second oxidation processes includes
Reaction temperature is 850 DEG C~1050 DEG C.
7. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that the thickness of first gate oxide
It is 35 angstroms~45 angstroms；Second gate oxide with a thickness of 13 angstroms~17 angstroms.
8. the forming method of semiconductor structure as claimed in claim 3, which is characterized in that remove the top region and with top
The method of first initial gate oxide of the part channel region of area's contact includes: to form the initial gate oxide side of covering part first
The protection side wall of wall, the protection side wall top are lower than the channel region top surface；It is exposure mask to institute using the protection side wall
It states the first initial gate oxide to perform etching, removes the first initial gate oxide that is exposed of protection side wall, form the
One gate oxide.
9. the forming method of semiconductor structure as claimed in claim 2, which is characterized in that the thickness of first gate oxide
Less than the thickness of second gate oxide；
The method for forming first gate oxide and the second gate oxide include: to the fin column channel region and top region into
Row third oxidation processes form the first gate oxide in the fin column channel region and top region sidewall surfaces；Form covering institute
The graph layer of the first gate oxide is stated, the graph layer top surface is lower than the channel region top surface；With the graph layer
For exposure mask, the 4th oxidation processes are carried out to the fin column, increase the thickness of the first gate oxide exposed, form second gate
Oxide layer.
10. the forming method of the semiconductor structure as described in claim 3 or 9, which is characterized in that formed the gate structure it
Afterwards, further includes: remove the second gate oxide of the top region.
11. the forming method of semiconductor structure as described in claim 1, which is characterized in that it is formed before the gate structure,
Further include: the first source and drain doping layer is formed in the substrate surface, the first source and drain doping layer covers the fin column bottom
Area's side wall；The gate structure is located at the top of the first source and drain doping layer.
12. the forming method of semiconductor structure as described in claim 1, which is characterized in that it is formed before the gate structure,
Further include: the first conductive structure is formed in the substrate surface, first conductive structure is electrically connected with fin column bottom area；Institute
Gate structure is stated to be located at the top of first conductive structure.
13. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the first gate oxide and the
After two gate oxides, further includes: form dielectric layer over the substrate；The dielectric layer covers the gate structure sidewall；
The method for forming the gate structure and dielectric layer includes: to form covering first gate oxide, the second gate oxide
And the dummy gate structure of fin column top area side wall；Dielectric layer is formed over the substrate, and the dielectric layer covers institute
Dummy gate structure side wall is stated, and exposes the dummy gate structure top surface；The dummy gate structure is removed, in the medium
Gate openings are formed in layer；First grid structure sheaf is formed in the gate openings；Remove the top region first grid knot
Structure layer forms gate structure.
14. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that the number of the fin column is more
A, the gate structure on multiple fin columns surface is mutually discrete；
The method for forming the dummy gate structure includes: to form dummy gate layer over the substrate, and the dummy gate layer covers institute
State fin column channel region side wall and top region side wall and top surface；The dummy gate layer is performed etching, removal part is pseudo-
Grid layer, forms dummy gate structure, and the pseudo- grid structure for covering adjacent fin column is mutually discrete.
15. the forming method of semiconductor structure as claimed in claim 13, which is characterized in that further include: in the substrate table
Face forms the first source and drain doping layer, and the first source and drain doping floor covers fin column bottom area side wall；The gate structure
At the top of the first source and drain doping layer；
It is formed after the gate structure, further includes: the first contact hole, first contact hole bottom are formed in the dielectric layer
Portion exposes the first source and drain doping layer；It is formed after first contact hole, the first contact hole bottom-exposed is gone out
The first source and drain doping layer, carry out first supplement ion implanting, form the first high-doped zone in the first source and drain doping layer；
After the first supplement ion implanting, the first interconnection structure is formed in first contact hole.
16. the forming method of semiconductor structure as described in claim 1, which is characterized in that form the side of the gate structure
Method includes: the formation second grid structure sheaf in the substrate top, and the second grid structure sheaf covers first grid oxygen
Change floor, the second gate oxide and fin column top area side wall；
The second grid structure sheaf is performed etching, the second grid structure sheaf of the top region is removed, forms gate structure.
17. the forming method of semiconductor structure as described in claim 1, which is characterized in that formed before gate structure, also wrapped
It includes: forming the first source and drain doping area in the area of the fin column bottom or in substrate；It is formed after the gate structure, is also wrapped
It includes: ion implanting being carried out to fin column top area, forms the second source and drain doping area in the area of the fin column top；
Alternatively, being formed before the gate structure, further includes: form barrier layer in the fin column channel region sidewall surfaces；With
The barrier layer is that exposure mask carries out ion implanting to the fin column, forms the first source and drain doping in the area of the fin column bottom
Area, and the second source and drain doping area is formed in the area of the fin column top；
Or, further includes: the second separation layer is formed in the gate structure top surface, second separation layer covers the fin
Portion's column top area side wall removes fin column top area, and source and drain groove is formed in second separation layer；In the source and drain
The second source and drain doping layer is formed in groove.
18. a kind of semiconductor structure characterized by comprising
Substrate has fin column on the substrate, and the fin column includes bottom zone, the channel region on the bottom zone with
And the top region on the channel region；
Positioned at the first gate oxide and the second gate oxide of the fin column channel region sidewall surfaces, first gate oxide
It is not identical with the thickness of the second gate oxide；
Cover the gate structure of first gate oxide and the second gate oxide.
19. semiconductor structure as claimed in claim 18, which is characterized in that further include: on the substrate first every
Absciss layer, first separation layer cover fin column bottom area；
Dielectric layer on first separation layer, the dielectric layer cover the gate structure sidewall；The dielectric layer top
Portion surface is higher than or is flush to fin column top surface；There is isolation opening, the isolation open bottom in the dielectric layer
Portion exposes at the top of the gate structure；The second separation layer in the isolation opening, second separation layer are located at institute
Gate structure top surface is stated, and covers fin column top area side wall.
20. semiconductor structure as claimed in claim 19, which is characterized in that further include: positioned at the first of the substrate surface
Source and drain doping layer, the first source and drain doping floor cover fin column bottom area, the first separation layer covering described first
Source and drain doping layer top surface；The first contact hole in the dielectric layer, the first contact hole bottom-exposed go out described
First source and drain doping layer；The first high-doped zone in the first source and drain doping layer of first contact hole bottom；Positioned at described
The first interconnection structure in first contact hole.
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