CN105304489A - Forming method of semiconductor device - Google Patents
Forming method of semiconductor device Download PDFInfo
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- CN105304489A CN105304489A CN201410310706.8A CN201410310706A CN105304489A CN 105304489 A CN105304489 A CN 105304489A CN 201410310706 A CN201410310706 A CN 201410310706A CN 105304489 A CN105304489 A CN 105304489A
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Abstract
The invention discloses a forming method of a semiconductor device. The semiconductor device comprises a substrate, wherein the substrate comprises a peripheral region and a core region; the peripheral region is provided with a peripheral region fin part; the core region is provided with a core region fin part; a peripheral region ion implantation is carried out on the substrate of the peripheral region and the peripheral region fin part to form at least one of a peripheral region threshold voltage ion implantation layer and a peripheral region channel cutoff layer; first peripheral region gate structure material layers are formed in the substrate of the peripheral region and the peripheral region fin part; first core region gate structure material layers are formed on the substrate of the core region and the core region fin part; a core region ion implantation is carried out on the substrate of the core region and the core region fin part to form at least one of a core region threshold voltage ion implantation layer and a core region channel cutoff layer; and etching is respectively carried out on the first core region gate structure material layers and the second core region gate structure material layers to form a first core region gate structure and a second core region gate structure respectively. By the method disclosed by the invention, the performance of the semiconductor device can be improved.
Description
Technical field
The present invention relates to semiconductor applications, particularly relate to the formation method of semiconductor device.
Background technology
The continuous progress of integrated circuit and IC technology, integrated component number on the same chip to have evolved to present millions of from tens initial hundreds ofs.The performance of current IC and complexity are far from can be imagined originally.In order to meet the requirement (that is: being integrated into the number of devices determined in region) of complexity and current densities, minimum characteristic size, namely " the geometry live width " of known device can be more and more less along with the innovation of technology.
Along with constantly the reducing of characteristic size of transistor, the demand for more small-sized transistor strengthens day by day, therefore in transistor technology, has developed fin formula field effect transistor.
With reference to figure 1 ~ Fig. 5, the formation method of the semiconductor device containing fin formula field effect transistor of the prior art is as follows:
In conjunction with reference to figure 1 and Fig. 2, provide Semiconductor substrate, described Semiconductor substrate comprises external zones A and core space B.External zones A for the formation of I/O line circuit, core space B for the formation of core devices, such as, memory etc.External zones A has external zones fin 101, the Semiconductor substrate between external zones fin 101 has highly equal external zones insulating barrier 102.Core space has core space fin 201, and the Semiconductor substrate between core space fin 201 has highly equal core space insulating barrier 202.
With reference to figure 3, ion implantation 104 is carried out to the Semiconductor substrate of the Semiconductor substrate of described external zones A, external zones fin 101 and core space B, core space fin 201, forms external zones threshold voltage ion implanted layer (not shown) and core space threshold voltage ion implanted layer (not shown).
With reference to figure 4, after forming external zones threshold voltage ion implanted layer (not shown) and core space threshold voltage ion implanted layer (not shown).Semiconductor substrate in described external zones and external zones fin 101 form external zones grid oxygen material layer 105 ', the Semiconductor substrate and core space fin 201 of described core space are formed the first core space grid oxygen material layer 205 '.Device in the A of external zones needs withstand high pressures, so the thickness of external zones grid oxygen material layer 105 ' is much larger than the first core space grid oxygen material layer 205 '.The formation method of the first core space grid oxygen material layer 205 ' and external zones grid oxygen material layer 105 ' is thermal oxidation or wet oxidation growth.The temperature of thermal oxidation or wet oxidation growth is at least 800 DEG C, and heating time is 5 ~ 6 hours.Such as, adopt furnace oxidation method, oxidizing temperature is 1000 ~ 1100 DEG C, and oxidization time is 5 ~ 6 hours.
With reference to figure 5, at external zones grid oxygen material layer 105 ' upper formation external zones polysilicon layer 106 ', at the first core space grid oxygen material layer 205 ' upper formation core space polysilicon layer 206 '.External zones polysilicon layer 106 ' and core space polysilicon layer 206 ' are formed in same step.
In conjunction with reference to figure 1 and Fig. 6, etching external zones grid oxygen material layer 105 ' and external zones polysilicon layer 106 ', the external zones polysilicon gate 106 forming external zones grid oxide layer 105 and be positioned on external zones grid oxide layer 105, that is, defines the first external zones grid structure.First external zones grid structure across external zones fin 101, and covers top and the sidewall of external zones fin 101.Etch the first core space grid oxygen material layer 205 ' and core space polysilicon layer 206 ', the core space polysilicon gate 206 forming the first core space grid oxide layer 205 and be positioned on the first core space grid oxide layer 205.That is, the first core space grid structure is defined.First core space grid structure across core space fin 201, and covers top and the sidewall of core space fin 201.
Then, in conjunction with reference to figure 1 and Fig. 6, then around the first external zones grid structure, form external zones side wall 107, around the first core space grid structure, form core space side wall 207.Afterwards, the external zones fin 101 of external zones side wall 107 both sides forms external zones source electrode 108 and external zones drain electrode 109, the core space fin 201 of core space side wall 207 both sides is formed core space source electrode 208 and core space drain electrode 209.Then, in the Semiconductor substrate of external zones, on external zones side wall 107 and the first external zones grid structure, external zones dielectric layer 110 is formed.The height of external zones dielectric layer 110 equals the height of the first outer ring district grid structure.Core space dielectric layer 210 is formed in the Semiconductor substrate of core space, on core space side wall 207 and the first core space grid structure.The height of core space dielectric layer 210 equals the height of the first core space grid structure.
Then, with reference to figure 7, remove external zones polysilicon gate 106 and remove core space polysilicon gate 206.After removing external zones polysilicon gate 106, form external zones gate recess at external zones dielectric layer 110, external zones grid oxide layer 105 is exposed in the bottom of external zones gate recess.After removing core space polysilicon gate 206, form core space gate recess at core space dielectric layer 210, the first core space grid oxide layer 205 is exposed in the bottom of core space gate recess.
Then, in conjunction with reference to figure 6 and Fig. 7, form patterned mask layer 111 at external zones A, cover external zones gate recess and external zones grid oxide layer 105.After forming mask layer, remove the first core space grid oxide layer 205 bottom core space gate recess, core space fin 201 is exposed in the bottom of core space gate recess.Afterwards, patterned mask layer 111 is removed.
Then, with reference to figure 8, the second core space grid oxide layer 211 is formed in the bottom of the core space gate recess of removal first core space grid oxide layer 205.
After forming the second core space grid oxide layer 211, external zones grid oxide layer 105 forms external zones height k grid oxide layer 112.Second core space grid oxide layer 211 is formed core space height k grid oxide layer 212, and the thickness of external zones height k grid oxide layer 112 equals the thickness of core space height k grid oxide layer 212.Therefore, external zones grid oxide layer 105 and the gross thickness of external zones height k grid oxide layer are greater than the gross thickness of the second core space grid oxide layer 211 and core space height k grid oxide layer.
With reference to figure 9, in the external zones gate recess forming external zones height k grid oxide layer, fill full metal level, form external zones metal gates 113, in external zones dielectric layer 110, form the second external zones grid structure.In the core space gate recess forming core space height k grid oxide layer, the full metal level of full filling, forms core space metal gates 213, forms the second core space grid structure in core space dielectric layer 210.
In prior art, the performance of the semiconductor structure adopting said method to be formed is not good.
Summary of the invention
The problem that the present invention solves is that the performance of the semiconductor structure adopting the method for prior art to be formed is not good.
For solving the problem, the invention provides a kind of formation method of semiconductor structure, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises external zones and core space, and described external zones has external zones fin, and described core space has core space fin;
External zones ion implantation is carried out to the Semiconductor substrate of described external zones and external zones fin, forms at least one in external zones threshold voltage ion implanted layer and external zones channel cutoff layer;
After the ion implantation of described external zones, in the Semiconductor substrate of described external zones He on peripheral fin, form the first external zones gate structure material layer, in the Semiconductor substrate of described core space He on core space fin, form the first core space gate structure material layer;
After forming the first external zones gate structure material layer and the first core space gate structure material layer, core space ion implantation is carried out to the Semiconductor substrate of described core space and core space fin, forms at least one in core space threshold voltage ion implanted layer and core space channel cutoff layer;
Etch the first core space gate structure material layer, form the first core space grid structure, described first core space grid structure across described core space fin, and covers top and the sidewall of described core space fin;
Etch the first external zones gate structure material layer, form the first external zones grid structure, described first external zones grid structure across described external zones fin, and covers top and the sidewall of described external zones fin.
Optionally, before carrying out the step of core space ion implantation, also comprise the upper surface leveling of the first core space gate structure material layer after forming the step of the first external zones gate structure material layer and the first core space gate structure material layer.
Optionally, the method for described leveling is cmp.
Optionally, described core space also comprises NMOS area and PMOS area, described core space fin comprises the first core space fin and the second core space fin, described first core space fin is in described NMOS area, described second core space fin is in described PMOS area, and described core space ion implantation comprises:
After first core space ion implantation is carried out to described first core space fin, the second core space ion implantation is carried out to described second core space fin.
Optionally, described NMOS area comprises first area, the 3rd region and the 4th region, the threshold voltage of described first area is greater than the threshold voltage in described 3rd region, the threshold voltage in described 3rd region is greater than described four-range threshold voltage, described first core space fin is in described first area, and described NMOS area also comprises the 3rd core space fin and the 4th core space fin, and described 3rd core space fin is in described 3rd region, described 4th core space fin is in described 4th region
After first core space ion implantation is carried out to described first core space fin, before the second core space ion implantation is carried out to described second core space fin, also comprise the following steps:
3rd core space ion implantation is carried out to described 3rd core space fin, after the 3rd core space ion implantation, the 4th core space ion implantation is carried out to described 4th core space fin.
Optionally, described PMOS area comprises second area, the 5th region and the 6th region, the threshold voltage of described second area is greater than the threshold voltage in described 5th region, the threshold voltage in described 5th region is greater than the threshold voltage in described 6th region, described second core space fin is at described second area, and PMOS area also comprises the 5th core space fin and the 6th core space fin, and described 5th core space fin is in described 5th region, described 6th core space fin is in described 6th region
After second core space ion implantation is carried out to described second core space fin, before the first core space gate structure material layer is etched, also comprise the following steps:
5th core space ion implantation is carried out to described 5th core space fin, after the 5th core space ion implantation, the 6th core space ion implantation is carried out to described 6th core space fin.
Optionally, described first external zones grid structure comprises external zones gate dielectric layer and is positioned at the first external zones grid on the gate dielectric layer of external zones; Described first core space grid structure comprises the first core space gate dielectric layer and is positioned at the first core space grid on the first core space gate dielectric layer.
Optionally, the thickness of described external zones gate dielectric layer is greater than described first core space gate dielectric layer.
Optionally, the material of described first external zones grid is polysilicon or metal, and the material of described first core space grid is polysilicon or metal.
Optionally, when the material of described first core space grid is polysilicon, after forming the first core space grid structure, also comprise the following steps:
In described core space Semiconductor substrate He on described first core space grid structure, form the first core space dielectric layer, described first core space dielectric layer is equal with described first core space grid structure top;
Remove described first core space grid and described first core space gate dielectric layer, in described first core space dielectric layer, form core space gate recess;
The second core space gate dielectric layer is formed at described core space gate recess inner surface or bottom;
The second core space gate dielectric layer in described core space gate recess is filled full metal, form the second core space grid.
Optionally, described second core space gate dielectric layer comprises intermediate layer and core space high-k gate dielectric layer.
Optionally, the formation method in described intermediate layer comprises Ozonation, air oxidation process or Quick Oxidation method.
Optionally, the formation method of described core space high-k dielectric layer is atom deposition method.
Optionally, when the material of described first external zones grid is polysilicon, after forming the first external zones grid structure, also comprise the following steps:
In the Semiconductor substrate of described external zones He on described first external zones grid structure, form the first external zones dielectric layer, described first external zones dielectric layer is equal with described first grid structure top, external zones;
Remove described first external zones grid, in described first external zones dielectric layer, form external zones gate recess, bottom the gate recess of described external zones, expose described external zones gate dielectric layer;
External zones gate dielectric layer in the gate recess of described external zones is filled full metal, form the second external zones grid.
Compared with prior art, technical scheme of the present invention has the following advantages:
After the step of formation first external zones gate structure material layer and the first core space gate structure material layer, again core space ion implantation is carried out to the Semiconductor substrate of core space and core space fin, can avoid the Ion transfer being injected into core space fin to fin.Therefore, the amount of ions be injected in the core space threshold voltage layer of core space fin can not be made greatly to reduce, improve the degree of regulation of the threshold voltage of the semiconductor device of follow-up formation.
Accompanying drawing explanation
Fig. 1 is the perspective view with the Semiconductor substrate of fin of the prior art;
Fig. 2 is the cross-sectional view of Fig. 1 along AA direction;
Fig. 3 ~ Fig. 5 is the cross-sectional view of each step forming semiconductor device along the AA direction in Fig. 1;
Fig. 6 ~ Fig. 9 is the cross-sectional view forming each step of semiconductor structure along the BB direction in Fig. 1 and CC direction;
Figure 10 is the perspective view with the Semiconductor substrate of fin in the specific embodiment of the invention;
Figure 11 ~ Figure 20 is the cross-sectional view of Figure 10 along DD direction;
Figure 21 ~ Figure 25 is the cross-sectional view forming each step of semiconductor structure along the EE direction in Figure 10 and FF direction.
Embodiment
Through finding and analyzing, the reason that the performance of the semiconductor structure adopting the method for prior art to be formed is not good is as follows:
The device size (bulkwidth) of fin formula field effect transistor is very little, especially, and fin top width (topwidth) size and fin bottom width (bottomwidth).In prior art, with reference to figure 3, ion implantation 104 is carried out to the Semiconductor substrate of the Semiconductor substrate of described external zones A, external zones fin 101 and core space B, core space fin 201, carries out in one step.First ion implantation is carried out to core space fin 201, form core space threshold voltage ion implanted layer.When core space fin 201 is for the formation of nmos pass transistor, the ion of injection comprises phosphonium ion, arsenic ion.When core space fin 201 is for the formation of PMOS transistor, the ion of injection comprises boron ion.Then, the Semiconductor substrate and core space fin 201 of core space adopt the method for thermal oxidation or wet oxidation form the first core space grid oxygen material layer 205 '.But, formed in the process of the first core space grid oxygen material layer 205 ' in above-mentioned oxidation technology, amount of ions in core space threshold voltage ion implanted layer can reduce greatly, thus affect the degree of regulation of the threshold voltage of the semiconductor device of follow-up formation, time serious, the adjustment of threshold voltage cannot be carried out to the semiconductor device of follow-up formation.
In prior art, in the process of oxidation formation first core space grid oxide layer 205 ', can a large amount of oxygen compositions be contained, and high temperature, the reaction time is long.The reason that amount of ions in core space threshold voltage ion implanted layer can reduce greatly is: the ion being injected into core space fin 201 can migrate to outside fin in above-mentioned oxidizing process, and concrete reason is as follows:
(1) be injected into ion generation oxidation-enhanced diffusion (OED, OxygenEnhancdDiffusion) of core space fin 201, made ionic transfer to the first core space grid oxygen material layer 205 ' being injected into core space fin 201.Specific as follows:
Oxidation-enhanced diffusion comprises gap digit diffusion and point defect diffusion.
For phosphonium ion and boron ion, first introduce the situation that gap digit diffusion occurs: formed in the process of the first core space grid oxygen material layer 205 ' in the Semiconductor substrate and core space fin 201 of core space, oxygen atom enters as silicon crystal lattice, form silicon dioxide, and destroy original silicon crystal lattice, such as distort, therefore, gap can be produced in the silicon crystal lattice inside by generation first core space grid oxygen material layer 205 ' position.Now, the phosphonium ion or the boron ion that are injected into core space fin 201 position can move into the inner above-mentioned gap produced of silicon crystal lattice rapidly, and can occupy rapidly this interstitial site.Therefore, the ion injecting core space fin 201 there occurs gap digit diffusive migration to the first core space grid oxygen material layer 205 '.
In addition, in the process of above-mentioned thermal oxidation or wet oxidation, when there is distortion in the silicon crystal lattice by generation first core space grid oxygen material layer 205 ' position, also can produce the silicon atom deficient phenomena that certain is a bit located, like this, the phosphonium ion or the boron ion that are injected into core space fin 201 also can move into this disappearance place rapidly, occupy rapidly this position.Therefore, the ion injecting core space fin 201 there occurs point defect diffusion and also can migrate to the first core space grid oxygen material layer 205 '.
(2) be that thermal oxide growth or wet oxidation growth all need hot environment, under above-mentioned hot environment, inject the solid solubility of ion at oxygen much larger than the solid solubility at silicon composition, therefore after above-mentioned thermal oxidative reaction, inject the interface aggregates that ion can be the insulating barrier 202 of silicon dioxide equally to the interface of the first core space grid oxygen material layer 205 ' and material, segregation (Segregation) phenomenon occurs.When segregation phenomena is serious, above-mentioned injection ion can move to the first core space grid oxygen material layer 205 ' inside and insulating barrier 202 inside.Therefore, above-mentioned segregation process also easily makes the ion diffuse being injected into core space fin 201 to core space fin 201.
(3) in prior art, if when adopting wet oxidation growth technique to form the first core space grid oxygen material layer 205 ', the reacting gas of wet oxidation process comprises oxygen and hydrogen, and therefore, the injection ion being infused in core space fin 201 also can react with the hydrogen of reacting gas.The boron ion being such as infused in core space fin 201 can be combined with hydrogen ion and generate borine (BH
3), the phosphonium ion being infused in core space fin 201 also can be combined with hydrogen ion and generate phosphine (PH
3), thus make injection Ion transfer to the first core space grid oxygen material layer 205 ' being injected into core space fin 201.
Therefore, formed in the process of the first core space grid oxygen material layer 205 ' adopting the technique of thermal oxidation or wet oxidation growth, the quantity being injected into the threshold voltage ion of core space fin 201 can reduce greatly, thus affect the degree of regulation of the threshold voltage of the semiconductor device of follow-up formation, time serious, the adjustment of threshold voltage cannot be carried out to the semiconductor device of follow-up formation.
It should be noted that, in planar transistor, after Semiconductor substrate being carried out to the step of ion implantation formation threshold voltage ion implanted layer, form fleet plough groove isolation structure (STI) in the semiconductor substrate, the technique of then carrying out thermal oxidation or wet oxidation on a semiconductor substrate forms grid oxide layer.Being formed in the technical process of fleet plough groove isolation structure or grid oxide layer, also can there is above-mentioned several migration and diffusion in the injection ion in threshold voltage ion implanted layer.Therefore, the injection ion in threshold voltage ion implanted layer can to the generation migration in the direction of grid oxide layer and fleet plough groove isolation structure and diffusion.But the device size (bulkwidth) in planar transistor is larger, therefore, the amount of ions be injected in Semiconductor substrate is inherently many.Add, above-mentioned threshold voltage ion implanted layer has the larger degree of depth, to such an extent as to the injection ion in threshold voltage ion implanted layer also just spreads in the semiconductor substrate and moves, thus the border of grid oxide layer border or shallow trench oxidation isolation structure cannot be diffused to.
In view of in fin formula field effect transistor, the threshold voltage amount of ions being injected into core space fin 201 can reduce greatly, thus affects the degree of regulation of the threshold voltage of the semiconductor device of follow-up formation.For this reason, the invention provides a kind of formation method of semiconductor structure, adopt the formation method of semiconductor device of the present invention can improve the degree of regulation of the threshold voltage of the semiconductor device of follow-up formation, thus improve the performance of the semiconductor device of follow-up formation.
For enabling above-mentioned purpose of the present invention, feature and advantage more become apparent, and are described in detail specific embodiments of the invention below in conjunction with accompanying drawing.
With reference to Figure 10 and Figure 11, provide Semiconductor substrate, described Semiconductor substrate comprises external zones A and core space B, and described external zones A has external zones fin 301, and described core space B has core space fin 401.Specific as follows:
In the present embodiment, external zones A for the formation of I/O line circuit, core space B for the formation of core devices, such as, memory etc.Semiconductor substrate is silicon substrate.Semiconductor substrate is Semiconductor substrate 300 in the part of external zones A, is Semiconductor substrate 400 in the part of core space B.The formation method of external zones fin 301 is as follows: in Semiconductor substrate 300, form patterned mask layer (not shown), and described patterned mask layer defines fin position, external zones to be formed; With described patterned mask layer for mask etching Semiconductor substrate 300 forms at least one first bulge-structure, then between the first bulge-structure height of formation identical and lower than the external zones insulating barrier 302 of the first bulge-structure, external zones insulating barrier 302 plays the insulating effect between semiconductor device.Described the first projective structure higher than external zones insulating barrier 302 is external zones fin 301.
The formation method of core space fin 401 is as follows: in Semiconductor substrate 400, form patterned mask layer (not shown), and described patterned mask layer defines core space fin position to be formed; With described patterned mask layer for mask etching Semiconductor substrate 400 forms at least one second bulge-structure, then between the second bulge-structure height of formation identical and lower than the core space insulating barrier 402 of the second bulge-structure, core space insulating barrier 402 plays the insulating effect between semiconductor device.Described the second projective structure higher than core space insulating barrier 402 is core space fin 401.
In the present embodiment, external zones fin 301 and core space fin 401 are formed in same step.In other embodiments, external zones fin 301 and core space fin 401 also can not be formed in same step.
In other embodiments, the Semiconductor substrate of external zones and the Semiconductor substrate of core space are all silicon-on-insulator (SOI).Silicon-on-insulator comprises bottom silicon layer, the insulating barrier be positioned on bottom silicon layer, the top silicon layer be positioned on insulating barrier.The described top silicon layer in external zones for the formation of at least one external zones fin, at the top silicon layer of core space for the formation of at least one core space fin.
Then, with reference to Figure 12, external zones ion implantation 303 is carried out to the Semiconductor substrate 300 of described external zones A and external zones fin 301, forms at least one in external zones threshold voltage ion implantation (Vtimplant) layer (not shown) or external zones channel cutoff (channelstopimplant) layer (not shown).In the present embodiment, be described to form external zones threshold voltage ion implantation (Vtimplant) layer, specific as follows:
Core space Semiconductor substrate 400 and core space fin 401 form patterned mask layer 403, and this patterned mask layer 403 exposes Semiconductor substrate 300 and the external zones fin 301 of external zones A.Then, carry out external zones ion implantation 303 to the Semiconductor substrate 300 of external zones A and external zones fin 301, described mask layer 403 prevents external zones ion implantation 303 to be damaged to core space Semiconductor substrate 400 and core space fin 401.
That carries out that external zones ion implantation 303 belongs to those skilled in the art to the Semiconductor substrate 300 of external zones A and external zones fin 301 knows technology, does not repeat them here.
In other embodiments, after external zones ion implantation is carried out to the Semiconductor substrate of described external zones and external zones fin, if formation is channel cutoff layer, then the ion implantation quantity of channel cutoff layer is greater than the injection quantity of threshold voltage ion with the injection degree of depth and injects the degree of depth.
Then, with reference to Figure 13 and Figure 14, after described external zones ion implantation 303, in the Semiconductor substrate of described external zones A He on external zones fin 301, form the first peripheral gates structural material, in the Semiconductor substrate of described core space He on core space fin 401, form the first core space gate structure material layer.
In the present embodiment, the first external zones gate material layers 305 ' that the first peripheral gates structural material comprises external zones gate dielectric material layer 304 ' and is positioned on external zones gate dielectric material layer 304 '.The first core space gate material layers 405 ' that first core space gate structure material layer comprises the first core space gate dielectric material layer 404 ' and is positioned on the first core space gate dielectric material layer.
In the present embodiment, the material of external zones gate dielectric material layer 304 ' and the first core space gate dielectric material layer 404 ' is silica, and formation method is thermal oxidation or wet oxidation growth.Relative to the device of core space B, the device in the A of external zones needs withstand high pressures.So the thickness of external zones gate dielectric material layer 304 ' is greater than the first core space gate dielectric material layer 404 '.Specific as follows:
At external zones Semiconductor substrate 300, external zones insulating barrier 302 with external zones fin 301, in core space Semiconductor substrate 400, core space insulating barrier 402 forms the identical silicon oxide layer of thickness with on core space fin 401 simultaneously, the thickness of this silicon oxide layer equals the thickness of external zones gate dielectric material layer 304 '.Then, adopt patterned mask layer cover the silicon oxide layer of external zones and expose the silicon oxide layer of core space, remove the silicon oxide layer of the core space of segment thickness, the oxide layer of the residual thickness of core space is the first core space gate dielectric material layer 404 '.Then, remove patterned mask layer, the silicon oxide layer of external zones is external zones gate dielectric material layer 304 '.
Then, in external zones gate dielectric material layer 304 ' upper formation first external zones gate material layers 305 '.The first core space gate material layers 405 ' is formed at the first core space gate dielectric material layer 404 '.In the present embodiment, the material of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ' is all polysilicon, the formation method of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ' is all deposit, and is formed in same step.
Then, adopt the method for cmp that the upper surface of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ' is carried out leveling.
Then, with reference to Figure 15 to Figure 20, core space ion implantation is carried out to the Semiconductor substrate of described core space and core space fin, forms at least one in core space threshold voltage ion implanted layer (not shown) or core space channel cutoff layer.
In the present embodiment, core space B comprises NMOS area B1 and PMOS area B2.NMOS area B1 is for the formation of nmos pass transistor, and PMOS area B2 is for the formation of PMOS transistor.
NMOS area B1 comprises first area B11, the 3rd region B12 and the 4th region B13.The transistor of follow-up formation on the B11 of first area is N-type high threshold voltage MOS transistor (NMOSHighVt, NHVT), on 3rd region B12, the transistor of follow-up formation is N-type standard threshold voltage MOS transistor (NMOSStandardVt, NSVT), on 4th region B13, the transistor of follow-up formation is N-type low threshold voltage MOS transistor (NMOSLowVt, NLVT).Therefore, on the B11 of first area, the threshold voltage of the transistor of follow-up formation is greater than the threshold voltage of the transistor of follow-up formation on the 3rd region B12, and on the 3rd region B12, the threshold voltage of the transistor of follow-up formation is greater than the threshold voltage of the transistor of follow-up formation on the 4th region B13.
PMOS area B2 comprises second area B21, the 5th region B22 and the 6th region B23.The transistor of follow-up formation on second area B21 is P type high threshold voltage MOS transistor (PMOSHighVt, PHVT), on 5th region B22, the transistor of follow-up formation is P type standard threshold voltage MOS transistor (PMOSStandardVt, PSVT), on 6th region B23, the transistor of follow-up formation is P type low threshold voltage MOS transistor (PMOSLowVt, PLVT).On second area B21, the threshold voltage of the transistor of follow-up formation is greater than the threshold voltage of the transistor of follow-up formation on the 5th region B22, and on the 5th region B22, the threshold voltage of the transistor of follow-up formation is greater than the threshold voltage of the transistor of follow-up formation on the 6th region B23.
Core space fin 401 comprises the first core space fin, the second core space fin, the 3rd core space fin, the 4th core space fin, the 5th core space fin and the 6th core space fin.Wherein, the first core space fin is at first area B11, and the 3rd core space fin is at the 3rd region B12, and the 4th core space fin is at the 4th region B13.Second core space fin is at second area B21, and the 5th core space fin is at the 5th region B22, and the 6th core space fin is at the 6th region B23.
In the present embodiment, carry out core space ion implantation to the Semiconductor substrate of described core space and core space fin, the concrete injection process forming core space threshold voltage ion implanted layer is as follows:
First ion implantation is carried out to NMOS area B1, and then ion implantation is carried out to PMOS area B2.
Further, with reference to Figure 15, at the patterned mask layer 306 of upper formation of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', described patterned mask layer 306 exposes first area B11, then the first core space ion implantation 406 is carried out to the B11 being positioned at first area, namely the first core space ion implantation 406 is carried out to the first core space fin, form core space NHVT threshold voltage ion implanted layer.Afterwards, above-mentioned patterned mask layer 306 is removed.
Then, with reference to Figure 16, at the patterned mask layer 307 of upper formation of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', described patterned mask layer 307 exposes the 3rd region B12, then the 3rd core space ion implantation 407 is carried out to the B12 being positioned at the 3rd region, namely the 3rd core space ion implantation 407 is carried out to the 3rd core space fin, form core space NSVT threshold voltage ion implanted layer.Afterwards, above-mentioned patterned mask layer 306 is removed.
Then, with reference to Figure 17, at the patterned mask layer 308 of upper formation of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', described patterned mask layer 308 exposes the 4th region B13, then the 4th core space ion implantation 408 is carried out to being positioned at four-range B13, namely the 4th core space ion implantation 408 is carried out to the 4th core space fin, form core space NLVT threshold voltage ion implanted layer.Afterwards, above-mentioned patterned mask layer 308 is removed.
Then, with reference to Figure 18, at the patterned mask layer 309 of upper formation of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', described patterned mask layer 309 exposes second area B21, then the second core space ion implantation 409 is carried out to the B21 being positioned at second area, namely the second core space ion implantation 409 is carried out to the second core space fin, form core space PHVT threshold voltage ion implanted layer.Afterwards, above-mentioned patterned mask layer 309 is removed.
Then, with reference to Figure 19, at the patterned mask layer 310 of upper formation of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', described patterned mask layer 310 exposes the 5th region B22, then the 5th core space ion implantation 410 is carried out to the B21 being positioned at the 5th region, namely the 5th core space ion implantation 410 is carried out to the 5th core space fin, form core space PSVT threshold voltage ion implanted layer.Afterwards, above-mentioned patterned mask layer 310 is removed.
Then, with reference to Figure 20, at the patterned mask layer 311 of upper formation of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', described patterned mask layer 311 exposes first area B23, then the 6th core space ion implantation 411 is carried out to the B23 being positioned at the 6th region, namely the 6th core space ion implantation 411 is carried out to the 6th core space fin, form core space PLVT threshold voltage ion implanted layer.Afterwards, above-mentioned patterned mask layer 311 is removed.
In the present embodiment, why the Semiconductor substrate of described core space and core space fin are carried out to the core space ion implantation of said sequence, reason is as follows:
From the above-mentioned process to core space ion implantation, carrying out core space ion implantation to the Semiconductor substrate of core space and core space fin needs multiple implantation step just to come.Each implantation step can use mask layer.After each ion implantation step completes, need to remove mask layer, the method removing mask layer is ashing and wet etching.In the process of ashing and wet etching, the upper surface of the first smooth core space gate material layers 405 ' can be roughened.When performing next ion implantation step, the injection track of the upper surface meeting changing section ion of the first coarse core space gate material layers 405 ', the injection track of part ion is offset, thus make that the injection degree of depth of identical transistor is inconsistent, uniform ion is bad, therefore, between identical transistor, threshold voltage mismatch is produced.
For nmos pass transistor, injecting ion is boron ion or indium ion.For PMOS transistor, injecting ion is phosphonium ion or arsenic ion.Further discovery, relative to injection phosphonium ion or arsenic ion, when injecting boron ion or indium ion, the upper surface that the first core space gate material layers 405 ' is coarse can make the injection Locus deviation of boron ion or indium ion larger.Relative to PMOS transistor, the injection degree of depth of identical nmos pass transistor can more inconsistent, uniform ion can be more bad.Therefore, nmos pass transistor to the susceptibility of threshold voltage mismatch higher than the susceptibility of PMOS transistor to threshold voltage mismatch.
In the present embodiment, first ion implantation is carried out to NMOS area B1, and then ion implantation is carried out to PMOS area B2.First ion implantation is carried out to the more sensitive NMOS area B1 of threshold voltage mismatch, the processing step of ashing and wet etching mask layer can be reduced, thus the upper surface roughness of the first core space gate material layers 405 ' in NMOS area B1 can be reduced, thus reduce the skew of ion implantation track, thus reduce the threshold voltage mismatch value between the identical transistor in NMOS area B1.
Further, in NMOS area B1, the transistor lower relative to the threshold voltage of follow-up formation, the implantation dosage that the transistor area higher to the threshold voltage of follow-up formation carries out ion implantation is larger.Therefore, the upper surface of the first coarse core space gate material layers 405 ' injects the change probability of the injection track of ion also comparatively greatly to part, and the injection track generation skew probability injecting ion is also larger.Therefore, the transistor that threshold voltage is higher to the susceptibility of threshold voltage mismatch higher than the lower transistor of threshold voltage to the susceptibility of threshold voltage mismatch.Therefore, in each transistor in NMOS area B1, the susceptibility of threshold voltage mismatch value is sorted as NHVT transistor > NSVT transistor > NLVT transistor.
In the present embodiment, at first the first core space ion implantation 406 is carried out to the first core space fin, form core space NHVT threshold voltage ion implanted layer, can the number of times of maximized minimizing ashing and wet etching mask layer, thus can the skew of maximized reduction ion implantation track, and then the threshold voltage mismatch value between NHVT transistor in maximized reduction first area B11.
Finally the 4th core space ion implantation 408 is carried out to the 4th core space fin, form NLVT threshold voltage ion implanted layer, although before through twice ashing and wet etching masking layer process, but, because NLVT transistor is the most insensitive to threshold voltage mismatch, so, when carrying out the 4th core space ion implantation 408 to the 4th region B13 again after twice ashing and wet etching masking layer process terminate, it is also minimum on the impact of the threshold voltage mismatch between the NLVT transistor in the 4th region B13.
Therefore, in the present embodiment, at first the first core space ion implantation 406 is carried out to first area B11, secondly, 3rd core space ion implantation 407 is carried out to the 3rd region B12, finally, the 4th core space ion implantation 408 is carried out to the 4th region B13, can the skew of maximized reduction ion implantation track, thus can threshold voltage mismatch value between each transistor in maximized reduction NMOS area.
Further, in PMOS area B2, the transistor lower relative to the threshold voltage of follow-up formation, the implantation dosage that the transistor area higher to the threshold voltage of follow-up formation carries out ion implantation is larger.Therefore, the upper surface of the first coarse core space gate material layers 405 ' injects the change probability of the injection track of ion also comparatively greatly to part, and the injection track generation skew probability injecting ion is also larger.Therefore, the transistor that threshold voltage is higher to the susceptibility of threshold voltage mismatch higher than the lower transistor of threshold voltage to the susceptibility of threshold voltage mismatch.Therefore, in each transistor in PMOS area B2, the susceptibility of threshold voltage mismatch value is sorted as PHVT transistor > PSVT transistor > PLVT transistor.
In the present embodiment, at first the second core space ion implantation 409 is carried out to the second core space fin, form PHVT threshold voltage ion implanted layer, can the number of times of maximized minimizing ashing and wet etching mask layer, thus can the skew of maximized reduction ion implantation track, and then the threshold voltage mismatch value between PHVT transistor in maximized reduction second area B21.
Finally the 6th core space ion implantation 411 is carried out to the 6th core space fin, form core space PLVT threshold voltage ion implanted layer, although before through repeatedly ashing and wet etching masking layer process, but, because PLVT transistor is the most insensitive to threshold voltage mismatch, so, when repeatedly ashing and wet etching masking layer process carry out the 6th core space ion implantation 411 to the 6th region B23 after terminating again, it is also minimum on the impact of the threshold voltage mismatch between the PLVT transistor in the 6th region B23.
Therefore, in the present embodiment, at first the second core space ion implantation 409 is carried out to second area B21, secondly, 5th core space ion implantation 410 is carried out to the 5th region B22, finally, the 6th core space ion implantation 411 is carried out to the 6th region B23, can the skew of maximized reduction ion implantation track, thus can threshold voltage mismatch value between each transistor in maximized reduction PMOS area.
In other embodiments, core space comprises NMOS area and PMOS area.Described core space fin only includes the first core space fin and the second core space fin, described first core space fin in described NMOS area, for the formation of nmos pass transistor.Described second core space fin in described PMOS area, for the formation of PMOS transistor.Then the step of core space ion implantation is comprised: first the first core space ion implantation is carried out to described first core space fin, afterwards, the second core space ion implantation is carried out to described second core space fin, also belongs to protection scope of the present invention.
In other embodiments; when NMOS area comprises first area; 3rd region and the 4th region; PMOS area comprise second area, the 5th region and the 6th region time; if carry out ion implantation not in accordance with the injection order of above-mentioned specific core space to core space; also protection scope of the present invention is belonged to, the slightly inferior properties of the device of just follow-up formation.
It should be noted that, in the present embodiment, after why leveling being carried out to the upper surface of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', proceed core space ion implantation step again, reason is as follows: carry out leveling to the upper surface of the first core space gate material layers 405 ', to reduce the roughness of the upper surface of the first core space gate material layers 405 '.Thus reduce the change of ion implantation track, ion implantation track is avoided to offset, and then the injection degree of depth of the identical transistor in core space is consistent, to improve the uniformity between identical transistor, reduce the threshold voltage mismatch produced between identical transistor.In other embodiments, if do not carry out leveling to the upper surface of the first external zones gate material layers 305 ' and the first core space gate material layers 405 ', directly carry out the ion implantation step of core space, also belong to protection scope of the present invention.
In other embodiments, only leveling is carried out to the upper surface of the first core space gate material layers 405 ', also belong to protection scope of the present invention.
In other embodiments, core space ion implantation is carried out to the substrate of core space and core space fin and carries out core space channel cutoff layer and also belong to protection scope of the present invention, just need that the degree of depth injected is darker, implantation dosage is larger.
In the present embodiment, after why first forming the step of the first external zones gate structure material layer and the first core space gate structure material layer, carry out core space ion implantation to the Semiconductor substrate of core space and core space fin again, the reason forming core space threshold voltage ion implanted layer is as follows:
First form the first external zones gate structure material layer and the first core space gate structure material layer, afterwards, then core space ion implantation is carried out to the Semiconductor substrate of core space and core space fin.Then, the ion generation oxidation-enhanced diffusion being injected into core space fin 201 can be avoided, produce segregation (Segregation) phenomenon, thus the ion being injected into core space fin 201 can be avoided to migrate to outside fin in above-mentioned oxidizing process.In addition, if the technique forming the first core space gate structure material layer is wet oxidation process, then the ion being injected into core space fin 201 also can be avoided and H-H reaction, thus avoids the ion diffuse making to be injected into core space fin 201 to fin.Therefore, the threshold voltage amount of ions being injected into core space fin 201 can not be made greatly to reduce, thus the degree of regulation of the threshold voltage of the semiconductor device of follow-up formation can be improved.
Then, with reference to Figure 21, etch the first core space gate structure material layer, form the first core space grid structure, the first core space grid structure across core space fin 401, and covers top and the sidewall of described core space fin 401; Etch the first external zones gate structure material layer, form the first external zones grid structure, described first external zones grid structure across described external zones fin 301, and covers top and the sidewall of described external zones fin 301.Specific as follows:
In the present embodiment, the first core space grid 405 that the first core space grid structure comprises the first core space gate dielectric layer 404 and is positioned on the first core space gate dielectric layer 404.The first external zones grid 305 that first external zones grid structure comprises external zones gate dielectric layer 304 and is positioned on external zones gate dielectric layer 304.
Then, continue with reference to Figure 21, around the first core space grid structure, form core space side wall 412, be that the core space fin 401 of mask to core space side wall 412 both sides carries out ion implantation with core space side wall 412, forms core space source electrode 413 and core space drain electrode 414.External zones side wall 312 is formed around first external zones grid structure.Be that the external zones fin 301 of mask to external zones side wall 312 both sides carries out ion implantation with external zones side wall 312, form external zones source electrode 313 and external zones drain electrode 314.
Then continue with reference to Figure 21, in core space Semiconductor substrate, on core space insulating barrier, core space fin 401, first core space grid structure and core space side wall 412, form the first core space dielectric layer 415.The height of the first core space dielectric layer 415 equals the height of the first core space grid structure.The first external zones dielectric layer 315 is formed in the Semiconductor substrate of external zones, on external zones insulating barrier, external zones fin 301, first external zones grid structure and external zones side wall 312.The height of the first external zones dielectric layer equals the height of the first external zones grid structure.In the present embodiment, the first core space dielectric layer 415 and the first external zones dielectric layer 315 are formed in same step, and formation method is deposition.
Then, with reference to Figure 22, remove the first core space grid 405, in the first core space dielectric layer 415, form core space gate recess, the bottom of core space gate recess has the first core space gate dielectric layer 404.Remove the first external zones grid 305, in the first external zones dielectric layer 315, form external zones gate recess, the bottom of external zones gate recess has external zones gate dielectric layer 304.In the present embodiment, the removal of the first core space grid 405 and the first external zones grid 305 is carried out in same step.
Then, in conjunction with reference Figure 21 and Figure 22, the first external zones dielectric layer 315 forms patterned mask layer 316, and patterned mask layer 316 covers external zones gate recess.Then, the first core space gate dielectric layer 404 in core space gate recess is removed.
Through above-mentioned core space ion implantation step, the first core space gate dielectric layer 404 is destroyed, and has not had the effect of the first core space gate dielectric layer.Therefore, need the first core space gate dielectric layer 404 in core space gate recess to remove.
The method removed by the first core space gate dielectric layer 404 in core space gate recess is dry etching or wet etching.Wherein wet etching agent can be hydrofluoric acid solution, also can be the mixed solution of ammoniacal liquor and hydrogen peroxide.
Then, with reference to Figure 23, after removing the first core space gate dielectric layer 404 in core space gate recess, intermediate layer 416 is formed in the core space gate recess of removal first core space gate dielectric layer 404, in the present embodiment, intermediate layer 416 is interface oxide layer (interfaceoxide), in order to alleviate the stress between the core space high-k gate dielectric layer of follow-up formation and core space fin 401.The thickness of interface oxide layer is less than 8 dusts.In the present embodiment, the method forming interface oxide layer comprises Ozonation, air oxidation process or Quick Oxidation method (RTO, RapidThermalOxidation).
Wherein, when the mixed solution of ammoniacal liquor and hydrogen peroxide removes the first core space gate dielectric layer 404, need to adopt Ozonation to form intermediate layer 416, the performance in the intermediate layer 416 of formation is like this better.Specifically comprise: adopt concentration of volume percent to be the soak with ozone solution of 10 ~ 85ppm, soak time is 30 ~ 90s, and soaking temperature is room temperature.
When hydrofluoric acid solution removes the first core space gate dielectric layer 404, need to adopt air oxidation process to form intermediate layer 416, the performance in the intermediate layer 416 formed like this is better.Air oxidation process specifically comprises: static 10 ~ 120min in atmosphere.
Quick Oxidation method specifically comprises: oxidizing temperature is 550 ~ 700 DEG C, and oxidization time is 30 ~ 60min.
It should be noted that, why adopt Ozonation and air oxidation process to form intermediate layer 416, the method of Ozonation and air oxidation process is room temperature, that is, oxidizing temperature is very low, and oxidization time is very short, can not cause the injection ion diffuse being injected into core space fin to fin.
What needs went on to say is, although the temperature of Quick Oxidation method is 550 ~ 700 DEG C, also belong to low-temperature oxidation in the oxidation reaction, and oxidization time is shorter, under such oxidizing temperature and oxidization time, also can not cause the injection ion diffuse being injected into core space fin to fin.After all, the oxidizing temperature of injection ion diffuse to fin being injected into core space fin is made at least to be greater than 800 DEG C.
In the present embodiment, adopt said method to form intermediate layer 416 and only can grow on a semiconductor substrate, therefore, 416, intermediate layer covers the bottom of core space gate recess.It should be noted that, because the thickness of interface oxide layer is too little, thermal oxidation, the technique of wet oxidation or the method for deposition can not be applied and form so thin interface oxide layer.And said method also can make the injection ion being injected into core space spread to silica material, thus greatly can reduce the quantity of the injection ion of core space.
Then, in conjunction with reference to Figure 23 and Figure 24, after forming intermediate layer 416, patterned mask layer 316 is removed.
Then, continue, with reference to Figure 24, intermediate layer 416 to form core space high-k gate dielectric layer 417.External zones gate dielectric layer 304 is formed external zones high-k gate dielectric layer 317.The thickness of external zones high-k gate dielectric layer 317 equals the thickness of core space high-k gate dielectric layer 417.Described external zones high-k gate dielectric layer 317 and core space high-k gate dielectric layer 417 are formed in same step.External zones high-k gate dielectric layer 317 is HfO with the material of core space high-k gate dielectric layer 417
2, Al
2o
3, ZrO
2, HfSiO, HfSiON, HfTaO and HfZrO.External zones high-k gate dielectric layer 317 and core space high-k gate dielectric layer 417 can improve isolates electric effect, reduces leakage current, improves device performance.External zones high-k gate dielectric layer 317 is ald (ALD) with the concrete formation method of core space high-k gate dielectric layer 417.
Wherein, the temperature of Atomic layer deposition method is 450 ~ 550 DEG C, and sedimentation time is 1 ~ 2h.What need again to illustrate be the temperature of Atomic layer deposition method is 450 ~ 550 DEG C, also low-temperature oxidation is belonged to, and oxidization time is shorter, under such oxidizing temperature and oxidization time, also can not cause the injection ion diffuse being injected into core space fin to fin.
It should be noted that, just because of, the external zones high-k gate dielectric layer 317 adopting the method for ald to be formed and core space high-k gate dielectric layer 417, therefore, external zones high-k gate dielectric layer 317, except covering external zones gate dielectric layer 304, also covers the sidewall of external zones gate recess.Core space high-k gate dielectric layer 417, except covering intermediate layer 416, also covers the sidewall of core space gate recess.
Then, continue, with reference to Figure 24, the second core space gate dielectric layer to form the second core space grid 418.External zones gate dielectric layer is formed the second external zones grid 318.In the present embodiment, the material of the second core space grid 418 and the second external zones grid 318 is metal, and is formed in same step.Concrete formation method be those skilled in the art know technology, do not repeat them here.
Now, intermediate layer 416 and core space high-k gate dielectric layer 417 are the second core space gate dielectric layer.The second core space grid 418 on second core space gate dielectric layer and the second core space gate dielectric layer is the second core space grid structure.The second external zones grid 318 on external zones gate dielectric layer and external zones gate dielectric layer is the second external zones grid structure.
Then, with reference to Figure 25, the first core space dielectric layer 415 is formed the second core space dielectric layer 419, the first external zones dielectric layer 315 is formed the second external zones dielectric layer 319.The material of the second core space dielectric layer 419 and the second external zones dielectric layer 319 is all silica, also can be all low k or ultra-low k dielectric layer.The dielectric constant of described low-k materials is less than or equal to 3, and the dielectric constant of described ultralow-k material film is less than or equal to 2.7.The method forming the second core space dielectric layer 419 and the second external zones dielectric layer 319 is all deposition.
In first, second external zones dielectric layer, form external zones source contact connector 320, external zones drain contact connector 321 and external zones gate contact connector 322, drain with external zones source electrode 313, external zones respectively 314 and second external zones grid 318 be electrically connected.In first, second core space dielectric layer, form core space source contact connector 420, core space drain contact connector 421 and core space gate contact connector 422, drain with core space source electrode 413, core space respectively 414 and second core space grid 418 be electrically connected.
It should be noted that: in external zones, why not first in the Semiconductor substrate of external zones He on peripheral fin, form the first peripheral gates structural material, again external zones ion implantation is continued to external zones Semiconductor substrate and external zones fin afterwards, has the following aspects reason:
(1) external zones gate dielectric layer 304 is thick more than the first core space gate dielectric layer 404, cannot be removed by external zones gate dielectric layer 304 in the process of removal first core space gate dielectric layer 404 simultaneously.Reason is as follows: the material of external zones gate dielectric layer 304, first core space gate dielectric layer 404, first external zones dielectric layer 315, first core space dielectric layer 415 is all silicon dioxide.And the formation method of external zones gate dielectric layer 304 is oxidation, the formation method of the first external zones dielectric layer 315 and the first core space dielectric layer 415 is deposition.Therefore, external zones gate dielectric layer 304 to the first external zones dielectric layer 315, first core space dielectric layer 415 is fine and close.Like this, if removed completely by the first core space dielectric layer 415, then the first external zones dielectric layer 315 will certainly be removed a lot, and the first external zones dielectric layer 315 also has the polish stop layer effect of external zones metal gates in subsequent technique.If the first core space dielectric layer 415 is removed, then the first external zones dielectric layer 315 does not have the effect of the polish stop layer of external zones metal gates.
In addition, if removed by external zones gate dielectric layer 304, except thermal oxidation technology, substantially do not have suitable method for oxidation can grow the external zones gate dielectric layer 304 of thickness like this again.And thermal oxidation technology can to being injected into the injection Ion transfer of core space fin to core space fin.
(2) if first form the first peripheral gates structural material in the Semiconductor substrate of external zones He on peripheral fin, again external zones ion implantation is continued to external zones Semiconductor substrate and external zones fin afterwards, external zones gate dielectric material layer 304 ' can be destroyed, thus external zones gate dielectric material layer 304 ' was lost efficacy.The external zones gate dielectric material layer 304 ' lost efficacy carries out the negative effect of diffusion couple device much larger than the injection ion of external zones threshold voltage regions to silica material layer to the negative effect of the device of follow-up formation.
(3) first carry out external zones ion implantation in external zones Semiconductor substrate and external zones fin, afterwards, in the Semiconductor substrate of external zones He on peripheral fin, form the first peripheral gates structural material.Just because of the thickness of the gate dielectric material layer of external zones is large, the desired value of the threshold voltage of external zones is lower.Like this, the injection rate of the injection ion of external zones threshold voltage does not need the desired value that much just can reach external zones threshold voltage.Therefore, even if the injection ion of external zones threshold voltage diffuses to silica material in the process of the gate dielectric material layer forming external zones, also can reach the desired value of external zones threshold voltage easily.
What need again to illustrate is, in the present embodiment, the step of core space ion implantation is carried out after the step of formation first core space gate material layers 405 ', instead of after the step of formation first core space gate dielectric material layer 404 ', and, carry out the step of core space ion implantation before forming the step of the first core space gate material layers 405 '.Reason is as follows: the first core space gate dielectric material layer 404 ' covers core space fin, and, the thickness covering the first core space gate dielectric material layer 404 ' on core space fin is also thinner, therefore, first core space gate dielectric material layer 404 ' can rise and fall by height, smooth not, and the height of highest point and lowest part differs greatly.If directly carry out core space ion implantation to the first core space gate dielectric material layer 404 ', owing to injecting interface out-of-flatness, then the degree of depth of the ion implantation in the core space threshold voltage district of follow-up formation can not be identical.
On the first core space gate dielectric material layer 404 ', the thickness of formation first core space gate material layers 405 ', the first core space gate material layers 405 ' is much larger than the first core space gate dielectric material layer 404 '.Even if do not carry out leveling to the upper surface of the first core space gate material layers 405 ', the top of the first core space gate material layers 405 ' is also than the upper flat of the first core space gate dielectric material layer 404 ', therefore, then the degree of depth of the ion implantation in the core space threshold voltage district of follow-up formation can be substantially identical.
Although the present invention discloses as above, the present invention is not defined in this.Any those skilled in the art, without departing from the spirit and scope of the present invention, all can make various changes or modifications, and therefore protection scope of the present invention should be as the criterion with claim limited range.
Claims (14)
1. a formation method for semiconductor device, is characterized in that, comprising:
There is provided Semiconductor substrate, described Semiconductor substrate comprises external zones and core space, and described external zones has external zones fin, and described core space has core space fin;
External zones ion implantation is carried out to the Semiconductor substrate of described external zones and external zones fin, forms at least one in external zones threshold voltage ion implanted layer and external zones channel cutoff layer;
After the ion implantation of described external zones, in the Semiconductor substrate of described external zones He on peripheral fin, form the first external zones gate structure material layer, in the Semiconductor substrate of described core space He on core space fin, form the first core space gate structure material layer;
After forming the first external zones gate structure material layer and the first core space gate structure material layer, core space ion implantation is carried out to the Semiconductor substrate of described core space and core space fin, forms at least one in core space threshold voltage ion implanted layer and core space channel cutoff layer;
Etch the first core space gate structure material layer, form the first core space grid structure, described first core space grid structure across described core space fin, and covers top and the sidewall of described core space fin;
Etch the first external zones gate structure material layer, form the first external zones grid structure, described first external zones grid structure across described external zones fin, and covers top and the sidewall of described external zones fin.
2. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, before carrying out the step of core space ion implantation, also to comprise the upper surface leveling of the first core space gate structure material layer after forming the step of the first external zones gate structure material layer and the first core space gate structure material layer.
3. the formation method of semiconductor device as claimed in claim 2, it is characterized in that, the method for described leveling is cmp.
4. the formation method of semiconductor device as claimed in claim 1, it is characterized in that, described core space also comprises NMOS area and PMOS area, described core space fin comprises the first core space fin and the second core space fin, described first core space fin is in described NMOS area, described second core space fin is in described PMOS area, and described core space ion implantation comprises:
After first core space ion implantation is carried out to described first core space fin, the second core space ion implantation is carried out to described second core space fin.
5. the formation method of semiconductor device as claimed in claim 4, it is characterized in that, described NMOS area comprises first area, 3rd region and the 4th region, the threshold voltage of described first area is greater than the threshold voltage in described 3rd region, the threshold voltage in described 3rd region is greater than described four-range threshold voltage, described first core space fin is in described first area, described NMOS area also comprises the 3rd core space fin and the 4th core space fin, described 3rd core space fin is in described 3rd region, described 4th core space fin is in described 4th region,
After first core space ion implantation is carried out to described first core space fin, before the second core space ion implantation is carried out to described second core space fin, also comprise the following steps:
3rd core space ion implantation is carried out to described 3rd core space fin, after the 3rd core space ion implantation, the 4th core space ion implantation is carried out to described 4th core space fin.
6. the formation method of semiconductor device as claimed in claim 4, it is characterized in that, described PMOS area comprises second area, the 5th region and the 6th region, the threshold voltage of described second area is greater than the threshold voltage in described 5th region, the threshold voltage in described 5th region is greater than the threshold voltage in described 6th region, described second core space fin is at described second area, PMOS area also comprises the 5th core space fin and the 6th core space fin, described 5th core space fin is in described 5th region, described 6th core space fin is in described 6th region
After second core space ion implantation is carried out to described second core space fin, before the first core space gate structure material layer is etched, also comprise the following steps:
5th core space ion implantation is carried out to described 5th core space fin, after the 5th core space ion implantation, the 6th core space ion implantation is carried out to described 6th core space fin.
7. the formation method of semiconductor device as claimed in claim 1, is characterized in that, described first external zones grid structure comprises external zones gate dielectric layer and is positioned at the first external zones grid on the gate dielectric layer of external zones; Described first core space grid structure comprises the first core space gate dielectric layer and is positioned at the first core space grid on the first core space gate dielectric layer.
8. the formation method of semiconductor device as claimed in claim 7, it is characterized in that, the thickness of described external zones gate dielectric layer is greater than described first core space gate dielectric layer.
9. the formation method of semiconductor device as claimed in claim 5, it is characterized in that, the material of described first external zones grid is polysilicon or metal, and the material of described first core space grid is polysilicon or metal.
10. the formation method of semiconductor device as claimed in claim 9, is characterized in that, when the material of described first core space grid is polysilicon, after forming the first core space grid structure, also comprise the following steps:
In described core space Semiconductor substrate He on described first core space grid structure, form the first core space dielectric layer, described first core space dielectric layer is equal with described first core space grid structure top;
Remove described first core space grid and described first core space gate dielectric layer, in described first core space dielectric layer, form core space gate recess;
The second core space gate dielectric layer is formed at described core space gate recess inner surface or bottom;
The second core space gate dielectric layer in described core space gate recess is filled full metal, form the second core space grid.
The formation method of 11. semiconductor device as claimed in claim 10, is characterized in that, described second core space gate dielectric layer comprises intermediate layer and core space high-k gate dielectric layer.
The formation method of 12. semiconductor device as claimed in claim 11, is characterized in that, the formation method in described intermediate layer comprises Ozonation, air oxidation process or Quick Oxidation method.
The formation method of 13. semiconductor device as claimed in claim 11, is characterized in that, the formation method of described core space high-k dielectric layer is atom deposition method.
The formation method of 14. semiconductor device as claimed in claim 9, is characterized in that, when the material of described first external zones grid is polysilicon, after forming the first external zones grid structure, also comprises the following steps:
In the Semiconductor substrate of described external zones He on described first external zones grid structure, form the first external zones dielectric layer, described first external zones dielectric layer is equal with described first grid structure top, external zones;
Remove described first external zones grid, in described first external zones dielectric layer, form external zones gate recess, bottom the gate recess of described external zones, expose described external zones gate dielectric layer;
External zones gate dielectric layer in the gate recess of described external zones is filled full metal, form the second external zones grid.
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| US20030190786A1 (en) * | 2002-04-08 | 2003-10-09 | Ramsbey Mark T. | Memory manufacturing process with bitline isolation |
| US20060163673A1 (en) * | 2004-06-11 | 2006-07-27 | International Business Machines Corporation | Method and structure for providing tuned leakage current in CMOS integrated circuits |
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| CN103681326A (en) * | 2012-09-05 | 2014-03-26 | 中芯国际集成电路制造(上海)有限公司 | Formation method of fin field-effect transistor (FinFET) substrates with different threshold voltages |
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| CN107799469B (en) * | 2016-09-05 | 2020-03-10 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
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| CN108461544B (en) * | 2017-02-17 | 2019-12-31 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN109962406A (en) * | 2017-12-14 | 2019-07-02 | 中国科学院半导体研究所 | Semiconductor laser and preparation method thereof |
| CN113745112A (en) * | 2020-05-28 | 2021-12-03 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN113745112B (en) * | 2020-05-28 | 2023-08-18 | 中芯国际集成电路制造(上海)有限公司 | Method for forming semiconductor device |
| CN113782442A (en) * | 2021-08-31 | 2021-12-10 | 上海华力集成电路制造有限公司 | Threshold voltage adjusting method of FinFET |
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