CN108461544A

CN108461544A - Semiconductor structure and forming method thereof

Info

Publication number: CN108461544A
Application number: CN201710087343.XA
Authority: CN
Inventors: 李勇; 洪中山
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2017-02-17
Filing date: 2017-02-17
Publication date: 2018-08-28
Anticipated expiration: 2037-02-17
Also published as: CN108461544B

Abstract

A kind of semiconductor structure and forming method thereof, method includes：Substrate and the fin on substrate are provided；Isolation structure is formed on substrate；It is developed across fin and covers the pseudo- grid structure of fin atop part and sidewall surfaces；Side wall is formed on pseudo- grid structure side wall；Form the first medium layer for being formed and being exposed at the top of fin on isolation structure after side wall；After forming first medium layer groove is formed in the fin of pseudo- grid structure both sides；Doped epitaxial layer is formed in groove；Second dielectric layer is formed on first medium layer after forming doped epitaxial layer and first medium layer constitutes interlayer dielectric layer；The pseudo- grid structure of removal, forms opening in interlayer dielectric layer；Metal layer is filled in opening forms metal gate structure.During forming groove in the fin of pseudo- grid structure both sides, first medium layer plays a protective role to isolation structure, avoids occurring below side wall because of gap caused by isolation structure loss, to avoid metal layer from bridging by gap and doped epitaxial layer.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates to the field of semiconductors, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE) phenomenon, so-called short-channel effect (SCE), is easier to occur.

Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processes are gradually starting to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.

However, the electrical performance and yield of the semiconductor devices formed by the prior art are still to be improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which can optimize the electrical performance and yield of a semiconductor device.

To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate; forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers part of the side wall of the fin portion; after the isolation structure is formed, forming a pseudo-gate structure crossing the fin part, wherein the pseudo-gate structure covers part of the top surface and the side wall surface of the fin part; forming a side wall on the side wall of the pseudo gate structure; after the side wall is formed, forming a first dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the first dielectric layer is exposed out of the top of the fin part; after the first dielectric layer is formed, forming grooves in the fin parts on two sides of the pseudo gate structure; forming a doped epitaxial layer in the groove; after the doped epitaxial layer is formed, forming a second dielectric layer on the first dielectric layer exposed out of the pseudo gate structure, wherein the second dielectric layer covers the pseudo gate structure and exposes out of the top of the pseudo gate structure, and the second dielectric layer and the first dielectric layer form an interlayer dielectric layer; removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer; and filling a metal layer in the opening to form a metal gate structure.

Accordingly, the present invention also provides a semiconductor structure comprising: the base comprises a substrate and a discrete fin part positioned on the substrate; the isolation structure is positioned on the substrate exposed out of the fin part and covers partial side walls of the fin part; the metal gate structure stretches across the fin part, covers part of the top surface and the side wall surface of the fin part, and comprises a metal layer; the side wall is positioned on the side wall of the metal grid structure; the doped epitaxial layer is positioned in the fin parts at two sides of the metal grid structure; and the interlayer dielectric layer is positioned on the isolation structure exposed out of the metal grid structure and comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, and the second dielectric layer covers the metal grid structure and exposes out of the top of the metal grid structure.

Compared with the prior art, the technical scheme of the invention has the following advantages:

after the side wall is formed on the side wall of the pseudo gate structure, a first dielectric layer is formed on the isolation structure exposed out of the pseudo gate structure, and the first dielectric layer is exposed out of the top of the fin portion. In the subsequent process of forming grooves in the fin parts on the two sides of the pseudo gate structure, the first dielectric layer plays a role in protecting the isolation structure, so that the isolation structure below the side wall is prevented from being lost in the process of forming the grooves, and gaps generated by loss of the isolation structure below the side wall are prevented; therefore, when the metal layers are filled in the openings in the second dielectric layer and the first dielectric layer subsequently, the problem that the metal layers are bridged with the doped epitaxial layer through the gap does not occur, namely, the doped epitaxial layer and the metal gate structure can be prevented from being bridged through the scheme of the invention, so that the electrical performance and the yield of the semiconductor device are improved.

In an alternative scheme, the second dielectric layer and the first dielectric layer form an interlayer dielectric layer, so that an additional film layer is not required to be introduced to protect the isolation structure through the first dielectric layer, and correspondingly, the additional film layer is not required to be removed after a groove is formed, so that the technical steps can be simplified, and the technical cost can be reduced.

The invention provides a semiconductor structure which comprises an interlayer dielectric layer positioned on an exposed isolation structure of a metal gate structure, wherein the interlayer dielectric layer comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, and the second dielectric layer covers the metal gate structure and exposes the top of the metal gate structure. In the semiconductor manufacturing process, a dummy gate structure crossing a fin part is generally formed, grooves are formed in the fin part on two sides of the dummy gate structure, after a doped epitaxial layer is formed in the grooves, the dummy gate structure is removed, and a metal layer is filled in the position of the dummy gate structure to form the metal gate structure; the first dielectric layer of the semiconductor structure is used for protecting the isolation structure in the process of forming the groove, so that the isolation structure below the side wall is prevented from being subjected to etching loss, and a gap generated by the loss of the isolation structure below the side wall is prevented from occurring.

Drawings

FIGS. 1 and 2 are schematic structural diagrams corresponding to steps in a method of forming a semiconductor structure;

fig. 3 to 24 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

As is known in the art, the electrical performance and yield of semiconductor devices are still to be improved. The reason for this analysis is:

referring to fig. 1 and fig. 2 in combination, a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure is shown, fig. 1 is a perspective view, and fig. 2 is a schematic cross-sectional structural diagram based on fig. 1, where the line is cut along a fin extending direction at an isolation structure position (as indicated by a cut line X1X2 in fig. 1).

Referring to fig. 1, a base is provided, the base including a substrate 10 and a discrete fin portion 11 on the substrate 10; forming an isolation structure 12 on the substrate 10 exposed out of the fin portion 11, wherein the isolation structure 12 covers a part of the sidewall of the fin portion 11; after the isolation structure 12 is formed, forming a dummy gate structure 13 crossing the fin portion 11, wherein the dummy gate structure 13 covers part of the top surface and the side wall surface of the fin portion 11; and forming a side wall 14 on the side wall of the dummy gate structure 13.

Referring to fig. 2 in combination, after the sidewalls 14 are formed, the fin portions 11 (as shown in fig. 1) on both sides of the dummy gate structure 13 are etched, and a groove (not shown) is formed in the fin portion 11; a doped epitaxial layer 15 is formed within the recess.

After the doped epitaxial layer 15 is formed, the following steps further include: forming an interlayer dielectric layer (not shown) on the isolation structure 12 exposed by the dummy gate structure 13; removing the dummy gate structure 13, and forming an opening (not shown) in the interlayer dielectric layer; and filling a metal layer in the opening to form a metal gate structure.

When the fin portions 11 on the two sides of the dummy gate structure 13 are etched to form the groove, the isolation structure 12 is exposed in an etching environment, so that the etching process is prone to cause etching loss to the isolation structure 12 and also prone to cause etching loss to the isolation structure 12 below the sidewall 14 (as shown by a dashed line 50 in fig. 1), thereby causing a gap to be formed below the sidewall 14 (as shown by a dashed line 51 in fig. 2). Therefore, when the opening is filled with the metal layer, the metal layer fills the gap in addition to the opening; therefore, bridging (bridging) between the metal layer and the doped epitaxial layer 15 through the gap is easily caused, that is, bridging between the doped epitaxial layer 15 and the formed metal gate structure is easily caused, and thus the electrical performance and yield of the semiconductor device are reduced.

When the P-type doped epitaxial layer 15 is formed, the etching amount of the fin parts 11 on the two sides of the pseudo gate structure 13 is large, the height of the fin parts 11 protruding out of the isolation structure 12 after the corresponding etching is low, and the P-type doped epitaxial layer 15 is closer to the isolation structure 12; the bridging between the P-type doped epitaxial layer 15 and the metal gate structure is more significant when the substrate 10 is used to form a P-type device.

In order to solve the technical problem, after the side wall is formed on the side wall of the dummy gate structure, a first dielectric layer is formed on the isolation structure exposed out of the dummy gate structure, and the first dielectric layer is exposed out of the top of the fin portion. In the subsequent process of forming grooves in the fin parts on the two sides of the pseudo gate structure, the first dielectric layer plays a role in protecting the isolation structure, so that the isolation structure below the side wall is prevented from being lost in the process of forming the grooves, and gaps generated by loss of the isolation structure below the side wall are prevented; therefore, when the metal layers are filled in the openings in the second dielectric layer and the first dielectric layer subsequently, the problem that the metal layers are bridged with the doped epitaxial layer through the gap does not occur, namely, the doped epitaxial layer and the metal gate structure can be prevented from being bridged through the scheme of the invention, so that the electrical performance and the yield of the semiconductor device are improved.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.

Referring to fig. 3, fig. 3 is a perspective view (only two fins are shown) providing a base (not labeled) comprising a substrate 100 and discrete fins 110 on the substrate 100.

The substrate is used for forming a fin field effect transistor, the substrate 100 provides a process platform for forming the fin field effect transistor, and the fin portion is used for providing a channel of the formed fin field effect transistor. In this embodiment, taking the formed finfet as a CMOS device as an example, the substrate 100 is used to form a P-type device. In other embodiments, the substrate is used to form an N-type device; alternatively, the substrate is used to form a P-type device and an N-type device.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate can also be germanium, silicon carbide, gallium arsenide, or indium gallium, and the substrate can also be a silicon-on-insulator substrate, a germanium-on-insulator substrate, or a glass substrate. The material of the substrate 100 may be selected to be suitable for process requirements or easy integration.

The material of the fin 110 is the same as the material of the substrate 100. In this embodiment, the fin 110 is made of silicon. In other embodiments, the material of the fin may also be germanium, silicon carbide, gallium arsenide, or indium gallium arsenide.

Specifically, the steps of forming the substrate 100 and the fin 110 include: providing an initial substrate; forming a patterned fin mask layer 200 on the surface of the initial substrate; and etching the initial substrate by taking the fin mask layer 200 as a mask to form the substrate 100 and the fin 110 on the substrate 100.

In this embodiment, after the substrate 100 and the fin 110 are formed, the fin mask layer 200 on the top of the fin 110 is remained. The fin mask layer 200 is made of silicon nitride, and when a planarization process is performed subsequently, the top surface of the fin mask layer 200 is used for defining a stop position of the planarization process and protecting the top of the fin 110.

Referring to fig. 4, an isolation structure 101 is formed on the substrate 100 where the fin 110 is exposed, and the isolation structure 101 covers a portion of the sidewall of the fin 110.

The isolation structure 101 serves as an isolation structure of a semiconductor device, and is used for isolating adjacent devices and also used for isolating adjacent fins 110. In this embodiment, the isolation structure 101 is made of silicon oxide. In other embodiments, the material of the isolation structure may also be silicon nitride or silicon oxynitride.

Specifically, the step of forming the isolation structure 101 includes: filling an isolation film on the substrate 100 exposed by the fin 110, wherein the top of the isolation film is higher than the top of the fin mask layer 200 (shown in fig. 3); grinding to remove the isolation film higher than the top of the fin mask layer 200; etching back the remaining isolation film with a partial thickness to expose the top and a partial sidewall of the fin 110, thereby forming the isolation structure 101; the fin mask layer 200 is removed.

Referring to fig. 5 to 7 in combination, fig. 5 is a perspective view, fig. 6 is a schematic cross-sectional view of fig. 5 taken along a line cut perpendicular to a fin extending direction (as indicated by a line cut B1B2 in fig. 5), and fig. 7 is a schematic cross-sectional view of fig. 5 taken along a line cut along a fin extending direction (as indicated by a line cut A1a2 in fig. 5), after the isolation structure 101 is formed, a dummy gate structure 120 is formed to cross the fin 110, and the dummy gate structure 120 covers a portion of the top surface and the sidewall surface of the fin 110.

In this embodiment, the metal gate structure is formed by a process of forming a high-k gate dielectric layer and then forming a gate electrode layer (high-k metal gate), and the dummy gate structure 120 occupies a space for forming the metal gate structure subsequently.

The dummy gate structure 120 is a stacked structure, and the dummy gate structure 120 includes a dummy oxide layer 121 and a dummy gate layer 122 on the dummy oxide layer 121. The dummy gate layer 122 is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon, and the dummy oxide layer 121 is made of silicon oxide or silicon oxynitride. In this embodiment, the material of the dummy oxide layer 121 is silicon oxide, and the material of the dummy gate layer 122 is polysilicon. In other embodiments, the dummy gate structure may also be a single-layer structure, and the dummy gate structure includes a dummy gate layer.

Specifically, the step of forming the dummy gate structure 120 includes: forming a dummy oxide layer 121 on the isolation structure 101, wherein the dummy oxide layer 121 spans the fin 110 and covers a top surface and a sidewall surface of the fin 110; forming a dummy gate film on the dummy oxide layer 121; forming a gate mask 210 on the dummy gate film; and patterning the dummy gate film by using the gate mask 210 as a mask to form a dummy gate structure 120 on the isolation structure 101.

It should be noted that after the dummy gate structure 120 is formed, the gate mask 210 on the top of the dummy gate structure 120 is remained. The gate mask 210 is made of silicon nitride, and the gate mask 210 is used for protecting the top of the dummy gate structure 120 in a subsequent process. In other embodiments, the material of the gate mask may also be silicon oxynitride, silicon carbide, or boron nitride.

With reference to fig. 8 to 12, fig. 8 is a schematic cross-sectional structure based on fig. 6, fig. 9 is a schematic cross-sectional structure based on fig. 7, fig. 10 is a schematic cross-sectional structure based on fig. 8, fig. 11 is a schematic cross-sectional structure based on fig. 9, and fig. 12 is a schematic cross-sectional structure of a cut line perpendicular to the fin extending direction (as indicated by a cut line C1C2 in fig. 5) at the position of a sidewall, and a sidewall 300 (as shown in fig. 11) is formed on the sidewall of the pseudo gate structure 120.

The sidewall spacers 300 are used to define the position of the doped epitaxial layer in the subsequent process. The material of the sidewall 300 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 may be a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 300 has a single-layer structure, and the material of the sidewall spacer 300 is silicon nitride.

Specifically, the step of forming the sidewall spacer 300 includes: forming a sidewall film 125 (shown in fig. 9) conformally covering the dummy gate structure 120; removing the top of the dummy gate structure 120 and the sidewall film 125 on the dummy oxide layer 121, and remaining the sidewall film 125 on the sidewall of the dummy gate structure 120, and using the remaining sidewall film 125 as the sidewall 300.

As shown in fig. 10 and 11, in this embodiment, after the sidewall spacers 300 are formed, the dummy oxide layer 121 exposed by the sidewall spacers 300 is also removed, and the dummy oxide layer 121 covered by the sidewall spacers 300 and the dummy gate layer 122 is remained.

It should be noted that, after the side wall 300 is formed, the forming method further includes: with the spacers 300 as masks, source and drain lightly doped regions (LDD) (not shown) are formed in the fin 110 on both sides of the dummy gate structure 120. In this embodiment, the substrate 100 is used to form a P-type device, and therefore, the doped ions of the source and drain lightly doped regions are P-type ions. In other embodiments, for example, when the substrate is used to form an N-type device, the dopant ions of the source and drain lightly doped regions are N-type ions.

With reference to fig. 13 to 15, fig. 13 is a schematic cross-sectional structure diagram based on fig. 10, fig. 14 is a schematic cross-sectional structure diagram based on fig. 11, and fig. 15 is a schematic cross-sectional structure diagram based on fig. 12, after the sidewalls 300 (shown in fig. 14) are formed, a first dielectric layer 102 (shown in fig. 13) is formed on the isolation structure 101 exposed by the dummy gate structure 120 (shown in fig. 14), and the first dielectric layer 102 exposes the top of the fin 110.

The first dielectric layer 102 is used for protecting the isolation structure 101 in the subsequent process of etching the fins 110 on the two sides of the dummy gate structure 120 to form the groove, so that the isolation structure 101 is prevented from being etched and lost, and gaps generated by the loss of the isolation structure 101 below the side wall 300 are avoided. In addition, the first dielectric layer 102 also serves as a part of an interlayer dielectric layer (ILD) of a subsequently formed semiconductor structure; accordingly, through the first dielectric layer 102, an additional film layer is not required to be introduced to protect the isolation structure 101, and accordingly, the additional film layer is not required to be removed after the fin portion 110 is etched, so that the process steps can be simplified, and the process cost can be reduced.

The first dielectric layer 102 is made of an insulating material, such as a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride. In this embodiment, the first dielectric layer 102 is made of silicon oxide.

It should be noted that the thickness of the first dielectric layer 102 is not too small, nor too large. If the thickness of the first dielectric layer 102 is too small, it is difficult to protect the isolation structure 101 in a subsequent etching process; if the thickness of the first dielectric layer 102 is too large, the subsequent process of etching the fin 110 may be adversely affected. For this reason, in the present embodiment, the thickness of the first dielectric layer 102 is 5nm to 50 nm. That is, the top of the first dielectric layer 102 is lower than the top of the fin 110; alternatively, the top of the first dielectric layer 102 is flush with the top of the fin 110.

In this embodiment, in order to increase the volume of the doped epitaxial layer formed subsequently, the top of the first dielectric layer 102 is lower than the top of the remaining fin 110 after the subsequent etching. Specifically, the step of forming the first dielectric layer 102 includes: forming a dielectric film on the isolation structure 101, wherein the top of the dielectric film is higher than the top of the fin portion 110; and etching back (etch back) the dielectric film with partial thickness, wherein the residual dielectric film is used as the first dielectric layer 102, and the top of the first dielectric layer 102 is lower than the top of the fin portion 110.

The process for back-etching the dielectric film with partial thickness can be a dry etching process, a wet etching process or a process combining wet etching and dry etching. In this embodiment, the process of etching back the dielectric film with a partial thickness is a dry etching process, so that a better anisotropic etching effect can be ensured, and the etching amount can be better controlled.

It should be noted that, in order to form a subsequent doped epitaxial layer, in this embodiment, before forming the first dielectric layer 102 on the isolation structure 101, the forming method further includes: a mask layer 310 is formed on the sidewalls of the fins 110 (as shown in fig. 13). Correspondingly, in the direction along the normal of the surface of the substrate 100, the first dielectric layer 102 covers a portion of the sidewall of the mask layer 310.

The mask layer 310 functions to include: when the fin parts 110 with the thicknesses of the two sides of the dummy gate structure 120 are etched subsequently, the mask layer 310 is used as an etching mask, so that a certain distance is reserved between a subsequently formed groove and the formed source and drain lightly doped region, and the source and drain lightly doped region is prevented from being completely etched and removed; moreover, the mask layer 310 on the sidewall of the fin 110 may protect the sidewall of the fin 110, so as to avoid performing an epitaxial growth process on the sidewall of the fin 110 during a subsequent doped epitaxial layer formation.

Specifically, the step of forming the mask layer 310 includes: forming a mask material (not shown) on the top and sidewalls of the fin 110; the mask material at the groove position on the top of the fin portion is removed, the mask material on the sidewall of the fin portion 110 is remained, and the remaining mask material is used as the mask layer 310. That is, after the mask layer 310 is formed, the top of the mask layer 310 on the sidewalls of the fins 110 is flush with the top of the fins 110.

The process of forming the mask material may be a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process. In this embodiment, the mask material is formed by an atomic layer deposition process. In the step of forming the mask material, the mask material further covers the dummy gate structure 120 and the sidewall 300, and is further located on the isolation structure 101. Therefore, in the step of removing the mask material at the position of the groove on the top of the fin 110, the mask material on the top of the dummy gate structure 120 and the isolation structure 101 is also removed, exposing the gate mask 210 and the isolation structure 101. Correspondingly, the mask layer 310 is also located on the sidewall surface of the sidewall 300.

The material of the mask layer 310 may be silicon nitride (SiN), silicon carbonitride (SiCN), silicon nitride boride (SiBN), silicon oxycarbide (SiOCN), or silicon oxynitride (SiON). The material of the mask layer 310 is different from that of the fin 110, and the material of the mask layer 310 is different from that of the isolation structure 101. In this embodiment, the mask layer 310 is made of silicon nitride.

Referring to fig. 16 and 17 in combination, fig. 16 is a schematic cross-sectional structure view based on fig. 13, and fig. 17 is a schematic cross-sectional structure view based on fig. 14, after the first dielectric layer 102 (shown in fig. 16) is formed, a groove 111 is formed in the fin 110 on both sides of the dummy gate structure 120.

The grooves 111 provide spatial locations for subsequent formation of doped epitaxial layers.

Specifically, the fin portion 110 of the thickness of the two sides of the dummy gate structure 120 is etched by using a dry etching process, and a groove 111 is formed in the fin portion 110.

In this embodiment, the fin portion 110 with a partial thickness is etched by using an anisotropic etching process, where the anisotropic etching process is a reactive ion etching process, and parameters of the reactive ion etching process include: the reaction gas comprises CF₄、SF₆And Ar, CF₄The flow rate is 50sccm to 100sccm, SF₆The flow rate is 10sccm to 100sccm, the flow rate of Ar is 100sccm to 300sccm, the source power is 50W to 1000W, the bias power is 50W to 250W, the chamber pressure is 50mTorr to 200mTorr, and the chamber temperature is 20 ℃ to 90 ℃.

It should be noted that, as shown in fig. 16, in this embodiment, in order to increase the volume of the subsequent doped epitaxial layer formed in the groove 111, the mask layer 310 on the sidewall of the fin 110 is etched while the fin 110 is etched, so that after the groove 111 is formed, the remaining mask layer 310 on the sidewall of the remaining fin 110 is flush with the top of the fin 110.

It should be further noted that, when the fin portion 110 is etched, since the first dielectric layer 102 is formed on the isolation structure 101, the first dielectric layer 102 can protect the isolation structure 101 during the etching process, and therefore the isolation structure 101 is not subjected to etching loss.

In addition, in order to provide a good interface foundation for a subsequent process of forming the doped epitaxial layer to improve the quality of forming the doped epitaxial layer, after forming the grooves 111 in the fins 110 on both sides of the dummy gate structure 120 and before forming the doped epitaxial layer, the forming method further includes: the groove 111 is subjected to a cleaning process. The cleaning process is used to remove both impurities in the recess 111 and a native oxide layer (not shown) on the surface of the fin 110.

The first dielectric layer 102 is exposed in the environment of the cleaning process, and the first dielectric layer 102 is used as a part of a subsequent interlayer dielectric layer, so in order to reduce the loss of the cleaning process to the first dielectric layer 102, in this embodiment, the cleaning process is a SiCoNi process, and the main etching gas adopted by the SiCoNi process is gaseous hydrofluoric acid.

Referring to fig. 18 and 19 in combination, fig. 18 is a schematic cross-sectional view based on fig. 16, and fig. 19 is a schematic cross-sectional view based on fig. 17, wherein a doped epitaxial layer 130 is formed in the recess 111 (shown in fig. 17).

In this embodiment, a selective epitaxy process is adopted, a stress layer is formed in the groove 111, and in the process of forming the stress layer, P-type ions are in-situ self-doped to form the doped epitaxial layer 130. In other embodiments, after a stress layer is formed in the groove, P-type ion doping may be performed on the stress layer to form the doped epitaxial layer.

Specifically, the stress layer is made of Si or SiGe, and the doped epitaxial layer 130 is made of P-type doped Si or SiGe. The stress layer provides a compressive stress effect for the channel region of the P-type device, so that the carrier mobility of the P-type device is improved. In this embodiment, the material of the doped epitaxial layer 130 is SiGe.

In this embodiment, the top of the doped epitaxial layer 130 is higher than the top of the groove 111. And due to the characteristics of the selective epitaxy process, the sidewall surface of the doped epitaxial layer 130 higher than the groove 111 has a top angle protruding in a direction away from the fin 110. In other embodiments, the top of the doped epitaxial layer may also be flush with the top of the recess.

In this embodiment, the substrate is used to form a P-type device. In another embodiment, for example, when the substrate is used for forming an N-type device, in the step of forming a stress layer in the groove, a material of the stress layer is Si or SiC, and the stress layer provides a tensile stress effect for a channel region of the N-type device, so as to improve carrier mobility of the N-type device; in the process of forming the stress layer, in-situ self-doping N-type ions to form the doped epitaxial layer, wherein the doped epitaxial layer is made of N-type doped Si or SiC; for example, the material of the doped epitaxial layer is SiP.

In other embodiments, when the substrate is used to form a P-type device and an N-type device, that is, when the substrate includes an N-type region and a P-type region, taking the doped epitaxial layer formed in the groove as a P-type doped epitaxial layer as an example, after the P-type doped epitaxial layer is formed, the forming method further includes: forming an N-region mask layer on the top and the side wall of the fin part of the N-type region, the top and the side wall of the pseudo-gate structure and the isolation structure, wherein the N-region mask layer is also positioned on the P-type doped epitaxial layer, the top and the side wall of the fin part of the P-type region, the top and the side wall of the pseudo-gate structure of the P-type region and the isolation structure of the P-type region; etching N-region mask layers on the tops of fin parts on two sides of the N-type region pseudo-gate structure, exposing the tops of the fin parts on two sides of the N-type region pseudo-gate structure, etching the fin parts with partial thickness, and forming N-region grooves in the fin parts on two sides of the N-type region pseudo-gate structure; and forming an N-region stress layer in the N-region groove, and in the process of forming the N-region stress layer, self-doping N-type ions in situ to form the N-type doped epitaxial layer. The material of the N-region stress layer is Si or SiC; the material of the N-type doped epitaxial layer is N-type doped Si or SiC.

With reference to fig. 20 and 21, fig. 20 is a schematic cross-sectional structure diagram based on fig. 18, fig. 21 is a schematic cross-sectional structure diagram based on fig. 19, after the doped epitaxial layer 130 is formed, a second dielectric layer 103 (shown in fig. 20) is formed on the first dielectric layer 102 (shown in fig. 20) exposed by the dummy gate structure 120 (shown in fig. 21), the second dielectric layer 103 covers the dummy gate structure 120 and exposes the top of the dummy gate structure 120, and the second dielectric layer 103 and the first dielectric layer 102 form an interlayer dielectric layer (not shown).

In this embodiment, the second dielectric layer 103 and the first dielectric layer 102 are used to form an interlayer dielectric layer (not labeled), and the interlayer dielectric layer is used to realize electrical isolation between semiconductor structures and also to define the size and position of a metal gate structure to be formed subsequently.

Therefore, the material of the second dielectric layer 103 is an insulating material, such as a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like. In this embodiment, in order to improve process compatibility, the material of the second dielectric layer 103 is the same as that of the first dielectric layer 102, that is, the material of the second dielectric layer 103 is silicon oxide.

Specifically, the step of forming the second dielectric layer 103 includes: forming a dielectric material layer on the exposed first dielectric layer 102 of the dummy gate structure 120, wherein the dielectric material layer covers the dummy gate structure 120; and removing the dielectric material layer higher than the top of the dummy gate structure 120 by chemical mechanical polishing and the like to expose the top of the dummy gate structure 120, and taking the residual dielectric material layer as a second dielectric layer 103.

It should be noted that a gate mask 210 is formed on the top of the dummy gate structure 120, so in the step of forming the second dielectric layer 103, the dielectric material layer higher than the top of the gate mask 210 is removed. In this embodiment, after the second dielectric layer 103 is formed, the top of the second dielectric layer 103 is flush with the top of the gate mask 210.

Referring to fig. 22 to 24 in combination, fig. 22 is a schematic cross-sectional view based on fig. 20, fig. 23 is a schematic cross-sectional view based on fig. 21, fig. 24 is a schematic cross-sectional view of a cut line perpendicular to the extending direction of the fin 110 at the position of the sidewall 300 (as indicated by a cut line C1C2 in fig. 5), the dummy gate structure 120 (as shown in fig. 21) is removed, and an opening (not shown) is formed in the interlayer dielectric layer (not shown); the opening is filled with a metal layer 222 (as shown in fig. 23) to form a metal gate junction (not shown).

The metal gate junction is used for controlling the conduction and the disconnection of the formed semiconductor device channel.

In this embodiment, in the step of removing the dummy gate structure 120, the dummy oxide layer 121 and the dummy gate layer 122 are removed, and the opening penetrates through the second dielectric layer 103 (shown in fig. 22) and the first dielectric layer 102 (shown in fig. 22) and exposes the fin 110.

It should be noted that, a gate mask 210 is formed on the top of the dummy gate structure 120, so before removing the dummy gate structure 120, the forming method further includes: the gate mask 210 is removed.

It should be further noted that, after removing the dummy gate structure 120 and before filling the metal layer 222 in the opening, the forming method further includes: a gate dielectric layer (not shown) is formed on the bottom and the sidewall of the opening, and the gate dielectric layer is further located on the top of the second dielectric layer 103. Specifically, the gate dielectric Layer includes an Interfacial Layer (IL) (not shown) and a high-k gate dielectric Layer (not shown) on the surface of the Interfacial Layer.

The interface layer is formed at the bottom of the opening and provides a good interface foundation for forming the high-k gate dielectric layer, so that the quality of the high-k gate dielectric layer is improved, the interface state density between the high-k gate dielectric layer and the fin portion 110 is reduced, and adverse effects caused by direct contact of the high-k gate dielectric layer and the fin portion 110 are avoided. The interface layer is made of silicon oxide or silicon oxynitride.

The high-k gate dielectric layer is made of a gate dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the material of the high-k gate dielectric layer is HfO₂. In other embodiments, the material of the high-k gate dielectric layer may also be HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or ZrO₂Or Al₂O₃。

The step of forming the metal gate junction thus comprises: forming a metal layer 222 on the gate dielectric layer; and removing the metal layer 222 higher than the top of the second dielectric layer 103, and also removing the gate dielectric layer higher than the top of the second dielectric layer 103, wherein the remaining gate dielectric layer and the metal layer 222 in the opening are used for forming the metal gate junction, and the top of the metal gate junction is flush with the top of the second dielectric layer 103.

In this embodiment, in the process of forming the groove 111 (as shown in fig. 17), the first dielectric layer 102 (as shown in fig. 16) protects the isolation structure 101 (as shown in fig. 16), so as to prevent the isolation structure 101 below the sidewall 300 (as shown by a dashed line frame in fig. 24) from being lost in the process of forming the groove 111, thereby preventing a gap from being formed below the sidewall 300 due to the loss of the isolation structure 101; therefore, when the metal layer 222 is filled in the openings in the second dielectric layer 103 and the first dielectric layer 102 (as shown in fig. 23), the problem that the metal layer 222 bridges with the doped epitaxial layer 130 (as shown in fig. 23) through the gap does not occur, that is, by the scheme of the present invention, the doped epitaxial layer 130 can be prevented from bridging with a metal gate structure (not shown), so that the electrical performance and yield of the semiconductor device are improved.

With continued reference to fig. 22-24, fig. 22 is a schematic cross-sectional view taken perpendicular to a line cut in the extending direction of the fin (as indicated by the line cut B1B2 in fig. 5), fig. 23 is a schematic cross-sectional view taken along the line cut in the extending direction of the fin (as indicated by the line cut A1a2 in fig. 5), and fig. 24 is a schematic cross-sectional view taken along the line cut perpendicular to the extending direction of the fin at the location of the sidewall (as indicated by the line cut C1C2 in fig. 5). Accordingly, the present invention also provides a semiconductor structure comprising:

a base comprising a substrate 100 and a discrete fin 110 on the substrate 100; the isolation structure 101 is located on the substrate 100 where the fin portion 110 is exposed, and the isolation structure 101 covers a part of the sidewall of the fin portion 110; a metal gate structure (not labeled) spanning the fin 110, the metal gate structure covering a portion of the top surface and sidewall surfaces of the fin 110, the metal gate structure comprising a metal layer 222 (shown in fig. 23); the side wall 300 is positioned on the side wall of the metal gate structure; a doped epitaxial layer 130 located in the fin 110 at both sides of the metal gate structure; an interlayer dielectric layer (not labeled) located on the isolation structure 101 exposed by the metal gate structure, where the interlayer dielectric layer includes a first dielectric layer 102 (as shown in fig. 22) and a second dielectric layer 103 (as shown in fig. 22) located on the first dielectric layer 102, and the second dielectric layer 103 covers the metal gate structure and exposes the top of the metal gate structure.

The substrate has a finfet, the substrate 100 provides a process platform for forming the finfet, and the fin is used to provide a channel of the finfet. In this embodiment, taking the finfet as a CMOS device as an example, the substrate has a P-type device. In other embodiments, the substrate has an N-type device; alternatively, the substrate has a P-type device and an N-type device.

The metal gate junction is used for controlling the conduction and the disconnection of the semiconductor device channel.

The metal gate structure includes a metal layer 222. In this embodiment, the metal gate structure further includes: a gate dielectric layer (not shown) that spans the fins 110, the gate dielectric layer covering a portion of the top surface and sidewall surfaces of the fins 110. Correspondingly, the metal layer 222 is located on the gate dielectric layer.

Specifically, the gate dielectric Layer includes an Interfacial Layer (IL) (not shown) and a high-k gate dielectric Layer (not shown) on the surface of the Interfacial Layer.

The interface layer provides a good interface foundation for forming the high-k gate dielectric layer, so that the quality of the high-k gate dielectric layer is improved, the interface state density between the high-k gate dielectric layer and the fin portion 110 is reduced, and adverse effects caused by direct contact of the high-k gate dielectric layer and the fin portion 110 are avoided. The interface layer is made of silicon oxide or silicon oxynitride.

The sidewall spacers 300 are used to define the position of the doped epitaxial layer 130. The material of the sidewall 300 may be silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride, silicon oxynitride, boron nitride or boron carbonitride, and the sidewall 300 may be a single-layer structure or a stacked-layer structure. In this embodiment, the sidewall spacer 300 has a single-layer structure, and the material of the sidewall spacer 300 is silicon nitride.

The doped epitaxial layer 130 serves as a source region or a drain region of the semiconductor structure channel. In this embodiment, the forming process of the doped epitaxial layer 130 is a selective epitaxy process, and thus the material of the doped epitaxial layer 130 is P-type doped Si or SiGe. In this embodiment, the material of the doped epitaxial layer 130 is SiGe.

In this embodiment, the top of the doped epitaxial layer 130 is higher than the top of the fin 110. And due to the characteristics of the selective epitaxy process, the sidewall surface of the doped epitaxial layer 130 higher than the top of the fin 110 has a top angle protruding in a direction away from the fin 110. In other embodiments, the top of the doped epitaxial layer may also be flush with the top of the fin.

In this embodiment, the substrate is exemplified to have a P-type device. In another embodiment, when the substrate is provided with an N-type device, the material of the doped epitaxial layer is N-type doped Si or SiC; for example, the material of the doped epitaxial layer is SiP.

It should be further noted that the semiconductor structure further includes: a mask layer 310 on the sidewalls of the fins 110 (as shown in figure 22).

During the semiconductor manufacturing process, a dummy gate structure is generally formed across the fin 110; etching the fin parts 110 with partial thickness at two sides of the pseudo gate structure, and forming grooves in the fin parts 110 at two sides of the pseudo gate structure; forming the doped epitaxial layer 130 in the groove; after the doped epitaxial layer 130 is formed, the dummy gate structure is removed and a metal layer 222 is filled at the position of the dummy gate structure to form the metal gate structure.

The mask layer 310 functions to include: when the fin part 110 with the thickness of the parts at the two sides of the pseudo gate structure is etched, the mask layer 310 is used as an etching mask for etching the fin part 110; the mask layer 310 on the sidewall of the fin 110 may also protect the sidewall of the fin 110, so as to avoid performing an epitaxial growth process on the sidewall of the fin 110 when the doped epitaxial layer 130 is formed. In this embodiment, the mask layer 310 is also located on the surface of the sidewall spacer 300.

The interlayer dielectric layer is used for realizing electrical isolation between the semiconductor structures and also used for defining the size and the position of the metal gate structure. Therefore, the material of the interlayer dielectric layer is an insulating material, such as a dielectric material of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon oxycarbonitride, or the like.

In this embodiment, the first dielectric layer 102 is made of silicon oxide, and in order to improve process compatibility, the second dielectric layer 103 is made of the same material as the first dielectric layer 102, that is, the second dielectric layer 103 is also made of silicon oxide.

According to the foregoing analysis, in the semiconductor manufacturing process, before the doped epitaxial layer 130 is formed, the fin portions 110 at two sides of the dummy gate structure are etched, and a groove is formed in the fin portions 110 at two sides of the dummy gate structure. The first dielectric layer 102 is used for protecting the isolation structure 101 in the process of forming the groove, so that the isolation structure 101 below the sidewall 300 (as shown by a dashed line frame in fig. 24) is prevented from being etched and lost, and a gap caused by the loss of the isolation structure 101 is prevented from occurring below the sidewall 300, so that the problem that the metal layer 222 is bridged with the doped epitaxial layer 130 through the gap can be avoided, the problem that the doped epitaxial layer 130 is bridged with a metal gate structure is correspondingly avoided, and thus the electrical performance and yield of the semiconductor structure are improved. In addition, through the first dielectric layer 102, an additional film layer is not required to be introduced to protect the isolation structure 101, and accordingly, the additional film layer is not required to be removed after the groove is formed, so that the process steps can be simplified, and the process cost can be reduced.

It should be noted that the thickness of the first dielectric layer 102 is not too small, nor too large. If the thickness of the first dielectric layer 102 is too small, it is difficult to protect the isolation structure 101 in the process of etching the fin portion 110; if the thickness of the first dielectric layer 102 is too large, the process for etching the fin 110 may be adversely affected. For this reason, in the present embodiment, the thickness of the first dielectric layer 102 is 5nm to 50 nm.

In this embodiment, the top of the first dielectric layer 102 is lower than the top of the fin 110. In other embodiments, the top of the first dielectric layer may be flush with the top of the fin; alternatively, the top of the first dielectric layer may be higher than the top of the fin portion.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a base, wherein the base comprises a substrate and a discrete fin part positioned on the substrate;

forming an isolation structure on the substrate exposed out of the fin portion, wherein the isolation structure covers part of the side wall of the fin portion;

after the isolation structure is formed, forming a pseudo-gate structure crossing the fin part, wherein the pseudo-gate structure covers part of the top surface and the side wall surface of the fin part;

forming a side wall on the side wall of the pseudo gate structure;

after the side wall is formed, forming a first dielectric layer on the isolation structure exposed out of the pseudo gate structure, wherein the first dielectric layer is exposed out of the top of the fin part;

after the first dielectric layer is formed, forming grooves in the fin parts on two sides of the pseudo gate structure;

forming a doped epitaxial layer in the groove;

after the doped epitaxial layer is formed, forming a second dielectric layer on the first dielectric layer exposed out of the pseudo gate structure, wherein the second dielectric layer covers the pseudo gate structure and exposes out of the top of the pseudo gate structure, and the second dielectric layer and the first dielectric layer form an interlayer dielectric layer;

removing the pseudo gate structure, and forming an opening in the interlayer dielectric layer;

and filling a metal layer in the opening to form a metal gate structure.

2. The method of claim 1, wherein the first dielectric layer is made of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

3. The method of claim 1, wherein a top of the first dielectric layer is lower than a top of the fin; or the top of the first dielectric layer is flush with the top of the fin portion.

4. The method of forming a semiconductor structure of claim 1, wherein the first dielectric layer has a thickness of 5nm to 50 nm.

5. The method of forming a semiconductor structure of claim 1, wherein forming the first dielectric layer comprises: forming a dielectric film on the isolation structure, wherein the top of the dielectric film is higher than the top of the fin part;

and etching back the dielectric film with partial thickness, wherein the residual dielectric film is used as the first dielectric layer, and the top of the first dielectric layer is lower than the top of the fin part.

6. The method for forming a semiconductor structure according to claim 5, wherein the step of etching back the dielectric film with a partial thickness is a dry etching step.

7. The method of claim 1, wherein the step of forming the recess in the fin on both sides of the dummy gate structure comprises: and etching the fin parts with partial thickness at two sides of the pseudo-gate structure by adopting a dry etching process, and forming grooves in the fin parts.

8. The method of claim 7, wherein the dry etching process is a reactive ion etching process, and the parameters of the reactive ion etching process comprise: the reaction gas comprises CF₄、SF₆And Ar, CF₄The gas flow rate of (1) is 50sccm to 100sccm, SF₆The gas flow of the gas is 10sccm to 100sccm, the gas flow of Ar is 100sccm to 300sccm, the source power is 50W to 1000W, the bias power is 50W to 250W, the chamber pressure is 50mTorr to 200mTorr, and the process temperature is 20 ℃ to 90 ℃.

9. The method of forming a semiconductor structure of claim 1, wherein after forming a recess in the fin on both sides of the dummy gate structure, before forming a doped epitaxial layer in the recess, the method further comprises: and carrying out a cleaning process on the groove.

10. The method of claim 9, wherein the cleaning process is a SiCoNi process, and wherein a main etching gas used in the SiCoNi process is gaseous hydrofluoric acid.

11. The method of claim 1, wherein the substrate is used to form a P-type device, and the step of forming a doped epitaxial layer in the recess is performed by using P-type doped Si or SiGe as the material of the doped epitaxial layer;

or,

the substrate is used for forming an N-type device, and in the step of forming the doped epitaxial layer in the groove, the doped epitaxial layer is made of N-type doped Si or SiC.

12. The method for forming a semiconductor structure according to claim 1, wherein after forming the sidewall spacers on the sidewalls of the dummy gate structure, before forming the first dielectric layer on the isolation structure, the method further comprises: forming a mask layer on the side wall of the fin part;

and in the step of forming grooves in the fin parts at two sides of the pseudo-gate structure, etching the fin parts with partial thicknesses at two sides of the pseudo-gate structure by taking the mask layer as a mask.

13. The method of claim 1, wherein the mask layer is made of silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.

14. A semiconductor structure, comprising:

the base comprises a substrate and a discrete fin part positioned on the substrate;

the isolation structure is positioned on the substrate exposed out of the fin part and covers partial side walls of the fin part;

the metal gate structure stretches across the fin part, covers part of the top surface and the side wall surface of the fin part, and comprises a metal layer;

the side wall is positioned on the side wall of the metal grid structure;

the doped epitaxial layer is positioned in the fin parts at two sides of the metal grid structure;

and the interlayer dielectric layer is positioned on the isolation structure exposed out of the metal grid structure and comprises a first dielectric layer and a second dielectric layer positioned on the first dielectric layer, and the second dielectric layer covers the metal grid structure and exposes out of the top of the metal grid structure.

15. The semiconductor structure of claim 14, wherein the first dielectric layer is silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.

16. The semiconductor structure of claim 14, wherein the first dielectric layer has a thickness of 5nm to 50 nm.

17. The semiconductor structure of claim 14, wherein the substrate has a P-type device, and the material of the doped epitaxial layer is P-type doped Si or SiGe;

or,

the substrate is provided with an N-type device, and the material of the doped epitaxial layer is N-type doped Si or SiC.

18. The semiconductor structure of claim 14, wherein the semiconductor structure further comprises: and the mask layer is positioned on the side wall of the fin part.

19. The semiconductor structure of claim 18, wherein the mask layer is made of silicon nitride, silicon carbonitride, silicon boronitride, silicon oxycarbonitride, or silicon oxynitride.