CN111383917B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN111383917B CN111383917B CN201811635977.5A CN201811635977A CN111383917B CN 111383917 B CN111383917 B CN 111383917B CN 201811635977 A CN201811635977 A CN 201811635977A CN 111383917 B CN111383917 B CN 111383917B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: forming a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate and a grid structure crossing the fin part, the grid structure covers part of the top and part of the side wall of the fin part, and a grid mask layer is formed on the top of the grid structure; forming an isolation layer on the substrate exposed out of the fin part, wherein the isolation layer covers part of the side wall of the grid structure; after the isolation layer is formed, removing the grid mask layer with the width of the two side parts of the grid structure; and etching the grid structure exposed by the grid mask layer by taking the residual grid mask layer as a mask and the isolating layer as an etching stop layer to form a beam-shaped grid structure, wherein the beam-shaped grid structure comprises a first part of the grid structure positioned below the grid mask layer and second parts of the grid structure positioned on two sides of the first part of the grid structure and protruding out of the first part of the grid structure. The embodiment of the invention is beneficial to improving the height consistency and the film quality of the second part of the grid structure and can reduce the process difficulty of forming the beam-shaped grid structure.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In Semiconductor manufacturing, with the trend of ultra-large scale integrated circuits, the feature size of the integrated circuit is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is also continuously shortened correspondingly. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so the controllability of the gate structure to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE), which is a so-called short-channel effect, is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
As moore's law continues with the irreversible step of extending forward, beam Gate Structure finfets were developed. Compared with the conventional FinFET, the beam-shaped gate structure FinFET is beneficial to increasing the length of an effective gate structure and improving the control capability of the gate structure on a channel region, and thus is beneficial to increasing the sub-threshold slope (sub-threshold slope), further improving the sub-threshold leakage phenomenon, and reducing the Drain Induced Barrier Lowering (DIBL) effect.
Disclosure of Invention
The embodiment of the invention provides a semiconductor structure and a forming method thereof, and aims to improve the electrical performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate and a grid structure crossing the fin part, the grid structure covers part of the top and part of the side wall of the fin part, and a grid mask layer is formed at the top of the grid structure; forming an isolation layer on the substrate exposed out of the fin part, wherein the isolation layer covers part of the side wall of the grid electrode structure; after the isolation layer is formed, removing the grid mask layer with the width of the two side parts of the grid structure; and etching the grid structure exposed by the grid mask layer by taking the residual grid mask layer as a mask and the isolation layer as an etching stop layer to form a beam-shaped grid structure, wherein the beam-shaped grid structure comprises a first grid structure part positioned below the grid mask layer and second grid structure parts positioned on two sides of the first grid structure part and protruding out of the first grid structure part.
Optionally, in the step of forming the isolation layer on the substrate with the exposed fin portion, the thickness of the isolation layer is
To
Optionally, a mask trimming process is adopted to remove the gate mask layer with the width of the two side portions of the gate structure.
Optionally, a plasma etching process is adopted to remove the gate mask layer with the width of the two side portions of the gate structure.
Optionally, in the step of removing the gate mask layer with the width of the two side portions of the gate structure, the removal width of the gate mask layer on the single side of the gate structure is 1nm to 10nm.
Optionally, in the step of etching the gate structure exposed by the remaining gate mask layer, an etching selection ratio of the process for etching the gate structure to the gate structure and the isolation layer is greater than 100.
Optionally, a plasma etching process is adopted, the remaining gate mask layer is used as a mask, the isolation layer is used as an etching stop layer, and the gate structure exposed by the gate mask layer is etched.
Optionally, the parameters of the plasma etching process are as follows: the etching gas is SF 6 、CF 4 And Cl 2 ，SF 6 The gas flow is 10SCCM to 100SCCM 4 The gas flow is 0SCCM to 200SCCM 2 The gas flow is 0SCCM to 500SCCM 6 、CF 4 And Cl 2 The temperature of the gas is 0 ℃ to 150 ℃, and the process pressure is 1mtorr to 200mtorr.
Optionally, the isolation layer is made of silicon oxide, silicon nitride or a silicon-containing anti-reflection coating.
Optionally, the isolation layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
Optionally, the step of forming the isolation layer includes: forming an isolation film on the substrate exposed out of the fin part, wherein the isolation film covers part of the side wall of the gate structure; planarizing the isolation film; and removing part of the thickness of the isolation film, and keeping the rest of the isolation film as the isolation layer.
Optionally, a plasma etching process is used to remove a portion of the thickness of the isolation film.
Optionally, the gate structure is a dummy gate structure.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: a substrate; the fin part protrudes out of the surface of the substrate; the isolation layer is positioned on the substrate with the exposed fin part; the beam-shaped gate structure comprises a first gate structure part, a second gate structure part and a third gate structure part, wherein the first gate structure part spans the fin part and covers part of the top and part of the side wall of the fin part; and the second part of the grid electrode structure is positioned on two sides of the first part of the grid electrode structure and protrudes out of the first part of the grid electrode structure, the second part of the grid electrode structure covers partial side walls of the fin part, and the top of the second part of the grid electrode structure is flush with the top of the isolation layer.
Optionally, the thickness of the isolation layer is
To is that
Optionally, the isolation layer is made of silicon oxide, silicon nitride, or a silicon-containing anti-reflection coating.
Optionally, the dimension of the second portion of the gate structure protruding beyond the first portion of the gate structure along a direction perpendicular to the side wall of the beam-shaped gate structure is 1nm to 10nm.
Optionally, the beam-shaped gate structure is an integrated structure.
Optionally, the beam-shaped gate structure is a dummy gate structure.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the embodiment of the invention, the rest grid mask layer is used as a mask, the isolation layer is used as an etching stop layer, and the grid structure exposed out of the grid mask layer is etched to form the beam-shaped grid structure, wherein the beam-shaped grid structure comprises a first grid structure part positioned below the grid mask layer and a second grid structure part positioned on two sides of the first grid structure part and protruding out of the first grid structure part. Compared with the scheme that the isolation layer is not formed, the top of the isolation layer can play a role in defining an etching stop position in the process of etching the Gate Structure exposed by the Gate mask layer, so that the height consistency and the film quality of the second part of the Gate Structure are improved, and the process difficulty of forming the beam-shaped Gate Structure is reduced.
And compared with the scheme that the grid structure material layer is etched by directly taking the grid mask layer as a mask, and the grid structure material layer exposed by the grid mask layer is reserved as the second part of the initial grid structure, the grid mask layer with the width of the two side parts of the grid structure is removed after the grid structure is formed, only the grid structure exposed by the residual grid mask layer is etched, the width of the grid structure to be etched is smaller, the process difficulty of forming the beam-shaped grid structure is favorably reduced, the height consistency of the second part of the grid structure is improved, and the electrical performance of the semiconductor structure is further improved.
Drawings
Fig. 1 to 5 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
FIGS. 6-10 are schematic structural diagrams corresponding to steps of a method for forming a semiconductor structure according to an embodiment of the present invention;
FIG. 11 is a schematic structural diagram of a semiconductor structure according to an embodiment of the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Referring to fig. 1 to 5, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1 and fig. 2, a perspective view of a semiconductor structure and a cross-sectional view along aa1 in fig. 1 are respectively illustrated, and a base is provided, where the base includes a substrate 1 and a fin portion 2 protruding from the substrate 1.
Referring to fig. 3, a gate structure material layer 3 is formed across the fin 2, and the gate structure material layer 3 covers the top and sidewalls of the fin 2.
Referring to fig. 4, a gate mask layer 4 is formed on top of the gate structure material layer 3; and etching the gate structure material layer 3 by taking the gate mask layer 4 as a mask, reserving the gate structure material layer 3 with the exposed part of the thickness of the gate mask layer 4, taking the gate structure material layer 3 below the gate mask layer 4 as a first part 5 of a gate structure, and taking the gate structure material layer 3 with the exposed part of the thickness of the gate mask layer 4 as a second part 6 of an initial gate structure.
Referring to fig. 5, a sidewall spacer 7 is formed on the sidewall of the first portion 5 of the gate structure exposed by the second portion 6 of the initial gate structure; after the side walls 7 are formed, the exposed second parts 6 of the initial grid structures of the side walls 7 are removed by taking the side walls 7 as masks, so that second parts 8 of the grid structures are formed, and the first parts 5 of the grid structures and the second parts 8 of the grid structures form beam-shaped grid structures 9.
In the process of etching the gate structure material layer 3 to form the gate structure first part 5 and the initial gate structure second part 6, the etching amount of the gate structure material layer 3 exposed by the gate mask layer 4 is difficult to control, the height consistency and the film quality of the initial gate structure second part 6 are poor, moreover, the area of the gate structure material layer 3 exposed by the gate mask layer 4 is large, the etching uniformity of the gate structure material layer 3 is poor, so that the height consistency of the initial gate structure second part 6 is poor, the process operation difficulty for forming the initial gate structure second part 6 is high, correspondingly, the height consistency and the film quality of the subsequently formed gate structure second part 8 are also poor, and the electrical performance of the formed semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: forming a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate and a grid structure crossing the fin part, the grid structure covers part of the top and part of the side wall of the fin part, and a grid mask layer is formed at the top of the grid structure; forming an isolation layer on the substrate exposed out of the fin part, wherein the isolation layer covers part of the side wall of the grid electrode structure; after the isolation layer is formed, removing the grid mask layer with the width of the two side parts of the grid structure; and etching the grid structure exposed by the grid mask layer by taking the residual grid mask layer as a mask and the isolation layer as an etching stop layer to form a beam-shaped grid structure, wherein the beam-shaped grid structure comprises a first grid structure part positioned below the grid mask layer and second grid structure parts positioned on two sides of the first grid structure part.
In the embodiment of the invention, the rest grid mask layer is used as a mask, the isolation layer is used as an etching stop layer, and the grid structure exposed by the grid mask layer is etched to form the beam-shaped grid structure, wherein the beam-shaped grid structure comprises a first grid structure part positioned below the grid mask layer and second grid structure parts positioned on two sides of the first grid structure part. Compared with the scheme that the isolation layer is not formed, the top of the isolation layer can play a role in defining an etching stop position in the process of etching the gate structure exposed by the gate mask layer, so that the height consistency and the film quality of the second part of the gate structure are improved, and the process difficulty in forming the beam-shaped gate structure is reduced.
In addition, compared with the scheme that the gate structure material layer is etched by directly taking the gate mask layer as a mask and the gate structure material layer exposed out of the gate mask layer is reserved as the second part of the initial gate structure, the gate structure etching method and the semiconductor structure remove the gate mask layer with the width of the two side parts of the gate structure after the gate structure is formed, only the gate structure exposed out of the remaining gate mask layer is etched, the width of the gate structure to be etched is small, the process difficulty of forming the beam-shaped gate structure is favorably reduced, the height consistency of the second part of the gate structure is improved, and the electrical performance of the semiconductor structure is further improved.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 6 to 10 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 6 and 7, a perspective view of the semiconductor structure and a cross-sectional view along the direction AA1 in fig. 6 are respectively illustrated, and a base is formed, where the base includes a substrate 100, a fin 110 protruding from the substrate 100, and a gate structure 112 crossing the fin 110, the gate structure 112 covers a part of the top and a part of the sidewall of the fin 110, and a gate mask layer 113 is formed on the top of the gate structure 112.
The substrate 100 provides a processing platform for subsequently forming semiconductor structures.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 110 is used to subsequently provide a conduction channel for a finfet.
In this embodiment, the fin 110 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, an isolation structure 111 is further formed on the substrate 100 where the fin 110 is exposed.
The isolation structure 111 is used for isolating adjacent devices, and the material of the isolation structure 111 may be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation structure 111 is made of silicon oxide.
In this embodiment, the gate structure 112 is a dummy gate structure, and the gate structure 112 occupies a space for a metal gate structure to be formed subsequently.
Accordingly, the gate structure 112 includes a gate oxide layer (not shown) and a gate layer (not shown) on the gate oxide layer.
The gate oxide layer is made of silicon oxide or silicon oxynitride; the grid layer is made of polycrystalline silicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. In this embodiment, the gate oxide layer is made of silicon oxide, and the gate layer is made of polysilicon.
In other embodiments, the gate structure may not be a dummy gate structure, and accordingly, the gate structure does not need to be removed subsequently. In other embodiments, the gate structure may also be a metal gate structure.
The gate mask layer 113 is used as an etching mask for forming the gate structure 112, and after the gate mask layer 113 with a partial width on both sides of the gate structure 112 is subsequently removed, the remaining gate mask layer 113 is also used as an etching mask for etching the gate structure 112 to form a beam-shaped gate structure, and the gate mask layer 113 can also protect the top of the gate structure 112 in subsequent process steps. In this embodiment, the gate mask layer 131 is made of silicon nitride.
Specifically, the step of forming the gate structure 112 includes: forming a gate structure material layer (not shown) crossing the fin 110, wherein the gate structure material layer comprises a gate oxide layer covering the surface of the fin 110 and a gate material layer (not shown) located on the gate oxide layer, and the gate structure material layer covers the top and the side wall of the fin 110; forming a gate mask layer 113 on the top of the gate structure material layer; and etching the gate structure material layer by taking the gate mask layer 113 as a mask, and taking the residual gate structure material layer as the gate structure 112.
In this embodiment, an isolation structure 111 is further formed on the substrate 100 where the fin 110 is exposed, and therefore, the gate structure 112 is formed on the isolation structure 111.
Referring to fig. 8, an isolation layer 114 is formed on the substrate 100 where the fins 110 are exposed, and the isolation layer 114 covers a portion of the sidewalls of the gate structure 112. Specifically, the isolation layer 114 is formed on the isolation structure 111.
The subsequent process further comprises: removing the gate mask layer 113 with the width of the two side portions of the gate structure 112, etching the gate structure 112 exposed by the gate mask layer 113 by using the remaining gate mask layer 113 as a mask and the isolation layer 114 as an etching stop layer to form a beam-shaped gate structure, wherein the beam-shaped gate structure comprises a first portion of the gate structure located below the gate mask layer 113 and second portions of the gate structure located at the two sides of the first portion of the gate structure.
In this embodiment, the isolation layer 114 and the isolation structure 111 are made of the same material, and the isolation layer 114 is made of silicon oxide.
Silicon oxide is a dielectric material with a common process and a low cost, and has high process compatibility, which is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 114.
Moreover, the following processes usually further include: forming a beam-shaped gate structure, forming an interlayer dielectric layer on the substrate 100 exposed by the beam-shaped gate structure, wherein silicon oxide is also a commonly used material for the interlayer dielectric layer, and by making the isolation layer 114 be made of silicon oxide, the isolation layer 114 may not be removed subsequently and the isolation layer 114 is used as a part of the interlayer dielectric layer, which is beneficial to simplifying the process flow and further improving the process compatibility. In other embodiments, the material of the isolation layer may also be silicon nitride or a silicon-containing anti-reflective coating (Si-ARC).
It should be noted that the thickness of the isolation layer 114 is not too small, nor too large. If the thickness of the isolation layer 114 is too small, the process difficulty of forming the isolation layer 114 is easily increased, and correspondingly, the process difficulty of subsequently forming the beam-shaped gate structure is also increased, the thickness of the isolation layer 114 is too small, the effect of defining an etching stop layer in the process of etching the gate structure 112 exposed by the gate mask layer 113 at the top of the isolation layer 114 is also easily reduced, and the thickness of the second part of the subsequent gate structure is easily too small due to the too small thickness of the isolation layer 114, so that the process requirements are difficult to meet; if the thickness of the isolation layer 114 is too large, the thickness of the second portion of the subsequent gate structure is correspondingly large, which tends to reduce process compatibility and to adversely affect the electrical performance of the semiconductor structureAnd (6) sounding. For this purpose, in this embodiment, the thickness of the isolation layer 114 is
To
It should be noted that, in this embodiment, the forming step of the isolation layer 114 is a manufacturing process commonly used in the semiconductor field, and the process compatibility is high, and the subsequent processes further include: and removing the gate mask layer 113 with the width of the two side parts of the gate structure 112, and etching the gate structure 112 exposed by the gate mask layer 113, wherein compared with the gate structure 112, the thickness of the isolation layer 114 is smaller, the process deviation for forming the isolation layer 114 is smaller, the process stability is high, so that the thickness uniformity of the isolation layer 114 can be ensured, and the height consistency of the second part of the subsequent gate structure is improved.
Specifically, the step of forming the isolation layer 114 includes: forming an isolation film (not shown) on the substrate 100 exposed by the fin 110, wherein the isolation film (not shown) covers a portion of the sidewall of the gate structure 112; planarizing the isolation film; part of the thickness of the isolation film is removed, and the remaining isolation film is left as the isolation layer 114.
In this embodiment, the isolation film is formed by an atomic layer deposition process. The atomic layer deposition process has good deposition uniformity, is beneficial to improving the thickness uniformity and the film quality of the isolation film, is correspondingly beneficial to improving the film forming quality of the isolation layer 114, and is also beneficial to accurately controlling the deposition thickness of the isolation film by adopting the atomic layer deposition process. In other embodiments, the isolation film may also be formed using a chemical vapor deposition process.
In this embodiment, a Chemical-Mechanical Polishing (CMP) process is used to planarize the isolation film, which is beneficial to improving the surface flatness and the thickness uniformity of the isolation film, so as to ensure the surface flatness and the thickness uniformity of the isolation layer.
In this embodiment, a plasma etching process is used to remove a portion of the thickness of the isolation film.
The plasma etching process has high etching selectivity, is favorable for reducing the influence on other materials in the process of etching the isolating film, has good etching profile controllability, and is favorable for improving the film quality of the isolating layer.
Referring to fig. 9, after the isolation layer 114 is formed, the gate mask layer 113 is removed along the width of the two side portions of the gate structure 112.
In this embodiment, after the gate structure 112 is formed, the gate mask layer 113 of the width of the two side portions of the gate structure 112 is removed, and compared with a scheme that the gate structure material layer is etched by directly using the gate mask layer as a mask and the gate structure material layer exposed by the gate mask layer is reserved as the second portion of the initial gate structure, in the embodiment of the present invention, only the gate structure 112 exposed by the remaining gate mask layer 113 needs to be etched subsequently, the width of the gate structure 112 to be etched is small, the process stability is improved, the process difficulty of forming the beam-shaped gate structure is further reduced, the height consistency of the second portion of the gate structure is improved, and further the electrical performance of the semiconductor structure is improved.
Note that the removal width W of the single-sided gate mask layer 113 of the gate structure 112 is not necessarily too small, nor is it necessarily too large. If the removal width W is too small, the difficulty of subsequently etching the gate structure 112 by using the remaining gate mask layer 113 as a mask is easily increased, and the width of the second part of the subsequently formed gate structure is easily too small, so that the process requirements are difficult to meet; if the removal width W is too large, the width of the first portion of the subsequent gate structure is too small, which may adversely affect the electrical performance of the semiconductor structure. Therefore, in the present embodiment, the removal width W of the single-sided gate mask layer 113 of the gate structure 112 is 1nm to 10nm.
In this embodiment, a mask trimming process is adopted to remove the gate mask layer 113 of the width of the two side portions of the gate structure 112.
Specifically, a plasma etching process is adopted to remove the gate mask layer 113 of the width of the two side portions of the gate structure 112. The plasma etching process has high etching selectivity, and can accurately control the etching amount, so that the removal amount of the gate mask layer 113 meets the process requirement, and the influence on other materials in the process of etching the gate mask layer 113 can be reduced by adopting the plasma etching process.
It should be further noted that, in this embodiment, after the isolation layer 114 is formed, the gate mask layer 113 with the width of the two side portions of the gate structure 112 is removed, and the isolation layer 114 covers a portion of the side wall of the gate structure 112, so that the bottom of the gate structure 112 is not exposed in a process environment for etching the gate mask layer 113, damage to the gate structure 112 in the process of etching the gate mask layer 113 is avoided, and the electrical performance of the semiconductor structure is correspondingly improved.
Referring to fig. 10, the gate structure 112 exposed by the gate mask layer 113 is etched (as shown in fig. 9) by using the remaining gate mask layer 113 as a mask and the isolation layer 114 as an etch stop layer, so as to form a beam-shaped gate structure 120, where the beam-shaped gate structure 120 includes a gate structure first portion 115 located below the gate mask layer 113 and a gate structure second portion 116 located at two sides of the gate structure first portion 115 and protruding from the gate structure first portion 115.
The top of the isolation layer 114 can play a role in defining an etching stop position in the process of etching the gate mask layer 113 to expose the gate structure 112, so that the height consistency and the film quality of the second part 116 of the gate structure are improved, and the process difficulty of forming the beam-shaped gate structure 120 is reduced; moreover, compared with the scheme that the gate structure material layer is directly etched by taking the gate mask layer as the mask and the gate structure material layer exposed by the gate mask layer is reserved as the second part of the initial gate structure, the embodiment only etches the gate structure 112 exposed by the residual gate mask layer 113, the width of the gate structure 112 to be etched is small, the process stability is improved, the process difficulty of forming the beam-shaped gate structure 120 is further reduced, the height consistency of the second part 116 of the gate structure is improved, and the electrical performance of the semiconductor structure is further improved.
It should be noted that, in the step of etching the gate structure 112 exposed by the remaining gate mask layer 113, the etching selection ratio of the process for etching the gate structure 112 to the gate structure 112 and the isolation layer 114 is not too small. If the etching selection ratio is too small, the top of the isolation layer 114 is difficult to define the etching stop position in the process of etching the gate mask layer 113 to expose the gate structure 112, and the effect of the isolation layer 114 serving as an etching stop layer is reduced, so that the height uniformity of the second portion 116 of the gate structure is easily reduced, and the process difficulty of forming the beam-shaped gate structure 120 is increased. For this reason, in this embodiment, the etching selectivity ratio of the process for etching the gate structure 112 to the etching of the gate structure 112 and the isolation layer 114 is greater than 100.
In this embodiment, a plasma etching process is used to etch the gate structure 112 exposed by the gate mask layer 113. The etching selectivity of the plasma etching process to the gate structure 112 and the isolation layer 114 is relatively large, which is beneficial to making the effect of the top of the isolation layer 114 for defining the etching stop position more obvious, so that the etching amount of the gate structure 112 meets the process requirement, and the height consistency of the second part 116 of the gate structure is further improved; moreover, the plasma etching process has high etching selectivity, and can reduce the influence on other structures in the process of etching the gate structure 112 exposed by the gate mask layer 113.
The etching gas adopted by the plasma etching process is SF 6 、CF 4 And Cl 2 。
It should be noted that the flow rate of the etching gas in the plasma etching process should not be too small, and should not be too large. If the flow rate of the etching gas is too small, it is difficult to pre-etch the gate structure 112The range is set, and the etching rate is easy to reduce; if the etching gas flow is too large, the process stability is easily reduced, and over-etching is easily caused to the gate structure 112, so that the shape of the beam-shaped gate structure 120 is difficult to meet the process requirement, and the height consistency of the second portion 116 of the gate structure is also poor. Therefore, in this embodiment, the etching gas adopted by the plasma etching process is SF 6 、CF 4 And Cl 2 ，SF 6 The gas flow is 10SCCM to 100SCCM 4 The gas flow is 0SCCM to 200SCCM 2 The gas flow is 0 to 500SCCM.
In addition, in this embodiment, SF 6 、CF 4 And Cl 2 The temperature of the gas is 0 ℃ to 150 ℃, and the process pressure is 1mtorr to 200mtorr. The gas flow, the reaction temperature and the process pressure of the plasma etching process are set within reasonable ranges and matched with each other, so that the process stability of the etching efficiency is improved, the process cost is reduced, and the side effects are reduced.
The subsequent process further comprises: and forming source and drain doped layers in the fin portions 110 on two sides of the beam-shaped gate structure 120. When an NMOS transistor is formed, the material of the source-drain doped layer comprises a stress layer doped with N-type ions, the material of the stress layer is Si or SiC, the stress layer provides a tensile stress effect for a channel region of the NMOS transistor, and therefore the carrier mobility of the NMOS transistor is favorably improved, wherein the N-type ions are P ions, as ions or Sb ions; when a PMOS transistor is formed, the material of the source-drain doped layer comprises a stress layer doped with P-type ions, the material of the stress layer is Si or SiGe, the stress layer provides a compressive stress effect for a channel region of the PMOS transistor, and therefore the carrier mobility of the PMOS transistor is improved, wherein the P-type ions are B ions, ga ions or In ions.
Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 11, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 200; a fin 210 protruding from the surface of the substrate 200; an isolation layer 214 on the substrate 200 where the fin 210 is exposed; a beam-shaped gate structure 220 including a gate structure first portion 215 crossing the fin 210 and covering a portion of the top and a portion of the sidewall of the fin 210; and a second portion 216 of the gate structure located on two sides of the first portion 215 of the gate structure and protruding from the first portion 215 of the gate structure, wherein the second portion 216 of the gate structure covers a portion of the sidewalls of the fin 210 and the top of the second portion 216 of the gate structure is flush with the top of the isolation layer 214.
In the embodiment of the present invention, the beam-shaped gate structure 220 is obtained by etching the gate structure with the gate mask layer as a mask, and compared with a scheme that the semiconductor structure does not include the isolation layer, the isolation layer 214 can serve as an etching stop layer, and the top of the isolation layer can play a role in defining an etching stop position in the process of etching the gate structure exposed by the gate mask layer, so that the height consistency and the film quality of the second portion 216 of the gate structure are good, and the process difficulty for forming the beam-shaped gate structure 220 is low; moreover, compared with the scheme that the gate structure material layer is etched by directly taking the gate mask layer as a mask, and the gate structure material layer exposed by the gate mask layer is reserved as the second part of the initial gate structure, the gate mask layer with the width of the two side parts of the gate structure is removed after the gate structure is formed, only the gate structure exposed by the residual gate mask layer is etched, the width of the gate structure to be etched is smaller, the process difficulty of forming the beam-shaped gate structure 220 is favorably reduced, the height consistency of the second part 216 of the gate structure is improved, and the electrical performance of the semiconductor structure is further improved.
The substrate 200 provides a process platform for the formation of semiconductor structures.
In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be a silicon-on-insulator substrate or another type of substrate such as a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
In this embodiment, the fin 210 and the substrate 200 are obtained by etching the same semiconductor layer. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
Therefore, in this embodiment, the material of the fin portion 210 is the same as the material of the substrate 200, and the material of the fin portion 210 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, the semiconductor structure further includes: an isolation structure 211 is located on the substrate 200 where the fin 210 is exposed.
The isolation structure 211 is used for isolating adjacent devices, and the isolation structure 211 may be made of silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the isolation structure 211 is made of silicon oxide.
In this embodiment, the isolation layer 214 is also located on the isolation structure 211.
In this embodiment, the isolation layer 214 and the isolation structure 211 are made of the same material, and the isolation layer 214 is made of silicon oxide.
Silicon oxide is a dielectric material with a low cost, which is commonly used in the process, and has a high process compatibility, which is beneficial to reducing the process difficulty and the process cost for forming the isolation layer 214.
Moreover, the subsequent processes usually further include: an interlayer dielectric layer, silicon oxide is also a commonly used material for the interlayer dielectric layer, is formed on the substrate 200 exposed from the beam-shaped gate structure 220, and by making the isolation layer 214 of silicon oxide, the isolation layer 214 may not be removed subsequently, and the isolation layer 214 is retained as a part of the interlayer dielectric layer, which is beneficial to simplifying the process flow and further improving the process compatibility. In other embodiments, the material of the isolation layer may also be silicon nitride or a silicon-containing anti-reflective coating.
It should be noted that the thickness of the isolation layer 214 is not too small, nor too large. If the thickness of the isolation layer 214 is too small, the process difficulty of forming the isolation layer 214 is easily increased, and correspondingly, the process difficulty of forming the beam-shaped gate structure 220 is also increased, the too small thickness of the isolation layer 214 also easily reduces the effect of defining an etching stop position in the process of etching the gate structure exposed by the gate mask layer on the top of the isolation layer 214, and moreover, the too small thickness of the isolation layer 214 also easily causes the too small thickness of the second portion 216 of the gate structure, so that the process requirements are difficult to meet; if the thickness of the isolation layer 214 is too large, the thickness of the second portion 216 of the gate structure is correspondingly large, which tends to reduce process compatibility and adversely affect the electrical performance of the semiconductor structure. For this purpose, in the present embodiment, the thickness of the isolation layer 214 is
To
It should be noted that, in this embodiment, the step of forming the isolation layer 214 is a manufacturing process commonly used in the semiconductor field, and has high process compatibility, and compared with the step of forming the beam-shaped gate structure 220, the thickness of the isolation layer 214 is smaller, the process stability is higher, and the process deviation is smaller, so that the thickness uniformity of the isolation layer 214 can be ensured, the height uniformity of the second portion 216 of the gate structure is further improved, and the electrical performance of the semiconductor structure is optimized.
In this embodiment, the beam-shaped gate structure 220 is a dummy gate structure, and the beam-shaped gate structure 220 occupies a space for forming a metal gate structure subsequently.
Accordingly, the beam-shaped gate structure 220 includes a gate oxide layer (not shown) and a gate layer (not shown) on the gate oxide layer.
The gate oxide layer is made of silicon oxide or silicon oxynitride; the gate layer is made of polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon oxycarbonitride or amorphous carbon. In this embodiment, the gate oxide layer is made of silicon oxide, and the gate layer is made of polysilicon.
In other embodiments, the beam-shaped gate structure may not be a dummy gate structure, and accordingly, the gate structure does not need to be removed subsequently. In other embodiments, the beam-shaped gate structure may also be a metal gate structure.
In this embodiment, the beam-shaped gate structure 220 is also located on the isolation structure 211.
In this embodiment, the beam-shaped gate structure 220 is an integrated structure, because the beam-shaped gate structure 220 is formed by the steps including: after the grid structure is formed, removing the grid mask layer with the width of the two side parts of the grid structure; and exposing the residual gate mask layer by taking the residual gate mask layer and the isolation layer 214 as an etching stop layer. In other embodiments, the beam-shaped gate structure may not be an integral structure according to actual process requirements.
Thus, in this embodiment, the top of the second portion 216 of the gate structure is flush with the top of the isolation layer 214. Specifically, the spacers 214 cover sidewalls of the second portion 216 of the gate structure.
It should be noted that, along the direction perpendicular to the sidewalls of the beam-shaped gate structure 220, the dimension w of the second portion 216 of the gate structure protruding beyond the first portion 215 of the gate structure is not too small or too large. If the dimension w of the second portion 216 of the gate structure protruding beyond the first portion 215 of the gate structure is too small, the difficulty of forming the second portion 216 of the gate structure is easily increased, and the too small dimension w also easily makes the second portion 216 of the gate structure have a poor effect on improving the control capability of the beam-shaped gate structure 220 on the channel region, so that the process requirements are difficult to meet; if the dimension w of the second portion 216 of the gate structure protruding beyond the first portion 215 of the gate structure is too large, the electrical performance of the semiconductor structure is easily adversely affected. For this reason, in the present embodiment, the dimension w of the second portion 216 of the gate structure protruding beyond the first portion 215 of the gate structure is 1nm to 10nm.
The semiconductor structure of this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the invention, as defined in the appended claims.
Claims (19)
1. A method of forming a semiconductor structure, comprising:
forming a substrate, wherein the substrate comprises a substrate, a fin part protruding out of the substrate and a grid structure crossing the fin part, the grid structure covers part of the top and part of the side wall of the fin part, and a grid mask layer is formed at the top of the grid structure;
forming an isolation layer on the substrate exposed out of the fin part, wherein the isolation layer covers part of the side wall of the grid electrode structure;
after the isolation layer is formed, removing the grid mask layer with the width of the two side parts of the grid structure;
and etching the grid structure exposed by the grid mask layer by taking the residual grid mask layer as a mask and the isolation layer as an etching stop layer to form a beam-shaped grid structure, wherein the beam-shaped grid structure comprises a first grid structure part positioned below the grid mask layer and second grid structure parts positioned on two sides of the first grid structure part and protruding out of the first grid structure part.
2. The method of forming a semiconductor structure of claim 1, wherein said fin is exposedIn the step of forming the isolation layer on the substrate, the thickness of the isolation layer is
To
3. The method as claimed in claim 1, wherein the gate mask layer is removed by a mask trimming process to remove the width of the gate mask layer at the two sides of the gate structure.
4. The method for forming a semiconductor structure according to claim 1 or 3, wherein the gate mask layer is removed by a plasma etching process in a width direction of both side portions of the gate structure.
5. The method as claimed in claim 1, wherein in the step of removing the gate mask layer with the width of the two side portions of the gate structure, the removal width of the single-side gate mask layer of the gate structure is 1nm to 10nm.
6. The method for forming a semiconductor structure according to claim 1, wherein in the step of etching the gate structure where the gate mask layer remains, an etching selection ratio of a process for etching the gate structure to the gate structure and the isolation layer is greater than 100.
7. The method for forming the semiconductor structure according to claim 1 or 6, wherein a plasma etching process is adopted to etch the gate structure exposed by the gate mask layer by using the remaining gate mask layer as a mask and the isolation layer as an etching stop layer.
8. The method of forming a semiconductor structure of claim 7, wherein the plasmaThe parameters of the etching process are as follows: the etching gas is SF 6 、CF 4 And Cl 2 ，SF 6 The gas flow is 10SCCM to 100SCCM 4 The gas flow is 0SCCM to 200SCCM 2 The gas flow is 0SCCM to 500SCCM 6 、CF 4 And Cl 2 The temperature of the gas is 0 ℃ to 150 ℃, and the process pressure is 1mtorr to 200mtorr.
9. The method of claim 1, wherein the isolation layer is formed of a material selected from the group consisting of silicon oxide, silicon nitride, and silicon-containing anti-reflective coatings.
10. The method of forming a semiconductor structure of claim 1, wherein the isolation layer is formed by an atomic layer deposition process or a chemical vapor deposition process.
11. The method of forming a semiconductor structure of claim 1, wherein the step of forming the isolation layer comprises: forming an isolation film on the substrate with the exposed fin part, wherein the isolation film covers part of the side wall of the gate structure;
planarizing the isolation film;
and removing part of the thickness of the isolation film, and keeping the rest of the isolation film as the isolation layer.
12. The method of forming a semiconductor structure of claim 11, wherein a plasma etch process is used to remove a portion of the thickness of the isolation film.
13. The method for forming a semiconductor structure according to claim 1, wherein the gate structure is a dummy gate structure.
14. A semiconductor structure formed by the method of forming a semiconductor structure of any one of claims 1 to 13, the semiconductor structure comprising:
a substrate;
the fin part protrudes out of the surface of the substrate;
the isolation layer is positioned on the substrate with the exposed fin part;
the beam-shaped gate structure comprises a first gate structure part, a second gate structure part and a third gate structure part, wherein the first gate structure part spans the fin part and covers part of the top and part of the side wall of the fin part; and the second part of the grid electrode structure is positioned on two sides of the first part of the grid electrode structure and protrudes out of the first part of the grid electrode structure, the second part of the grid electrode structure covers part of the side wall of the fin part, and the top of the second part of the grid electrode structure is flush with the top of the isolation layer.
15. The semiconductor structure of claim 14, wherein the isolation layer has a thickness of
To
16. The semiconductor structure of claim 14, wherein the isolation layer is a silicon oxide, a silicon nitride, or a silicon-containing anti-reflective coating.
17. The semiconductor structure of claim 14, wherein the dimension of the second portion of the gate structure protruding beyond the first portion of the gate structure in a direction perpendicular to the sidewalls of the beam-shaped gate structure is 1nm to 10nm.
18. The semiconductor structure of claim 14, wherein the beam-shaped gate structure is a monolithic structure.
19. The semiconductor structure of claim 14, wherein the beam gate structure is a dummy gate structure.
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| US9318582B2 (en) * | 2014-03-17 | 2016-04-19 | International Business Machines Corporation | Method of preventing epitaxy creeping under the spacer |
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| CN108122768A (en) * | 2016-11-29 | 2018-06-05 | 台湾积体电路制造股份有限公司 | The forming method of semiconductor device |
| CN108878529A (en) * | 2017-05-16 | 2018-11-23 | 中芯国际集成电路制造（天津）有限公司 | Semiconductor devices and its manufacturing method |
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