CN113745113B - Semiconductor device and method of forming the same - Google Patents

Semiconductor device and method of forming the same Download PDF

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Publication number
CN113745113B
CN113745113B CN202010469293.3A CN202010469293A CN113745113B CN 113745113 B CN113745113 B CN 113745113B CN 202010469293 A CN202010469293 A CN 202010469293A CN 113745113 B CN113745113 B CN 113745113B
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layer
forming
channel
substrate
semiconductor device
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CN113745113A (en
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor device and a method of forming the same, including: providing a substrate, wherein the substrate is provided with a plurality of channel columns which are arranged separately, and each channel column comprises a true channel column and a false channel column; forming a sacrificial layer on the substrate surface, the side walls and the top of the channel pillars; forming a patterned layer on the sacrificial layer to expose the sacrificial layer on the side wall and the top of the pseudo channel column and a part of the sacrificial layer on the substrate between the pseudo channel column and the pseudo channel column; after forming the patterned layer, the exposed sacrificial layer and the dummy channel columns at the bottom of the sacrificial layer are removed until the substrate surface is exposed. The forming method can improve the performance of the fin field effect transistor with the channel gate surrounding structure.

Description

Semiconductor device and method of forming the same
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor device and a method of forming the same.
Background
Fin field effect transistors (Fin FETs) are an emerging type of multi-gate device that generally include a Fin protruding from a semiconductor substrate surface, a gate structure covering a portion of the top surface and sidewalls of the Fin, and source-drain doped regions in the Fin on either side of the gate structure. In the traditional planar metal-oxide semiconductor field effect transistor structure, a gate for controlling current to pass through can only control the on and off of a circuit at one side of the gate, and belongs to a planar architecture; in the FinFET structure, the gate is a 3D fork-like structure similar to a fin, and can control the on/off of the circuit at both sides of the circuit. The fin field effect transistor has stronger short channel inhibition capability, can improve circuit control, reduce leakage current, shorten the gate length of the transistor, and has stronger working current and better electrical control on a channel.
With further development of semiconductor technology, the size of integrated circuit devices is smaller and smaller, and conventional fin field effect transistors have limitations in further increasing the operating current. In particular, since only the regions of the fin near the top surface and the sidewalls are used as the channel region, the volume of the fin used as the channel region is smaller, which limits the operating current of the fin field effect transistor. Therefore, a gate-all-around (GAA) fin field effect transistor (GAA FinFET) structure is proposed, so that the volume for serving as a channel region is increased, and the operating current of the channel gate-around fin field effect transistor is further increased.
However, the performance of the fin field effect transistor with the channel gate surrounding structure in the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor device and a forming method thereof, which are used for improving the performance of a fin field effect transistor with a channel gate surrounding structure.
In order to solve the above technical problems, the present invention provides a method for forming a semiconductor device, including: providing a substrate, wherein the substrate is provided with a plurality of channel columns which are arranged separately, and the channel columns comprise true channel columns and false channel columns; forming a sacrificial layer on the surface of the substrate, the side wall and the top of the channel column; forming a patterned layer on the sacrificial layer, the patterned layer exposing the sacrificial layer on the sidewalls and top of the dummy channel columns and a portion of the sacrificial layer on the substrate between the true channel columns and the dummy channel columns; and after the patterning layer is formed, removing the exposed sacrificial layer and the pseudo channel column positioned at the bottom of the sacrificial layer, and exposing the surface of the substrate.
Optionally, the sacrificial layer material is at least one of SiN, siOCN or SiBCN.
Optionally, before forming the sacrificial layer, the method further includes: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the channel column, and the top surface of the isolation layer is lower than the top surface of the channel column.
Optionally, the method for forming the isolation layer includes: forming an initial isolation layer on the substrate, wherein the initial isolation layer covers the true channel column and the false channel column; flattening the initial isolation layer until the top surfaces of the true channel columns and the false channel columns are exposed; after planarization, etching back a portion of the initial isolation layer to form the isolation layer.
Optionally, after removing the exposed sacrificial layer and the dummy channel post at the bottom of the sacrificial layer until the substrate surface is exposed, the method further includes: and removing the patterned layer.
Optionally, after removing the patterned layer, the method further includes: an insulating layer is formed on top surfaces of the dummy channel columns remaining in and having a surface lower than the surface of the isolation layer, the top surfaces of the insulating layer being flush with the top surfaces of the isolation layer.
Optionally, after forming the insulating layer, the method further includes: and removing the sacrificial layer on the top and the side wall of the true channel column and the sacrificial layer on the surface of the substrate.
Optionally, after removing the sacrificial layer on the top and the sidewall of the true channel pillar and the sacrificial layer on the surface of the substrate, further comprising: and forming a gate structure on the surface of the side wall of the true channel, wherein the gate structure comprises a first part and a second part, the first part surrounds the true channel column, and the second part is positioned on the surface of the substrate at one side of the true channel column.
Optionally, the first portion of the gate structure includes: the gate dielectric layer is positioned on the side wall of the true channel column, the work function layer is positioned on the surface of the gate dielectric layer, and the gate layer is positioned on the surface of the work function layer; the second portion of the gate structure includes: and the work function layer is positioned on the surface of the substrate, and the gate layer is positioned on the surface of the work function layer.
Optionally, after forming the gate structure on the sidewall surface of the true channel pillar, the method further includes: forming a dielectric layer on the isolation layer and the insulation layer, wherein the dielectric layer covers the gate structure and the true channel column; and forming a conductive structure in the dielectric layer.
Correspondingly, the invention also provides a semiconductor device, which comprises: a substrate; a true channel pillar on the substrate; an isolation layer which is positioned on the substrate and covers part of the side wall of the true channel column; and partial pseudo-channel column is positioned on the substrate and in the isolation layer, and the top surface is lower than the top surface of the isolation layer.
Optionally, the method further comprises: and the insulating layer is positioned on the top surface of the partial pseudo-channel column, and the top surface is flush with the top surface of the isolation layer.
Optionally, the method further comprises: a gate structure comprising a first portion surrounding the true channel pillar and a second portion on a surface of the isolation layer on a side of the true channel pillar.
Optionally, the method further comprises: the dielectric layer is positioned on the isolation layer and covers the grid structure and the true channel column.
Optionally, the substrate includes: a substrate and a source doped layer located on the substrate.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
forming a plurality of channel columns which are arranged separately on a substrate, wherein the channel columns comprise true channel columns and pseudo channel columns adjacent to the true channel columns, forming sacrificial layers on the substrate and the side walls and the top of the channel columns, forming patterned layers on the sacrificial layers, exposing the sacrificial layers on the side walls and the top of the pseudo channel columns and part of the substrate between the true channel columns and the pseudo channel columns by using the patterned layers, removing the exposed sacrificial layers and the pseudo channel columns positioned at the bottom of the sacrificial layers, so that the process space around the true channel columns is enlarged, and thus, when a grid structure is formed on the side walls of the true channel columns, the forming height of the grid structure can be better controlled, the uniformity of the height of the grid structure is improved, space is provided for subsequent connection lines, and the process difficulty is reduced; meanwhile, before forming the patterned layer, a sacrificial layer is formed on the substrate and the side wall and the top of the channel column, the patterned layer only exposes the sacrificial layer on the side wall and the top of the channel column and part of the sacrificial layer on the substrate between the true channel column and the false channel column, and thus, in the process of removing the exposed sacrificial layer and the pseudo channel column at the bottom of the sacrificial layer, the sacrificial layer can protect the top and the side wall surfaces of the true channel column and part of the surface of the substrate around the true channel column from being damaged, and the performance and the quality of the formed semiconductor device are improved.
Further, the method of forming the isolation layer includes: forming an initial isolation layer on the source doping layer, wherein the initial isolation layer covers the true channel column and the false channel column; flattening the initial isolation layer until the top surfaces of the true channel columns and the false channel columns are exposed; after planarization treatment, etching part of the initial isolation layer to form an isolation layer, wherein the substrate is provided with a pseudo channel column, and when the isolation layer is formed by etching part of the initial isolation layer, the thickness uniformity of the isolation layer is better, because the process environment around the pseudo channel and the true channel column is similar due to existence of the pseudo channel column, the influence of the process environment on the isolation layer is approximately the same, and thus the isolation layer with uniform thickness is more convenient to form, so that the uniformity of device performance is improved.
Drawings
Fig. 1 to 4 are schematic cross-sectional structures of a semiconductor device in an embodiment;
fig. 5 to 16 are schematic cross-sectional structures of a semiconductor device forming process in an embodiment of the present invention.
Detailed Description
The performance of the fin field effect transistor with the conventional channel gate surrounding structure is to be improved. The analysis will now be described with reference to specific examples.
Referring to fig. 1, a base 100 is provided, the base 100 including a substrate 101 and a source doped layer 102 on the substrate 101.
Referring to fig. 2, a plurality of channel pillars 103 are formed on the source doped layer 102 in a discrete arrangement.
Referring to fig. 3, an isolation layer 104 is formed on the source doped layer 102, the isolation layer 104 covers a portion of the sidewall of the channel pillar 103, and the top surface of the isolation layer 104 is lower than the top surface of the channel pillar 103.
Referring to fig. 4, a gate structure 105 is formed on a sidewall surface of the channel pillar 103, a dielectric layer 106 is formed after the gate structure 105 is formed, and a conductive structure 107 is formed in the dielectric layer 106.
The inventor finds that the grid structure formed by the method has poor height uniformity, and the height of the grid structure is not well controlled when the grid structure is formed, and the height uniformity of the grid structure is poor; meanwhile, the thickness of the isolation layer is not well controlled, so that the performance of the semiconductor device is reduced, and the application range of the semiconductor device is limited.
The inventors found that: forming a channel column on a substrate, wherein the channel column comprises a true channel column and a false channel column adjacent to the true channel column, forming a sacrificial layer on the surface of the substrate and on the side wall and the top of the channel column, forming a patterned layer on the sacrificial layer, exposing the sacrificial layer on the side wall and the top of the false channel column and a part of the sacrificial layer on the substrate between the true channel column and the false channel column by using the patterned layer, so that when the exposed sacrificial layer is removed, the side wall and the top surface of the true channel column and a part of the surface of the substrate around the true channel column are not damaged under the protection of the sacrificial layer, and meanwhile, removing the false channel column, so that the process space around the true channel column is enlarged, and when the gate structure is formed on the side wall of the true channel column, the height of the gate structure is easier to control, so that the height uniformity of the gate structure is improved, and the quality and the performance of a formed semiconductor device are improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Note that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 5 to 16 are schematic cross-sectional structures of a semiconductor device forming process in an embodiment of the present invention.
Referring to fig. 5, a substrate 200 is provided.
The base 200 includes a substrate 201 and a source doped layer 202 on the substrate 201.
The source dopant layer 202 has dopant ions therein. The type of the doping ions is N type or P type; the N-type ions include, but are not limited to, phosphorus (P) ions, arsenic (As) ions, antimony (Sb) ions, and the like; the P-type ions include, but are not limited to, boron (B) ions, indium (In) ions, gallium (Ga) ions, and the like.
In this embodiment, the forming process of the source doped layer 202 includes an ion implantation process. In other embodiments, the source doped layer forming process includes an in-situ doping process, a high temperature diffusion process, and the like.
In this embodiment, the material of the substrate 201 is monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium (SiGe), gallium arsenide (GaAs), silicon-on-insulator (SOI), or germanium-on-insulator (GOI).
Referring to fig. 6, the substrate 200 has a plurality of channel pillars 300 arranged separately, and the channel pillars 300 include true channel pillars 301 and dummy channel pillars 302 adjacent to the true channel pillars 301.
In this embodiment, the dummy trench pillars 302 are trench pillars that are subsequently removed; the true channel pillar 301 is subsequently used as a channel for a semiconductor device.
In this embodiment, the number of the true channel columns 301 is one; in other embodiments, the number of true channel pillars 301 may also be multiple.
The number of the true channel pillars 301 and the dummy channel pillars 302 and their distribution are set according to an actual layout design.
In this embodiment, the number of the dummy channel columns 302 is two, and the dummy channel columns are respectively located at two sides of the true channel column 301.
In this embodiment, a plurality of channel pillars 300 are formed on the source doped layer 202.
The method for forming the channel pillar 300 includes: forming a channel material layer (not shown) on the substrate 201; forming a patterned mask layer (not shown) on the surface of the channel material layer, wherein the patterned mask layer exposes a part of the surface of the channel material layer; and etching the channel material layer by taking the patterned mask layer as a mask until the surface of the source doping layer 202 is exposed, and forming the channel pillars 300 on the source doping layer 202.
In this embodiment, the material of the channel pillar 300 comprises silicon. In other embodiments, the channel pillar 300 material includes semiconductor materials such as germanium, silicon germanium, gallium arsenide, and the like.
The process of etching the channel material layer comprises a dry etching process or a wet etching process; the process of forming the channel material layer includes a physical vapor deposition process, an epitaxial growth process, or an atomic layer deposition process.
In this embodiment, the process of etching the trench material layer includes a dry etching process, which can form the trench pillar 300 with good sidewall morphology; the process of forming the channel material layer includes a physical vapor deposition process capable of forming a channel material layer having a dense structure and a thicker thickness.
In this embodiment, the material of the patterned mask layer includes photoresist; the process of forming the patterned mask layer includes a spin-on process.
In other embodiments, the patterned mask layer comprises a hard mask layer and a photoresist layer on the hard mask layer, wherein the material of the hard mask layer comprises amorphous carbon (a-C), silicon oxide (SiO) 2 ) One or a combination of several materials such as silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon carbide nitride (SiCN), and polysilicon (Poly-Si).
In this embodiment, a protective layer is not formed on the top surface of the channel pillar 300.
In other embodiments, a protection layer may be formed on the top surface of the channel pillar 300, where the protection layer is used to protect the top of the channel pillar 300 from damage in a subsequent process. The material of the protective layer comprises silicon nitride, silicon oxide (SiO 2 ) Silicon oxynitride (SiON), carbonizationSilicon (SiC), silicon oxycarbide (SiOC), silicon carbide nitride (SiCN), polysilicon (Poly-Si), or the like.
After the channel pillars 300 are formed, the patterned mask layer is removed. In this embodiment, the process of removing the patterned mask layer includes an ashing process.
Referring to fig. 7, an isolation layer 203 is formed on the surface of the source doped layer 202, the isolation layer 203 is located on a portion of the sidewall surface of the channel pillar 300, and the top surface of the isolation layer 203 is lower than the top surface of the channel pillar 300.
The isolation layer 203 is used to electrically isolate the device.
The method for forming the isolation layer 203 comprises the following steps: forming an initial isolation layer (not shown) on the substrate 201, the initial isolation layer covering the true channel pillars 301 and the false channel pillars 302; planarizing the initial isolation layer until the top surfaces of the true channel pillars 301 and the false channel pillars 302 are exposed; after the planarization process, a portion of the initial isolation layer is etched back to form the isolation layer 203.
The material of the isolation layer 203 includes one or a combination of several of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbide nitride, polysilicon (Poly-Si) and the like; the process of forming the initial isolation layer includes a chemical vapor deposition process, a sputtering process, an atomic layer deposition process, or a physical vapor deposition process.
In this embodiment, the material of the isolation layer 203 includes silicon oxide; the process for forming the initial isolation material layer comprises a chemical vapor deposition process, particularly a flowable chemical vapor deposition process (FCVD), wherein the flowable chemical vapor deposition process is matched with a subsequent heat treatment process, so that the initial isolation layer with good filling performance and compact structure can be formed.
In this embodiment, since the substrate 200 has the dummy channel pillars 302, in the process of etching back a portion of the initial isolation layer to form the isolation layer 203, the thickness uniformity of the isolation layer 203 is better, and the thickness of the isolation layer 203 is better controlled, because the process environments around the dummy channel pillars 302 and the true channel pillars 301 are similar, so that the influence of the process environment on the formation of the isolation layer 203 is approximately the same, thus the formation of the isolation layer 203 with uniform density and uniform thickness is more convenient, and the uniformity of device performance is improved.
Referring to fig. 8, a sacrificial layer 204 is formed on the substrate surface, the sidewalls of the channel pillars 300, and the tops of the channel pillars 300.
In the present embodiment, the sacrificial layer 204 is formed on the surface of the isolation layer 203, the sidewalls of the channel pillars 300, and the top of the channel pillars 300.
In this embodiment, the sacrificial layer 204 is made of silicon nitride; in other embodiments, the material of the sacrificial layer 204 may be one or a combination of materials such as SiOCN, siBCN, siC or SiCN.
In this embodiment, the sacrificial layer 204 and the isolation layer 203 have a larger etching selectivity ratio, so that no damage or little damage to the surface of the isolation layer 203 can be ensured in the subsequent process of removing the sacrificial layer 204, thereby helping to ensure the surface quality of the isolation layer 203, and improving the quality and performance of the formed semiconductor device.
In the present embodiment, the sacrificial layer 204 is formed on the side wall of the channel pillar 300 and the top of the channel pillar 300, specifically, the sacrificial layer 204 is formed on the side wall and the top of the true channel pillar 301, and the sacrificial layer 204 is formed on the side wall and the top of the false channel pillar 302, respectively. The purpose of forming the sacrificial layer 204 on the top and the side wall of the true channel pillar 301 is to ensure that the side wall and the top of the true channel pillar 301 are not damaged in the subsequent etching process.
The sacrificial layer 204 is formed by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or the like.
In this embodiment, the process of forming the sacrificial layer 204 is an atomic layer deposition process, and specific process parameters include: by usingSiH 2 Cl 2 Or NH 3 As reaction gas, the reaction temperature is 200-600 ℃, the reaction pressure is 1 mTorr-100 mTorr, the flow rate of the gas is 1500-4000 sccm, and the reaction period is 20-100 times.
In the present embodiment, the thickness of the sacrificial layer 204 is in the range ofWhen the thickness of the sacrificial layer 204 is smaller than +>Since the thickness of the sacrificial layer 204 is too thin, it cannot protect the surface of the true channel pillar 201; when the thickness of the sacrificial layer 204 is greater than +.>The thickness of the sacrificial layer 204 is too thick, so that the space between the channel pillars 300 becomes smaller, the process window of the subsequent process becomes smaller, and the process difficulty is increased.
Referring to fig. 9, a patterned layer 205 is formed on the sacrificial layer 204, wherein the patterned layer 205 exposes the sacrificial layer 204 on the sidewalls and top of the dummy channel columns 302 and a portion of the sacrificial layer 204 on the substrate 200 between the dummy channel columns 301 and the dummy channel columns 302.
In this embodiment, the patterned layer 205 exposes the sacrificial layer 204 on the sidewalls and top of the dummy channel pillars 302 and portions of the sacrificial layer 204 on the isolation layer 203 between the true channel pillars 301 and the dummy channel pillars 302.
In this embodiment, the patterned layer 205 uses photoresist; in other embodiments, the patterned layer 205 may also be one or a combination of amorphous carbon (a-C), amorphous silicon (a-Si), polysilicon (Poly-Si), or some other material with a high etch selectivity to the sacrificial layer 204.
Referring to fig. 10, after the patterned layer 205 is formed, the exposed sacrificial layer 204 and the dummy trench pillars 302 covered by the sacrificial layer 204 are removed until the substrate surface is exposed.
In this embodiment, since the etching rate of the sacrificial layer 204 is much greater than that of the isolation layer 203, namely: has a high etching selectivity, so that the exposed sacrificial layer 204 on the isolation layer 203 has little or no damage to the surface of the isolation layer 203, thereby ensuring good morphology and flatness of the surface of the isolation layer 203.
In this embodiment, the process of removing the sacrificial layer 204 and the dummy trench pillars 302 covered by the sacrificial layer 204 is a dry etching process; specific parameters include: the reaction gas used comprises CF 4 、H 2 、O 2 、CH 3 F, performing the process; wherein CF is 4 The gas flow rate of (C) is 10 sccm-500 sccm, H 2 The gas flow rate of (2) is 20 sccm-300 sccm, O 2 The gas flow rate of (C) is 5 sccm-200 sccm, CH 3 The gas flow of F is 60 sccm-800 sccm, and the reaction pressure is 5 mTorr-200 mTorr.
In this embodiment, the dummy channel pillar 302 is removed, so that a larger process space is provided for forming the gate structure and the conductive structure on the true channel pillar 301 later, and thus, when the gate structure is formed on the true channel pillar 301, the height of the formed gate structure can be better controlled, so that the uniformity of the height of the gate structure can be improved, and the performance of the formed semiconductor device can be improved.
In this embodiment, since a portion of the sidewall of the dummy channel pillar 302 is covered by the isolation layer 203, a portion of the dummy channel pillar below the surface of the isolation layer 203 cannot be completely removed when the dummy channel pillar 302 is removed, so as to avoid damage to the surface of the source doped layer 202 caused by over etching. Thus, the portion of the dummy channel column that will be below the surface of the spacer 203 is denoted by 303.
In this embodiment, the top and the side walls of the true channel pillar 301 are protected by the sacrificial layer 204, so that the surface of the true channel pillar 301 is not damaged during the process of removing the false channel pillar 302, which is helpful for improving the quality of the formed semiconductor device.
Referring to fig. 11, after removing the exposed sacrificial layer 204 and the portion of the dummy channel posts 302 covered by the sacrificial layer 204 until the substrate surface is exposed, the patterned layer 205 is removed.
In this embodiment, an ashing process is used to remove the patterned layer 205; in other embodiments, an etching process (e.g., a dry etching process, a wet etching process, etc.) may also be used to remove the patterned layer 205.
Referring to fig. 12, an insulating layer 206 is formed on the top surface of the dummy channel column 303 remaining in the isolation layer 203 and having a surface lower than the surface of the isolation layer 203, the top surface of the insulating layer 206 being flush with the top surface of the isolation layer 203.
In this embodiment, the material of the insulating layer 206 is silicon oxide; in other embodiments, the material of the insulating layer 206 may be one or more of silicon carbide, silicon nitride, silicon oxynitride, or silicon carbide nitride.
In this embodiment, the insulating layer 206 is formed to electrically isolate the remaining dummy channel columns 303 so that the remaining dummy channel columns 303 cannot conduct electricity.
In this embodiment, the process of forming the insulating layer 206 is a chemical vapor deposition process; in other embodiments, the insulating layer 206 may also be formed using a physical vapor deposition process, a selective growth process, a heat treatment process, a sputtering process, or the like; in other embodiments, patterning processes may also be coordinated, such as: a masking layer, photoresist layer, photolithography, etching, etc. are deposited so that the insulating layer 206 is formed only on the surface of the remaining isolation layer 303, and the top surface of the insulating layer 206 is flush with the top surface of the isolation layer 203.
Referring to fig. 13, after the insulating layer 206 is formed, the sacrificial layer 204 on the top and side walls of the true channel pillars 301 and the sacrificial layer 204 on the substrate are removed.
In this embodiment, the sacrificial layer 204 on the top and sidewalls of the true channel pillars 301 is removed while the sacrificial layer 204 on the isolation layer 203 around the true channel pillars 301 is removed.
In this embodiment, the process of removing the sacrificial layer 204 on the top and the sidewall of the true channel pillar 301 and the sacrificial layer 204 on the isolation layer 203 is a dry etching process, and specific parameters include: the reaction gas used comprises CH 3 F、N 2 And O 2 Wherein CH is 3 F has a gas flow rate of 10sccm to 200sccm and N 2 The gas flow rate of (2) is 50 sccm-300 sccm, O 2 The gas flow rate is 10 sccm-80 sccm, and the reaction pressure is 5 mTorr-300 mTorr.
Referring to fig. 14, a gate structure 400 is formed on a surface of a sidewall of the true channel 301, the gate structure 400 includes a first portion 410 and a second portion 420, the first portion 410 surrounds the true channel pillar 301, and the second portion 420 is located on a surface of the isolation layer 203 on one side of the true channel pillar 301.
In this embodiment, the first portion 410 of the gate structure 400 includes: the gate dielectric layer 401 is positioned on the side wall of the true channel column 301, the work function layer 402 is positioned on the surface of the gate dielectric layer 401, and the gate electrode layer 403 is positioned on the surface of the work function layer 402; the second portion 420 of the gate structure 400 includes: the gate dielectric layer 401 is located on the surface of the substrate 201, the work function layer 402 is located on the surface of the gate dielectric layer 401, and the gate layer 403 is located on the surface of the work function layer 402.
The method for forming the gate dielectric layer 401 includes: forming a gate dielectric material layer (not shown) on the surface of the substrate 201 and the sidewall surfaces and the top surfaces of the true channel pillars 301; forming a mask layer (not shown) on the surface of the gate dielectric material layer, wherein the mask layer exposes part of the surface of the gate dielectric material layer; and etching the gate dielectric material layer by taking the mask layer as a mask until the surface of the isolation layer 203 is exposed, and forming the gate dielectric layer 401 on the side wall of the true channel column 301.
In this embodiment, the material of the gate dielectric layer 401 includes a High-K material, and the dielectric constant of the High-K material is greater than 3.9; the high dielectric constant material comprises hafnium oxide or aluminum oxide.
In other embodiments, the gate dielectric layer 401 comprises a material comprising silicon oxide (SiO 2 ) Zirconium oxide (ZrO) 2 ) Tantalum oxide (Ta) 2 O 5 ) Titanium oxide (TiO) 2 ) One or a combination of several of the same high dielectric constants.
In this embodiment, the process of forming the gate dielectric material layer includes a chemical vapor deposition process. In other embodiments, the process of forming the gate dielectric material layer includes an atomic layer deposition process, a thermal oxidation process, and the like.
In this embodiment, the material of the mask layer includes photoresist; in other embodiments, the material of the mask layer includes a hard mask material including one or a combination of several of silicon oxide, silicon nitride, silicon carbide (SiC), silicon oxycarbide (SiOC), amorphous carbon (a-C), silicon oxynitride (SiON), polysilicon (Poly-Si), and the like, which have a high etching selectivity to the gate dielectric layer 401.
In this embodiment, the process of forming the mask layer includes a spin-coating process; in other embodiments, the process of forming the mask layer further includes chemical vapor deposition, atomic layer deposition, physical vapor deposition, and the like.
After the gate dielectric layer 401 is formed, the mask layer is removed. In this embodiment, the process of removing the mask layer includes an ashing process.
The method for forming the work function layer 402 and the gate layer 403 includes: forming a work function material layer (not shown) on the surface of the substrate 201 and the surface of the gate dielectric layer 401; forming a gate material layer (not shown) on the work function material layer surface; forming a mask layer (not shown) on the surface of the gate material layer, wherein the mask layer exposes a part of the surface of the gate material layer; and etching the gate material layer and the work function material layer by taking the mask layer as a mask until the surface of the isolation layer 203 is exposed, and forming the work function layer 402 and the gate layer 403 on the work function layer 402 on the side wall of the true channel pillar 301 and the surface of the substrate 201.
The material of the work function layer 402 includes titanium (Ti), titanium nitride (TiN), aluminum titanate (TiAl), tantalum nitride (TaN), or the like.
The material of the gate layer 403 includes polysilicon (Poly-Si), metals (e.g., tungsten, cobalt, nickel, etc.), silicon metals (e.g., titanium silicon (TiSi), tungsten silicon (WSi), cobalt silicon (CoSi), etc.). In this embodiment, the material of the gate layer includes a metal including tungsten.
In the present embodiment, the process of forming the work function material layer includes a chemical vapor deposition process or a physical vapor deposition process.
In this embodiment, the process of forming the gate material layer includes a physical vapor deposition process or an electroplating process.
In the present embodiment, the process of etching the gate material layer and the work function material layer includes a dry etching process.
Referring to fig. 15, after the gate structure 400 is formed, a dielectric layer is formed on the isolation layer 203, the dielectric layer includes a first dielectric layer 207, and a second dielectric layer 208 is formed on the first dielectric layer 207.
The first dielectric layer 207 exposes the gate dielectric layer 401 on top of and part of the sidewalls of the true channel pillars 301.
In this embodiment, the method for forming the first dielectric layer 207 includes: an initial first dielectric layer (not shown) is formed on the isolation layer 203, the gate structure 400 is located in the initial first dielectric layer, and the gate layer 401 and the work function layer 402 on top of the true channel pillar 301 are etched back until the gate dielectric layer 401 on top of the true channel pillar 301 and the gate dielectric layer 401 on a portion of the sidewall of the true channel pillar 301 are exposed, so as to form the first dielectric layer 207.
In this embodiment, the material of the first dielectric layer 207 is silicon oxide; in other embodiments, the material of the first dielectric layer 207 includes one or more of silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide, or silicon carbide nitride.
After forming the first dielectric layer 207, a second dielectric layer 208 is formed on the gate structure 400 and on the first dielectric layer 207.
The top surface of the second dielectric layer 208 is higher than the top surface of the gate structure 400.
In this embodiment, the material of the second dielectric layer 208 includes silicon oxide; in other embodiments, the material of the second dielectric layer 208 includes silicon nitride or silicon carbide nitride.
In this embodiment, the process of forming the second dielectric layer 208 includes a chemical vapor deposition process. In other embodiments, the process of forming the second dielectric layer 208 includes an atomic layer deposition process or a thermal oxidation process.
Referring to fig. 16, a conductive structure is formed in the dielectric layer.
The conductive structures include a first conductive structure 501, a second conductive structure 502, and a third conductive structure 503.
In this embodiment, the first conductive structure 501 is connected to the source doped layer 202; the material of the first conductive structure 501 comprises a metal or metal silicide, and the metal comprises copper, tungsten or aluminum.
The process of forming the first conductive structure 501 includes a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, or the like.
In this embodiment, the process of forming the first conductive structure 501 is an electroplating process.
In this embodiment, the second conductive structure 502 is connected to the gate structure 400; the material of the second conductive structure 502 includes a metal including copper, tungsten, or aluminum.
The process of forming the second conductive structure 502 includes a chemical vapor deposition process, a physical vapor deposition process, an electroplating process, or the like.
In this embodiment, the third conductive structure 503 is connected to the second portion 420 of the gate structure 400.
The material of the third conductive structure 503 includes a metal including copper, tungsten, or aluminum.
Referring to fig. 15, the present invention further provides a semiconductor device, including: a substrate 200; a true channel pillar 301 located on the substrate 200; an isolation layer 203 on the substrate 200 and covering a portion of the sidewall of the true channel pillar 301; a portion of the dummy channel pillars 303 are located on the substrate 200 and within the isolation layer 203, with a top surface below the top surface of the isolation layer 203.
In this embodiment, in the process of forming the semiconductor device, the upper dummy channel pillar of the substrate 200 is etched and removed, the part of the dummy channel pillar 303 is formed on the substrate 200 only and is located in the isolation layer 203, and the top surface of the dummy channel pillar is lower than the top surface of the isolation layer 203, and in the process of forming the semiconductor device with this structure, the isolation layer 203 with uniform density and uniform thickness can be formed, because the part of the dummy channel pillar 303 is formed on the substrate 200 in advance, and then the dummy channel pillar is etched and formed, so that the influence of the process environment on the formation of the isolation layer 203 is approximately the same, thereby improving the quality of the isolation layer 203, in addition, the height uniformity of the gate structure formed on the subsequent dummy channel pillar 301 by the semiconductor device with this structure is better controlled, because the part of the dummy channel pillar 301 is the part of the dummy channel pillar 303, the part of the dummy channel pillar is lower than the gate structure 301, thereby improving the quality of the gate structure 301 is better than the gate structure 301, and the quality of the gate structure formed by the dummy channel pillar 301 is better than the control of the gate structure 301.
In this embodiment, further comprising: an insulating layer 206, the insulating layer 206 being located on top surfaces of the partial dummy channel columns 303, and the top surfaces being flush with top surfaces of the isolation layers 203.
In this embodiment, further comprising: a gate structure 400, the gate structure 400 comprising a first portion 410 and a second portion 420, the first portion 410 surrounding the true channel pillar 301, the second portion 420 being located on a surface of the isolation layer 203 on one side of the true channel pillar 301.
In this embodiment, the first portion 410 of the gate structure 400 includes: the gate dielectric layer 401 is positioned on the side wall of the true channel column 301, the work function layer 402 is positioned on the surface of the gate dielectric layer 401, and the gate electrode layer 403 is positioned on the surface of the work function layer 402; the second portion 420 of the gate structure 400 includes: the gate dielectric layer 401 is located on the surface of the substrate 201, the work function layer 402 is located on the surface of the gate dielectric layer 401, and the gate layer 403 is located on the surface of the work function layer 402.
In this embodiment, further comprising: a dielectric layer on the isolation layer 203, wherein the dielectric layer covers the gate structure 400 and the true channel pillar 301.
In this embodiment, the dielectric layer includes a first dielectric layer 207, and a second dielectric layer 208 is formed on the first dielectric layer 207.
The first dielectric layer 207 exposes the gate dielectric layer 401 on top of and part of the sidewalls of the true channel pillars 301.
The top surface of the second dielectric layer 208 is higher than the top surface of the gate structure 400.
In this embodiment, the substrate 200 includes: a substrate 201 and a source doped layer 202 on said substrate 201.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (15)

1. A method of forming a semiconductor device, comprising:
providing a substrate, wherein the substrate is provided with a plurality of channel columns which are arranged separately, and each channel column comprises a true channel column and a pseudo channel column adjacent to the true channel column;
forming a sacrificial layer on the surface of the substrate, the side wall and the top of the channel column;
forming a patterned layer on the sacrificial layer, the patterned layer exposing the sacrificial layer on the sidewalls and top of the dummy channel columns and a portion of the sacrificial layer on the substrate between the true channel columns and the dummy channel columns;
and after the patterning layer is formed, removing the exposed sacrificial layer and the pseudo channel column positioned at the bottom of the sacrificial layer, and exposing the surface of the substrate.
2. The method of forming a semiconductor device of claim 1, wherein the sacrificial layer material is at least one of SiN, siOCN, or SiBCN.
3. The method of forming a semiconductor device according to claim 1, further comprising, before forming the sacrificial layer: and forming an isolation layer on the substrate, wherein the isolation layer covers part of the side wall of the channel column, and the top surface of the isolation layer is lower than the top surface of the channel column.
4. The method of forming a semiconductor device according to claim 3, wherein the method of forming the isolation layer comprises: forming an initial isolation layer on the substrate, wherein the initial isolation layer covers the true channel column and the false channel column; flattening the initial isolation layer until the top surfaces of the true channel columns and the false channel columns are exposed; after planarization, etching back a portion of the initial isolation layer to form the isolation layer.
5. The method of forming a semiconductor device of claim 3, further comprising, after removing the exposed sacrificial layer and the dummy channel post at the bottom of the sacrificial layer to expose the substrate surface: and removing the patterned layer.
6. The method of forming a semiconductor device of claim 5, further comprising, after removing the patterned layer: an insulating layer is formed on top surfaces of the dummy channel columns remaining in and having a surface lower than the surface of the isolation layer, the top surfaces of the insulating layer being flush with the top surfaces of the isolation layer.
7. The method for forming a semiconductor device according to claim 6, further comprising, after forming the insulating layer: and removing the sacrificial layer on the top and the side wall of the true channel column and the sacrificial layer on the surface of the substrate.
8. The method of forming a semiconductor device of claim 7, further comprising, after removing the sacrificial layer on top and sidewalls of the true channel pillar and the sacrificial layer on the substrate surface: and forming a gate structure on the surface of the side wall of the true channel column, wherein the gate structure comprises a first part and a second part, the first part surrounds the true channel column, and the second part is positioned on the surface of the substrate at one side of the true channel column.
9. The method of forming a semiconductor device of claim 8, wherein the first portion of the gate structure comprises: the gate dielectric layer is positioned on the side wall of the true channel column, the work function layer is positioned on the surface of the gate dielectric layer, and the gate layer is positioned on the surface of the work function layer; the second portion of the gate structure includes: and the work function layer is positioned on the surface of the substrate, and the gate layer is positioned on the surface of the work function layer.
10. The method of forming a semiconductor device of claim 8, further comprising, after forming a gate structure on a sidewall surface of the true channel pillar: forming a dielectric layer on the isolation layer and the insulation layer, wherein the dielectric layer covers the gate structure and the true channel column; and forming a conductive structure in the dielectric layer.
11. A semiconductor device, comprising:
a substrate;
a true channel pillar on the substrate;
an isolation layer which is positioned on the substrate and covers part of the side wall of the true channel column;
a portion of the dummy channel pillars adjacent to the true channel pillars are located on the substrate and within the isolation layer, and have a top surface lower than a top surface of the isolation layer.
12. The semiconductor device according to claim 11, further comprising: an insulating layer is located on top surfaces of the portions of the pseudo-channel pillars, and the top surfaces are flush with top surfaces of the isolation layers.
13. The semiconductor device according to claim 11, further comprising: a gate structure comprising a first portion surrounding the true channel pillar and a second portion on a surface of the isolation layer on a side of the true channel pillar.
14. The semiconductor device according to claim 13, further comprising: the dielectric layer is positioned on the isolation layer and covers the grid structure and the true channel column.
15. The semiconductor device of claim 11, wherein the substrate comprises: a substrate and a source doped layer located on the substrate.
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