CN109712987A - The manufacturing method and 3D memory device of 3D memory device - Google Patents
The manufacturing method and 3D memory device of 3D memory device Download PDFInfo
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Abstract
This application discloses a kind of manufacturing method of 3D memory device and 3D memory devices.The manufacturing method of the 3D memory device includes: that the first laminated construction is formed on the substrate；Form the first channel hole for running through first laminated construction；Epitaxial layer is formed in first channel hole bottom；Sacrificial layer is filled in first channel hole；And removal is located at the sacrificial layer in first channel hole, wherein the selection between the material of the sacrificial layer and the material of the epitaxial layer is than greater than the selection ratio between polysilicon and the material of the epitaxial layer.The material of the sacrificial layer of the manufacturing method of the 3D memory device is used with epitaxial layer with the material compared with high selectivity ratio, to will not cause to damage to epitaxial layer when removing sacrificial layer, to improve the yield and reliability of 3D memory device.
Description
Technical field
The present invention relates to memory technology fields, manufacturing method and 3D memory more particularly, to 3D memory device
Part.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor, as the storage unit number of plies vertically stacked in 3D memory device is more and more, using single-groove road group (Single
Channel hole Formation, SCF) memory cell string of the structure formation with store function.In SCF technique, usually
It using polysilicon as sacrificial layer, is filled in the channel hole of lower stack structure, in the channel hole for forming top stacked structure
When, polysilicon will be used as barrier layer (stop layer), and the dry etching for avoiding upper channel hole destroys the channel hole of lower part.
During removing the polysilicon being located inside the channel hole of bottom set structure, it is easy to damage epitaxial layer (Silicon
Epitaxial Growth, SEG) or SEG dielectric layer, there is the problems such as store function failure so as to cause 3D memory device.Phase
The structure and its manufacturing method for being further improved 3D memory device are hoped, to improve the yield and reliability of 3D memory device.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of manufacturing method of 3D memory device and 3D memories
Part, wherein the first channel hole, the selection between the material of the sacrificial layer and the material of the epitaxial layer are filled using sacrificial layer
Than the selection ratio being greater than between polysilicon and the material of the epitaxial layer, to will not be made to epitaxial layer when removing sacrificial layer
At damage.
According to an aspect of the present invention, a kind of manufacturing method of 3D memory device is provided characterized by comprising serving as a contrast
The first laminated construction is formed on bottom；Form the first channel hole for running through first laminated construction；In the first channel bottom hole
Portion forms epitaxial layer；Sacrificial layer is filled in first channel hole；And removal is described in first channel hole
Sacrificial layer, wherein selection between the material of the sacrificial layer and the material of the epitaxial layer is than greater than polysilicon and described outer
Prolong the selection ratio between the material of layer.
Preferably, after forming the sacrificial layer, before the removal sacrificial layer, further includes: in first lamination
The second laminated construction is formed in structure；And form the second channel hole for running through second laminated construction, second channel
Hole is connected to first channel hole.
Preferably, first laminated construction and second laminated construction include the multiple interlayer sacrificial layers being alternately stacked
With multiple interlayer insulating films；The material of the material of the sacrificial layer and first laminated construction and second laminated construction it
Between selection than greater than selection ratio between polysilicon and first laminated construction and the material of second laminated construction.
Preferably, the material of the sacrificial layer is Spun-on carbon.
Preferably, the method for removing the sacrificial layer includes dry etching.
Preferably, the etchant for carrying out dry etching includes oxygen.
Preferably, the extension dielectric layer being located above the epitaxial layer, the material of the sacrificial layer and the extension are formed
Selection between the material of dielectric layer is than greater than the selection ratio between polysilicon and the material of the extension dielectric layer.
According to another aspect of the present invention, a kind of 3D memory device is provided characterized by comprising substrate；Positioned at described
The first rhythmic structure of the fence above substrate；The second rhythmic structure of the fence above first rhythmic structure of the fence, described first
Rhythmic structure of the fence and the second gate laminated construction include the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；With
And the first channel hole through first rhythmic structure of the fence and the second channel hole through second rhythmic structure of the fence, it is described
First channel hole is connected to second channel hole, and the bottom in first channel hole includes epitaxial layer, wherein described in formation
Before second rhythmic structure of the fence, sacrificial layer is formed inside first channel hole, after forming the second channel hole, removes institute
Sacrificial layer is stated, the selection between the material of the sacrificial layer and the material of the epitaxial layer is than greater than polysilicon and the epitaxial layer
Material between selection ratio.
The manufacturing method and 3D memory device of 3D memory device provided by the invention fill the first channel using sacrificial layer
Hole, material of the selection than being greater than polysilicon and the epitaxial layer between the material of the sacrificial layer and the material of the epitaxial layer
Between selection ratio will not damage epitaxial layer therefore when removing sacrificial layer, to improve the yield of 3D memory device and reliable
Property.
Further, the material of the material of the sacrificial layer of the 3D memory device and the first laminated construction and the second laminated construction
With high selectivity ratio, so that the first lamination knot positioned at the first channel hole side wall will not be damaged when etching the first laminated construction
Structure will not expand characteristic size；When etching the second laminated construction the second channel hole of formation, sacrificial layer will not be etched into,
The epitaxial layer below sacrificial layer will not be etched into, the yield and reliability of 3D memory device are improved.
Further, the manufacturing method of the 3D memory device removes sacrificial layer using gas phase etching, and etching speed is very fast, at
This is lower, saves process costs, improves process efficiency.
Further, the material of the sacrificial layer of the 3D memory device is Spun-on carbon, even if when removing sacrificial layer in channel
The problem of hole side wall remains sacrificial layer, will not cause current leakage improves the yield and reliability of 3D memory device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory device.
Fig. 3 a to 3h shows the sectional view in each stage of the 3D memory device manufacturing method of the embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor, as the storage unit number of plies vertically stacked in 3D memory device is more and more, using single-groove road group (Single
Channel hole Formation, SCF) memory cell string of the structure formation with store function.In SCF technique, usually
It using polysilicon as sacrificial layer, is filled in the channel hole of lower stack structure, in the channel hole for forming top stacked structure
When, polysilicon will be used as barrier layer (stop layer), and the dry etching for avoiding upper channel hole destroys the channel hole of lower part.
During removing the polysilicon being located inside the channel hole of bottom set structure, it is easy to damage epitaxial layer (Silicon
Epitaxial Growth, SEG) or SEG dielectric layer, there is the problems such as store function failure so as to cause 3D memory device.Into
One step, sacrificial layer is done using polysilicon, long-time wet etching is needed to remove polysilicon, causes equipment capacity to reduce, technique
Complexity increase and cost increase.Further, during long-time wet etching removes polysilicon, it is easy overetch
Damage is located at the laminated construction of channel hole side wall, to expand characteristic size, reduces the performance of 3D memory device.Further,
Polysilicon is removed using wet etching, is easy in channel hole side wall residual fraction polysilicon, thus worked in 3D memory device
The problem of will appear current leakage in journey.
Present inventor notices the problem of yield and reliability of above-mentioned influence 3D memory device, thus propose into
The manufacturing method and 3D memory device of the improved 3D memory device of one step.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 is respectively connected to
The respective word of wordline WL1 to WL4.
As shown in Figure 1 b, the first choice transistor Q1 of memory cell string 100 and the second selection transistor Q2 are respectively included
Grid conductor 122 and 123, memory transistor M1 to M4 respectively include grid conductor 121.Grid conductor 121,122 and 123 with deposit
The stacking order of transistor in storage unit string 100 is consistent, is separated each other using interlayer insulating film between adjacent grid conductor,
To form rhythmic structure of the fence.Further, memory cell string 100 includes channel column 110.Channel column 110 runs through gate stack knot
Structure.In the middle section of channel column 110, tunneling medium layer 112, charge storage are accompanied between grid conductor 121 and channel layer 111
Layer 113 and block media layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110,122 He of grid conductor
Block media layer 114 is accompanied between 123 and channel layer 111, to form first choice transistor Q1 and the second selection transistor
Q2。
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and block media layer
114 are made of oxide respectively, such as silica, and charge storage layer 113 is by the insulating layer comprising quantum dot or nanocrystal
Composition, such as the silicon nitride of the particle comprising metal or semiconductor, grid conductor 121,122 and 123 are made of metal, such as
Tungsten.Channel layer 111 is used to provide the channel region of control selection transistor and memory transistor, the doping type of channel layer 111 and choosing
It is identical with the type of memory transistor to select transistor.For example, for the selection transistor and memory transistor of N-type, channel layer 111
It can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Block media layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is attached
The insulating layer added, channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer 114 are formed around core
Laminated construction.
In this embodiment, first choice transistor Q1 and the second selection transistor Q2, memory transistor M1 to M4 are used
Public channel layer 111 and block media layer 114.In channel column 110, channel layer 111 provides the source-drain area of multiple transistors
And channel layer.In alternate embodiments, step independent of one another can be used, first choice transistor Q1 and the is respectively formed
The epitaxial layer and block media layer of two selection transistor Q2 and the epitaxial layer and block media layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device
A insulating layer.
The 3D memory device 200 shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage
Unit string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that
The invention is not limited thereto, and 3D memory device may include any number of memory cell strings, for example, 1024, each storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
In 3D memory device 200, memory cell string respectively includes respective channel column 110 and public grid is led
Body 121,122 and 123.Grid conductor 121,122 and 123 is consistent with the stacking order of transistor in memory cell string 100, phase
It is separated each other using interlayer insulating film between adjacent grid conductor, to form rhythmic structure of the fence 120.Interlayer is being not shown in the figure
Insulating layer.
The internal structure of channel column 110 is as shown in Figure 1 b, is no longer described in detail herein.Channel column 110 is folded through grid
Layer structure 120, and it is arranged in array, the first end of multiple channel columns 110 of same row is commonly connected to same bit line (i.e.
One of bit line BL1 to BL4), second end is commonly connected to substrate 101, and second end forms common source via substrate 100 and connects.
The grid conductor 122 of first choice transistor Q1 is divided into difference by grid line gap (gate line slit) 161
Grid line.With multiple channel columns 110 of a line grid line be commonly connected to same string selection line (i.e. string selection line SSL1 extremely
One of SSL4).
The grid conductor 121 of memory transistor M1 and M4 are respectively connected to corresponding wordline.If memory transistor M1 and
The grid conductor 121 of M4 is divided into different grid lines by grid line gap 161, then the grid line of same level is via respective conductive logical
Road 131 reaches interconnection layer 132, thus it is interconnected amongst one another, then same wordline (i.e. wordline WL1 is connected to via conductive channel 133
One of to WL4).
The grid conductor of second selection transistor Q2 links into an integrated entity.If the grid conductor of the second selection transistor Q2
123 are divided into different grid lines by grid line gap 161, then grid line reaches interconnection layer 132 via respective conductive channel 131, from
And it is interconnected amongst one another, then via with the being connected to same selection line GSL of conductive channel 133.
The internal structure of false channel column and channel column 110 can be identical or different, and at least across in rhythmic structure of the fence
At least part grid conductor.In final 3D memory device, false channel column is not connected with bit line, to only mention
It is acted on for mechanical support, without being used to form selection transistor and memory transistor.Therefore, false channel column is not formed effectively
Storage unit.
Fig. 3 a to 3h shows the sectional view in each stage of the 3D memory device manufacturing method of the embodiment of the present invention.Described section
Face figure is intercepted along the AA line in Fig. 2.
This method starts from forming the first laminated construction 150 in semiconductor substrate 101 and through the first lamination knot
The semiconductor structure in the first channel hole 109 of structure 150, the bottom in the first channel hole 109 include epitaxial layer 116 and extension dielectric layer
117, as shown in Figure 3a.Semiconductor structure includes semiconductor substrate 101 and the first laminated construction 150 thereon.First lamination knot
Structure 150 includes the multiple interlayer insulating films 151 and multiple interlayer sacrificial layers 152 being alternately stacked.In this embodiment, semiconductor serves as a contrast
Bottom 101 is, for example, monocrystalline substrate, and interlayer insulating film 151 is for example made of silica, and interlayer sacrificial layer 152 is for example by silicon nitride
Composition.Epitaxial layer 116 is, for example, monocrystalline silicon or polysilicon, and extension dielectric layer 117 is, for example, silica.The 3D of the present embodiment is stored
Device includes at least the laminated construction of two-layer laminate, and the present embodiment is by taking two layer stacked structures as an example, i.e., including substrate 101 and successively
It is stacked in the first laminated construction 150 and the second laminated construction 250 of 101 top of substrate (referring to Fig. 3 d).
Further, sacrificial layer 180 is filled in the first channel hole 109, as shown in Figure 3b.In the first channel hole 109
Sacrificial layer 180 is filled, can be prevented in the subsequent process, channel hole 109 is collapsed, so that being located at the function of channel hole side wall
Layer can not normally form.It can simultaneously serve as hard mask layer, keep the surfacing of the first laminated construction 150, it is smooth to be formed
The second laminated construction.In this embodiment, the material of sacrificial layer 180 includes carbon, for example, Spun-on carbon (Spin-onCarbon,
SOC) layer forms spin-on sacrificial layer for example, by using the mode of spin coating.With chemical vapor deposition (Chemical Vapor
Deposition, CVD) carbon phase ratio, Spun-on carbon cost is lower.
Further, sacrificial layer 180 is carried out back carving (Etch back), as shown in Figure 3c.Sacrificial layer 180 is returned
When quarter, anisotropic etching can be used, for example, by using dry etching, such as ion beam milling etching, plasma etching, reactive ion erosion
It carves, laser ablation.For example, by control etching period, so that the interlayer being etched in positioned at 150 the top of the first laminated construction is sacrificial
The surface of domestic animal layer 152 nearby stops.
Further, the second laminated construction 250 is formed above the first laminated construction 150, as shown in Figure 3d.It is folded first
150 top of layer structure successively alternately deposits multiple interlayer insulating films 251 and multiple sacrificial layers 252 form the second laminated construction
250.Second laminated construction 250 is similar with the first laminated construction 150, and the second laminated construction 250 includes the multiple layers being alternately stacked
Between insulating layer 251 and multiple sacrificial layers 252, layer insulation, 251 are for example made of silica, and sacrificial layer 252 is for example by silicon nitride
Composition.
Further, the second channel hole 209 is formed in the second laminated construction 250, as shown in Figure 3 e.First channel hole
209 are located at the top of sacrificial layer 180 and are connected to the first channel hole 109.Second channel hole is formed using anisotropic etching
209, for example, by using dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation.For example, passing through
Etching period is controlled, so that the surface of etching sacrificial layer 180 nearby stops.
Further, removal is located at the sacrificial layer 180 in the first channel hole 109, as illustrated in figure 3f.It is lost for example, by using gas phase
The sacrificial layer 180 that removal is located in the first channel hole 109 is carved, O can be used in gas phase etching2As etchant.It is etching
In step, etchant fills the second channel hole 209.The end of the sacrificial layer 180 in the first channel hole 109 is exposed to the second channel hole
In 209 opening, therefore, sacrificial layer touches etchant.Etchant gradually etches sacrificial layer by the opening in the second channel hole 209
180.Since the high selectivity ratio of etchant will not be to the layer in the first laminated construction 180 when this is etched in removal sacrificial layer 180
Between insulating layer 151 and interlayer sacrificial layer 152 cause to damage.
Further, blocking is sequentially formed in the channel hole that the first channel hole 109 and the second channel hole are formed by connecting to be situated between
Matter layer 114, charge storage layer 113, tunneling medium layer 112 and channel layer 111 (referring to Fig. 1 b) are such as schemed with forming channel column 110
Shown in 3g.Block media layer 114, electricity are sequentially formed in the channel hole that the first channel hole 109 and the second channel hole are formed by connecting
Lotus accumulation layer 113, tunneling medium layer 112 and channel layer 111, to form ONOP (oxide-nitride-oxide-polysilicon)
Laminated construction.Opening, and deposit polycrystalline silicon are formed in the ONOP lamination for being located at channel column bottom, make channel layer 111 and extension
Layer 116 connects.It is appreciated that the method for forming ONOP laminated construction is not limited to this, any the one of the prior art can be used
Kind forms ONOP laminated construction.In a preferred embodiment, oxide layer 115 can also be formed in 110 core of channel column.It is substituting
Embodiment in, the oxide layer positioned at 110 core of channel column can also be saved.
Further, the shape in the insulating laminate structure that the first laminated construction 150 and the second laminated construction 250 collectively form
At grid line gap 161 (referring to fig. 2), the interlayer sacrificial layer in insulating laminate structure is removed to form sky via grid line gap 161
Chamber, and grid conductor 121,122,123 is formed using metal layer filling cavity, to form rhythmic structure of the fence 120 (referring to figure
2), as illustrated in figure 3h.
After interlayer sacrificial layer is substituted for grid conductor, grid conductor is further attached to wordline.In order to be formed from grid
Pole conductor reaches the conductive channel of wordline, and multiple interlayer sacrificial layers are for example patterned step-like, that is, each interlayer sacrificial layer
Marginal portion provides electrical connection area relative to the interlayer sacrificial layer exposure of top.In the patterning step of multiple interlayer sacrificial layers
Later, insulating laminate structure can be covered using dielectric layer.
When forming grid line gap 161, anisotropic etching can be used, is lost for example, by using dry etching, such as ion beam milling
Quarter, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in semiconductor lining
The surface at bottom 101 nearby stops.
In this embodiment, grid conductor is divided into a plurality of grid line by grid line gap 161.For this purpose, grid line gap 161 is run through
Insulating laminate structure.
It is folded using isotropic etching removal insulation using grid line gap 161 as etchant channel when forming cavity
Interlayer sacrificial layer in layer structure is to form cavity.Isotropic etching can be using wet etching or the gas phase erosion of selectivity
It carves.Use etching solution as etchant in wet etching, wherein in the etch solution by semiconductor structure submergence.In gas
Mutually use etching gas as etchant in etching, wherein semiconductor structure is exposed in etching gas.
The feelings that interlayer insulating film and interlayer sacrificial layer in insulating laminate structure are made of silica and silicon nitride respectively
Under shape, C can be used in gas phase etching using phosphoric acid solution as etchant in wet etching4F8、C4F6、CH2F2
And O2One of or it is a variety of.In an etching step, etchant is full of grid line gap 161.Interlayer in insulating laminate structure is sacrificial
The end of domestic animal layer is exposed in the opening in grid line gap 161, and therefore, interlayer sacrificial layer touches etchant.Etchant is by grid line
The opening in gap 161 is gradually to the etched inside interlayer sacrificial layer of insulating laminate structure.Due to the selectivity of etchant, the etching
Interlayer sacrificial layer is removed relative to the interlayer insulating film in insulating laminate structure.
When forming grid conductor, using grid line gap 161 as deposit channel, using atomic layer deposition (ALD),
Metal layer is filled in grid line gap 161 and cavity.
In this embodiment, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, hexafluoro
Change tungsten WF6, the reducing gas of use is, for example, silane SiH4Or diborane B2H6.In the atomic layer deposition the step of, hexafluoro is utilized
Change tungsten WF6With silane SiH4Reaction product chemisorption obtain tungsten material realize deposition process.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (8)
1. a kind of manufacturing method of 3D memory device characterized by comprising
The first laminated construction is formed on the substrate；
Form the first channel hole for running through first laminated construction；
Epitaxial layer is formed in first channel hole bottom；
Sacrificial layer is filled in first channel hole；And
Removal is located at the sacrificial layer in first channel hole,
Wherein, the selection between the material of the sacrificial layer and the material of the epitaxial layer is than greater than polysilicon and the epitaxial layer
Material between selection ratio.
2. the manufacturing method according to claim 1, which is characterized in that after forming the sacrificial layer, removal it is described sacrificial
Before domestic animal layer, further includes:
The second laminated construction is formed on first laminated construction；And
The the second channel hole for running through second laminated construction is formed, second channel hole is connected to first channel hole.
3. manufacturing method according to claim 2, which is characterized in that
First laminated construction and second laminated construction include the multiple interlayer sacrificial layers and multiple interlayers being alternately stacked
Insulating layer；
Selection between the material of the sacrificial layer and first laminated construction and the material of second laminated construction is than big
Selection ratio between polysilicon and first laminated construction and the material of second laminated construction.
4. the manufacturing method according to claim 1, which is characterized in that the material of the sacrificial layer is Spun-on carbon.
5. the manufacturing method according to claim 1, which is characterized in that the method for removing the sacrificial layer includes dry method erosion
It carves.
6. manufacturing method according to claim 5, which is characterized in that the etchant for carrying out dry etching includes oxygen.
7. the manufacturing method according to claim 1, which is characterized in that form the extension medium being located above the epitaxial layer
Layer, the selection between the material of the sacrificial layer and the material of the extension dielectric layer is than greater than polysilicon and the extension medium
Selection ratio between the material of layer.
8. a kind of 3D memory device characterized by comprising
Substrate；
The first rhythmic structure of the fence above the substrate；
The second rhythmic structure of the fence above first rhythmic structure of the fence, first rhythmic structure of the fence and the second gate
Laminated construction includes the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；And
The first channel hole through first rhythmic structure of the fence and the second channel hole through second rhythmic structure of the fence, institute
The first channel hole to be stated to be connected to second channel hole, the bottom in first channel hole includes epitaxial layer,
Wherein, before forming second rhythmic structure of the fence, sacrificial layer is formed inside first channel hole, is forming the
After two channel holes, the sacrificial layer is removed, the selection between the material of the sacrificial layer and the material of the epitaxial layer is than big
Selection ratio between polysilicon and the material of the epitaxial layer.
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| CN201811440088.3A CN109712987A (en) | 2018-11-29 | 2018-11-29 | The manufacturing method and 3D memory device of 3D memory device |
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