CN109686739A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109686739A CN109686739A CN201811615535.4A CN201811615535A CN109686739A CN 109686739 A CN109686739 A CN 109686739A CN 201811615535 A CN201811615535 A CN 201811615535A CN 109686739 A CN109686739 A CN 109686739A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The 3D memory device includes: rhythmic structure of the fence, including the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；Semiconductor layer, on the surface of the bottommost interlayer insulating film of the multiple interlayer insulating film；And multiple channel columns, through the rhythmic structure of the fence and extend to the semiconductor layer, wherein, the bottom end of the multiple channel column is flushed with the surface of the bottommost interlayer insulating film, and the semiconductor layer includes the public source zone being electrically connected with the bottom end of the channel column.The manufacturing method of the 3D memory device, which is included in be formed after channel column, uses semiconductor layer to substitute the first sacrificial layer to provide public source zone, so as to the step of saving selective silicon epitaxial growth, to reduce manufacturing cost and improve mass production capabilities, and device performance is improved since the bottom end of channel column flushes.
Description
Technical field
The present invention relates to memory technologies, more particularly, to a kind of 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
The 3D memory device of NAND structure includes: semiconductor substrate, the rhythmic structure of the fence in semiconductor substrate, runs through
The through-hole and conductive channel of rhythmic structure of the fence are led using the grid that rhythmic structure of the fence provides selection transistor and memory transistor
Body layer provides the channel layer and gate medium lamination of selection transistor and memory transistor using through-hole, and uses conductive channel
Realize the interconnection of memory cell string.In the manufacturing method of 3D memory device, through-hole is formed using etching, the through-hole is folded through grid
Layer structure, and reach the projected depth of semiconductor substrate.After the etching, using selective silicon epitaxial growth (Selective
Epitaxial Growth, is abbreviated as SEG) packing material is formed in the bottom of through-hole, lead to threshold so that the depth of through-hole is inconsistent
The non-uniform problem of threshold voltage.
However, SEG technique is not only high complexity and high-cost technique, and the height of the packing material formed can also
It can be non-uniform, and the interface of formation out-of-flatness leads to sheet resistance height between semiconductor substrate and channel column.Therefore,
SEG technique leads to the difficulty of batch production and the reduction of device performance.
Therefore, expect to use new manufacturing process to replace SEG technique to improve mass production capabilities and device performance.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, wherein is forming channel column
Semiconductor layer is used to substitute the first sacrificial layer to provide public source zone later.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: rhythmic structure of the fence, including be alternately stacked
Multiple gate conductor layers and multiple interlayer insulating films；Semiconductor layer, positioned at the bottommost interlayer of the multiple interlayer insulating film
On the surface of insulating layer；And multiple channel columns, through the rhythmic structure of the fence and extend to the semiconductor layer, wherein institute
The bottom end for stating multiple channel columns is flushed with the surface of the bottommost interlayer insulating film, and the semiconductor layer include with it is described
The public source zone of channel column electrical connection, the semiconductor layer are sedimentary.
Preferably, the semiconductor layer is the sedimentary on the surface of the bottommost interlayer insulating film.
Preferably, the semiconductor layer is made of polysilicon.
Preferably, further includes: multiple bit lines are connected to respective column ditch in the multiple channel column via the first conductive channel
The top of road column；A plurality of wordline is connected to the intermediate gate conductor layer of the multiple gate conductor layer via the second conductive channel；
String selection line and source selection line, are connected to the multiple gate conductor layer via third conductive channel and the 4th conductive channel respectively
In top gate conductor layer and bottommost gate conductor layer；And source electrode line, it is connected to via the 4th conductive channel described
Public source zone.
Preferably, further includes: supplemental dielectric layer covers the top interlayer insulating film of the multiple interlayer insulating film, and
And the covering multiple bit lines, a plurality of wordline, the string selection line, the source selection line and the source electrode line.
Preferably, the Free Surface of the supplemental dielectric layer further includes as the first bonding face, the 3D memory device
Cmos circuit chip, one of the cmos circuit chip each other relative first surface and second surface are used as the second bonding face,
First bonding face and second bonding face bond together.
According to another aspect of the present invention, a kind of method for manufacturing 3D memory device is provided, comprising: on the support substrate
Form the first sacrificial layer；Form rhythmic structure of the fence on the first sacrificial layer, the rhythmic structure of the fence include be alternately stacked it is multiple
Gate conductor layer and multiple interlayer insulating films, described in the surface contact of the bottommost interlayer insulating film of the multiple interlayer insulating film
First sacrificial layer；The multiple channel columns for running through the rhythmic structure of the fence are formed, it is sacrificial that the multiple channel column extends to described first
In domestic animal layer；Remove the support substrate；First sacrificial layer is removed, with the bottommost layer of the multiple interlayer insulating film of exposure
Between insulating layer surface；Semiconductor layer is formed on the surface of the bottommost interlayer insulating film；And in the semiconductor layer
Middle formation public source zone, wherein the bottom end of the multiple channel column is flushed with the surface of the bottommost interlayer insulating film, and
It is electrically connected with the public source zone.
Preferably, the support substrate selected from any one of metal, ceramics, glass, organic material by forming.
Preferably, first sacrificial layer is made of any one of polysilicon, metal, ceramics, glass, organic material.
Preferably, the sedimentary that the semiconductor layer is made of polysilicon.
Preferably, the step of the step of removing the support substrate and first sacrificial layer, respectively includes including wet process erosion
Quarter, dry etching, chemical-mechanical planarization or above-mentioned process combination.
Preferably, when removing the support substrate, first sacrificial layer is as stop-layer.
Preferably, when removing first sacrificial layer, the bottommost interlayer insulating film of the multiple interlayer insulating film is made
For stop-layer.
Preferably, while removing first sacrificial layer or later, the multiple channel column is removed described first
Extension in sacrificial layer.
Preferably, when removing first sacrificial layer, the bottom end of the multiple channel column is exhausted in the bottommost interlayer
The surface of edge layer is prominent, and the method also includes the protrusion of the multiple channel column is removed using additional chemical-mechanical planarization
Portion.
Preferably, the step of forming rhythmic structure of the fence includes: to be formed before forming the multiple channel column and sacrifice lamination
Structure, the sacrifice laminated construction include multiple second sacrificial layers, the multiple second sacrificial layer and the multiple layer insulation
Layer is alternately stacked；It is formed through the multiple through-holes for sacrificing laminated construction, the multiple through-hole extends to described first and sacrifices
In layer, after forming the multiple channel column, metal layer is used to replace the multiple second sacrificial layer the multiple to be formed
Gate conductor layer.
Preferably, further includes: formed on the surface of the top interlayer insulating film of the multiple interlayer insulating film additional exhausted
Edge layer；And multiple bit lines, a plurality of wordline, string selection line and source selection line and source electrode are formed in the supplemental dielectric layer
Line.
Preferably, further includes: by cmos circuit chip bonding on the Free Surface of the supplemental dielectric layer, to form key
Seaming element.
3D memory device according to an embodiment of the present invention and its manufacturing method are formed in support substrate and the first sacrificial layer
Then channel column removes substrate and the first sacrificial layer, semiconductor layer is used to substitute the first sacrificial layer to provide public source zone.The system
It makes method and provides the wider space of the corresponding through-hole of channel column using the first sacrificial layer, make while removing the first sacrificial layer
The bottom end for obtaining channel column flushes, so as to save SEG technique to reduce manufacturing cost and raising mass production capabilities.
Further, the bottom end of multiple channel columns flushes, even if the depth-to-width ratio of the corresponding through-hole of channel column is different, channel
The extension depth of column is also identical, to reduce the fluctuation of threshold voltage.Moreover, the bottom end of channel column and connecing for semiconductor layer
Contacting surface is smooth, so as to reduce interface electric leakage and the source and drain resistance of channel column bottom end, improves device performance.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
The perspective view and sectional view of 3D memory device according to an embodiment of the present invention is shown respectively in Fig. 2 a and 2b.
Fig. 3 to Figure 11 shows the schematic diagram in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Term " Free Surface " refers to cmos circuit and storage unit battle array
The respective surface opposite with the two contact surface is arranged, term " bonding face " refers to that both cmos circuit and memory cell array contact
Surface, cmos circuit and memory cell array using both bonding face realize mechanical connection and electrical connection.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the present embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line (Bit-Line, BL), and second end is connected to
Source electrode line (Source Line, SL).Memory cell string 100 is more including being sequentially connected in series between the first end and a second end
A transistor, comprising: first choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.First choice
The grid of transistor Q1 is connected to string selection line (Selection Gate for Drain, SGD), the second selection transistor Q2's
Grid is connected to source selection line (Selection Gate for Source, SGS).The grid of memory transistor M1 to M4 is distinguished
It is connected to the respective word of wordline (Word-Line) WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include gate conductor layer 122 and 123,
Memory transistor M1 to M4 respectively includes gate conductor layer 121.In gate conductor layer 121,122 and 123 and memory cell string 100
Transistor stacking order it is consistent, separated each other using interlayer insulating film between adjacent gate conductor layer, to form grid
Laminated construction.Further, memory cell string 100 includes channel column 110.Channel column 110 is adjacent with rhythmic structure of the fence or passes through
Wear rhythmic structure of the fence.In the middle section of channel column 110, tunneling medium layer is accompanied between gate conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.In the ideal case, in channel column
110 both ends accompany gate dielectric layer 114 between gate conductor layer 122 and 123 and channel layer 111, to form selection transistor
Q1 and Q2.But since technique limits, tunneling medium layer can also be accompanied between gate conductor layer 122 and 123 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114.
In the present embodiment, channel layer 111 is for example made of polysilicon, and tunneling medium layer 112 and gate dielectric layer 114 are distinguished
It is made of oxide, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, example
The silicon nitride of particle such as comprising metal or semiconductor, gate conductor layer 121,122 and 123 is made of metal, such as tungsten.Ditch
Channel layer 111 is for providing the channel region of selection transistor and memory transistor, the doping type and selection transistor of channel layer 111
It is identical with the type of memory transistor.For example, the selection transistor and control transistor, channel layer 111 for N-type can be N
The polysilicon of type doping.
In the present embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In the present embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of substitution
Example in, can use step independent of one another, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel column 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling effect
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, source selection line SGS is biased to greatly
About zero volts, so that the selection transistor Q2 corresponding to source selection line SGS is disconnected, string selection line SGD is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SGD.Further, bit line BL2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 a shows the perspective view of 3D memory device according to an embodiment of the present invention, and Fig. 2 b shows the line A-A along Fig. 2 a
Sectional view.For the sake of clarity, each insulating layer in 3D memory device is not shown in Fig. 2 a and 2b.
3D memory device 200 includes the multiple channel columns 100 for being arranged in array structure.Memory cell string 100 includes channel
The middle section of column 110 and its corresponding gate conductor layer.The heap of transistor in gate conductor layer and memory cell string 100
Sequence consensus is folded, is separated each other using interlayer insulating film between adjacent gate conductor layer.The internal structure of channel column 110 referring to
Fig. 1 b accompanies tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 between channel layer 111 and gate conductor layer.
The 3D memory device 200 of the present embodiment includes that 4*4 amounts to 16 memory cell strings 100, each memory cell string 100
Including 4 storage units, to be respectively formed the storage array that 4*4*4 amounts to 64 storage units.It is appreciated that the present invention is not
It is limited to this, which may include any number of memory cell strings, for example, 1024, in each memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.In the present embodiment, semiconductor layer 101 includes common source
The bottom end in area, the channel column 110 of the multiple memory cell string 100 all extends in public source zone.
Multiple well regions are formed in semiconductor layer 101.The multiple well region for example including deep N-well 102, be located at deep N-well 102
In high pressure p-well 103, with the adjacent high pressure N trap 105 of high pressure p-well 103, the P+ doped region 104 in high pressure p-well 103,
N+ doped region 106 in high pressure N trap 105.In this embodiment, public source zone of the high pressure p-well 103 as channel column is high
Press N trap 105 for the precharge to public source zone, P+ doped region 104 and N+ doped region 106 connect respectively as contact zone to reduce
Electric shock resistance.Public source zone of the high pressure p-well 103 as multiple channel columns.
The 3D memory device 200 of the present embodiment further include for provide electrical connection multiple bit lines 131, a plurality of wordline 141,
String selection line 142, source selection line 143, source electrode line 144.In array structure, positioned at multiple memory cell strings 100 of same row
It is connected to same bit line 131.It is formed with embolism 132 on the top of channel column 110, is used between bit line 131 and embolism 132
Conductive channel 133 is electrically connected.In array structure, the storage unit of the same level of multiple memory cell strings 100 shares same
A gate conductor layer 121, gate conductor layer 121 are connected to a corresponding wordline 141 via conductive channel 145.Further, grid
The top gate conductor layer 122 and bottommost gate conductor layer 123 of laminated construction are respectively used to first choice transistor and
Two selection transistors are connected to string selection line 142 and source selection line 143 via conductive channel 145 respectively.In semiconductor layer 101
Public source zone be connected to source electrode line 144 via conductive channel 145.
In some preferred embodiments, the marginal portion of multiple gate conductor layers 121 to 123 of rhythmic structure of the fence 120
Form step structure.That is, the marginal portion of each gate conductor layer is electrically connected relative to the gate conductor layer exposure of top with providing
Meet area.The marginal portion of gate conductor layer is connected to a corresponding wordline 141 via conductive channel 145.
In some preferred embodiments, the 3D memory device of the present embodiment further includes the step in multiple gate conductor layers
The false channel column that structural region is formed, for providing mechanical support effect.
Fig. 3 to Figure 11 shows the schematic diagram in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
It is described in detail below in conjunction with manufacturing method of the Fig. 3 to Figure 11 to invention memory construction.
Directly form in semiconductor substrate that the method for rhythmic structure of the fence is different, and method of the invention starts from from the prior art
Support substrate 201 and the first sacrificial layer 202 in support substrate 201.
The effect of support substrate 201 is to provide the support surface for the first sacrificial layer, can satisfy surface smoothness and
The requirement of the uniformity and temperature tolerance.For example, support substrate 201 can be made of any one following material: metal, pottery
Porcelain, glass, organic material.The effect of first sacrificial layer 202 is to provide the wider space of through-hole, can satisfy selective etch and
The requirement of chemical-mechanical planarization (Chemical Mechanical Planarization, CMP) and temperature tolerance.Example
Such as, the first sacrificial layer 202 can be made of any one following material: polysilicon, metal, ceramics, glass, organic material.
It is formed on the first sacrificial layer 202 and sacrifices laminated construction, as shown in Figure 3.
In this step, for example, by using chemical vapor deposition process (Chemical Vapor Deposition, CVD), object
Physical vapor deposition technique (Physical Vapor Deposition, PVD) successively forms multiple layers on the first sacrificial layer 202
Between insulating layer 203 (integrally being shown in figure) and multiple second sacrificial layers 204, wherein the material packet of multiple interlayer insulating films 203
Oxide, such as silica are included, the material of multiple second sacrificial layers 204 includes nitride, such as silicon nitride.
Preferably, the marginal portion of multiple second sacrificial layers 204 forms step structure, that is, the side of each second sacrificial layer
Second sacrificial layer exposure of the edge split-phase for top.In subsequent steps, multiple second sacrificial layers 204 will be replaced into multiple
Gate conductor layer 121 to 123, thus, the marginal portion of multiple gate conductor layers 121 to 123 retains step structure to provide electricity
Bonding pad.
Then, it is formed through the through-hole 205 for sacrificing laminated construction, as shown in Figure 4.
In this step, for example, forming photoresist mask on sacrificing laminated construction.The photoresist mask shape
The corresponding patterns of openings of Cheng Youyu through-hole.Then, it using anisotropic etching, is lost for example, by using dry etching, such as ion beam milling
Quarter, plasma etching, reactive ion etching, laser ablation remove multiple 203 Hes of interlayer insulating film via photoresist mask
The expose portion of multiple second sacrificial layers 204 forms multiple through-holes 205.After an etching step, it dissolves or is ashed using solvent
Remove photoresist mask.
In the present embodiment, by controlling etching period, stop so that being etched in the first sacrificial layer 202.Alternatively, it props up
Support substrate 201 and the first sacrificial layer 202 can be made of different materials, and support substrate 201 is used as stop-layer.
In the present embodiment, various structures component will be formed in through-hole 205, for example, channel column, false channel column, running through battle array
Column contact TAC, any one in array side wall TAB.It is consistent with the shape of various structure members, in different location shape
At the patterns of openings of through-hole 205 may be different, as a result, in the depth-to-width ratio (aspect for the through-hole 205 that different location is formed
Ratio) also not identical, so as to extend different depth in the first sacrificial layer 202.
Then, channel column 110 and embolism 132 are formed in through-hole 205, and the second sacrificial layer 204 is replaced as grid
Conductor layer 121 to 123, as shown in Figure 5.
The step of forming channel column includes multiple depositions and patterning step.Channel column 110 fills at least part through-hole
205.Channel column 110 includes the channel layer 111 extended in the first sacrificial layer 202 from upper part.As shown, channel column 110
Including tunneling medium layer 112, charge storage layer 113 and the block media layer 114 being sequentially stacked on channel layer 111.
Preferably, which further includes forming embolism 132.After forming channel column 110, etch-back is carried out, is existed again
Recess is formed in through-hole 205.Then, conductive material is filled in the valley, to form embolism 132.It is used to form embolism 132
Conductive material includes tungsten or DOPOS doped polycrystalline silicon.In final 3D memory device, the tip contact embolism 132 of channel column 110.
Preferably, using technique identical with channel column 110, false channel column is formed in a part of through-hole 205.Using with
The common or independent step of channel column 110 forms through array contact TAC in a part of through-hole 205, runs through array side wall
TAB。
The step of second sacrificial layer is replaced as gate conductor layer includes forming grid line gap, etching the second sacrificial layer of removal
Gate conductor layer is formed with deposition.
When forming grid line gap, anisotropic etching can be used, for example, by using dry etching, as ion beam milling etching,
Plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in the first sacrificial layer
202 surface nearby stops.
When etching removes the second sacrificial layer, using grid line gap as etchant channel, gone using isotropic etching
Except the second sacrificial layer in insulating laminate structure to form cavity.Isotropic etching can be using the wet etching of selectivity
Or gas phase etching.Use etching solution as etchant in wet etching, wherein semiconductor structure is immersed in etching solution
In.Use etching gas as etchant in gas phase etching, wherein semiconductor structure is exposed in etching gas.Insulation
The end of the second sacrificial layer in laminated construction is exposed in the opening in grid line gap, and therefore, sacrificial layer touches etchant.Erosion
Agent is carved from the opening in grid line gap gradually to the second sacrificial layer of etched inside of insulating laminate structure.Due to the selection of etchant
Property, which removes the second sacrificial layer relative to the interlayer insulating film in insulating laminate structure.
When forming gate conductor layer, using grid line gap as deposit channel, using atomic layer deposition (ALD),
Metal layer is filled in grid line gap and cavity, to form gate conductor layer.In this embodiment, metal layer is for example by tungsten group
At.The forerunner source used in atomic layer deposition is, for example, tungsten hexafluoride WF6, the reducing gas of use be, for example, silane SiH4 or
Diborane B2H6.In the atomic layer deposition the step of, the chemisorption of tungsten hexafluoride WF6 and the reaction product of silane SiH4 are utilized
It obtains tungsten material and realizes deposition process.After forming gate conductor layer, such as the metal layer in removal grid line gap, so that not
Gate conductor layer with level is separated from each other.
Then, the conductive channel for forming bit line 131 above rhythmic structure of the fence, bit line 131 being connected with embolism 132
133 and for providing the insulating layer 206 of bonding surface, as shown in Figure 6.
Although insulating layer 206 shown in figure is single layer, actually insulating layer 206 can be multilayered structure, example
Such as, including first layer for providing the corresponding through-hole of conductive channel 133 and being used to support the surface and second of bit line 131
Layer is for covering bit line 131.One side surface of insulating layer 206 is in contact with the top layer 206 of rhythmic structure of the fence, the other side
Surface is Free Surface, for being used as bonding face in a subsequent step.
In this embodiment, the conductive material for being used to form bit line 131 and conductive channel 133 includes tungsten or doped polycrystalline
Silicon, the material for being used to form insulating layer 206 includes silicon oxide or silicon nitride.
Include rhythmic structure of the fence and channel column in the semiconductor structure that the step is formed, can be used as storage array chip into
One step executes subsequent process steps.
Then, as preferred step, storage array chip is bonded with cmos circuit chip 301, forms bonding component,
As shown in Figure 7.
Cmos circuit chip 301 is for providing the peripheral circuit being written and read to memory cell array, for example, CMOS
The inside of circuit chip 301 includes transistor and wiring layer etc. (being not shown).One side surface of cmos circuit chip 301
As bonding face, it is bonded face contact with storage array chip and realizes bonding.Another side surface shape of cmos circuit chip 301
At there is pad 302, for being electrically connected between the internal circuit and external circuit by cmos circuit chip.It is appreciated that
The internal structure and its formation process of cmos circuit chip 301 be it is known, this will not be detailed here.
Then, overturning bonding component, be bonded component in support substrate 201 Free Surface upward, be then thinned with
Support substrate 201 is removed, as shown in Figure 8.
Technique for removing support substrate 201 includes but is not limited to wet etching, dry etching, chemical machinery plane
Change or above-mentioned process combination.In the case of support substrate 201 and the first sacrificial layer 202 are made of different materials, Ke Yili
Use the difference of the etching characteristic of the two by the first sacrificial layer 202 as stop-layer.In support substrate 201 and the first sacrificial layer 202
In the case of being made of identical material, etching process can be controlled by the time to remove support substrate 201.
Then, the first sacrificial layer 202 is further removed, and the bottom end of channel column 110 is planarized, such as Fig. 9 institute
Show.
Technique for removing the first sacrificial layer 202 includes but is not limited to wet etching, dry etching, chemical machinery plane
Change or above-mentioned process combination.It, can be using the layer of storage array chip in bonding component when removing the first sacrificial layer 202
Between insulating layer 203 be used as stop-layer.
In the case of using chemical-mechanical planarization, channel column 110 is removed simultaneously positioned at first with the first sacrificial layer 202
Part in sacrificial layer 202.In the case of using wet etching or dry etching, after removing the first sacrificial layer 202, into
One step removes the protrusion of channel column 100 using mechanical planarization.
After this step, the bottom end of channel column 110 is exposed on the surface of the interlayer insulating film 203 in bonding component.
Then, deposition forms semiconductor layer on the surface of the interlayer insulating film 203 of storage array chip in bonding component
101, as shown in Figure 10, and multiple well regions are formed in semiconductor layer 101, as shown in figure 11.
The sedimentary that semiconductor layer 101 is formed for example, by using sputtering, and multiple well regions are formed for example, by using ion implanting.
Semiconductor layer 101 is for example made of polysilicon.The multiple well regions formed in semiconductor layer 101 are for example including deep N-well 102, position
High pressure p-well 103 and the adjacent high pressure N trap 105 of high pressure p-well 103, the P+ in high pressure p-well 103 in deep N-well 102
Doped region 104, the N+ doped region 106 in high pressure N trap 105.In this embodiment, public affairs of the high pressure p-well 103 as channel column
Common source area, high pressure N trap 105 is for the precharge to public source zone, and P+ doped region 104 and N+ doped region 106 are respectively as contact
Area is to reduce contact resistance.Public source zone of the high pressure p-well 103 as multiple channel columns.
In the above-described embodiment, the bit line of 3D memory device and its being electrically connected between channel column are described.The 3D
Memory device can also include the wordline being formed simultaneously with bit line, string selection line, source selection line, source electrode line.As described above, word
Line, string selection line, source selection line are electrically connected with corresponding gate conductor layer respectively, and source electrode line is electrically connected with public source zone.
In the above-described embodiment, describing 3D memory device includes the storage array chip being bonded together and CMOS electricity
Road chip.In alternate embodiments, which only includes storage array chip, and the mode of component is bonded with formation
Difference forms pad on the surface of storage array chip, and is electrically connected via pad with external cmos circuit chip.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (18)
1. a kind of 3D memory device, comprising:
Rhythmic structure of the fence, including the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；
Semiconductor layer, on the surface of the bottommost interlayer insulating film of the multiple interlayer insulating film；And
Multiple channel columns through the rhythmic structure of the fence and extend to the semiconductor layer,
Wherein, the bottom end of the multiple channel column is flushed with the surface of the bottommost interlayer insulating film, and the semiconductor
Layer includes the public source zone being electrically connected with the channel column, and the semiconductor layer is sedimentary.
2. 3D memory device according to claim 1, wherein the semiconductor layer is the bottommost interlayer insulating film
Sedimentary on surface.
3. 3D memory device according to claim 1, wherein the semiconductor layer is made of polysilicon.
4. 3D memory device according to claim 1, further includes:
Multiple bit lines are connected to the top of respective column channel column in the multiple channel column via the first conductive channel；
A plurality of wordline is connected to the intermediate gate conductor layer of the multiple gate conductor layer via the second conductive channel；
String selection line and source selection line, are connected to the multiple grid via third conductive channel and the 4th conductive channel respectively and lead
Top gate conductor layer and bottommost gate conductor layer in body layer；And
Source electrode line is connected to the public source zone via the 4th conductive channel.
5. 3D memory device according to claim 4, further includes:
Supplemental dielectric layer, covers the top interlayer insulating film of the multiple interlayer insulating film, and cover the multiple bit lines,
The a plurality of wordline, the string selection line, the source selection line and the source electrode line.
6. 3D memory device according to claim 5, wherein the Free Surface of the supplemental dielectric layer is as the first bonding
Face, the 3D memory device further include cmos circuit chip, the cmos circuit chip each other relative first surface and second
One of surface is used as the second bonding face, and first bonding face and second bonding face bond together.
7. a kind of method for manufacturing 3D memory device, comprising:
The first sacrificial layer is formed on the support substrate；
Form rhythmic structure of the fence on the first sacrificial layer, the rhythmic structure of the fence include multiple gate conductor layers for being alternately stacked with
The surface of multiple interlayer insulating films, the bottommost interlayer insulating film of the multiple interlayer insulating film contacts first sacrificial layer；
The multiple channel columns for running through the rhythmic structure of the fence are formed, the multiple channel column extends in first sacrificial layer；
Remove the support substrate；
First sacrificial layer is removed, with the surface of the bottommost interlayer insulating film of the multiple interlayer insulating film of exposure；
Semiconductor layer is formed on the surface of the bottommost interlayer insulating film；And
Public source zone is formed in the semiconductor layer,
Wherein, the bottom end of the multiple channel column is flushed with the surface of the bottommost interlayer insulating film, and with it is described public
Source region electrical connection.
8. according to the method described in claim 7, wherein, the support substrate is by being selected from metal, ceramics, glass, organic material
Any one of composition.
9. according to the method described in claim 7, wherein, first sacrificial layer is by polysilicon, metal, ceramics, glass, organic
Any one of material composition.
10. according to the method described in claim 7, wherein, the sedimentary that the semiconductor layer is made of polysilicon.
11. according to the method described in claim 7, wherein, the step of removing the support substrate and first sacrificial layer
Step respectively includes including wet etching, dry etching, chemical-mechanical planarization or above-mentioned process combination.
12. according to the method for claim 11, wherein when removing the support substrate, the first sacrificial layer conduct
Stop-layer.
13. according to the method for claim 11, wherein when removing first sacrificial layer, the multiple layer insulation
The bottommost interlayer insulating film of layer is as stop-layer.
14. according to the method for claim 11, wherein while removing first sacrificial layer or later, remove institute
State extension of multiple channel columns in first sacrificial layer.
15. according to the method for claim 14, wherein when removing first sacrificial layer, the multiple channel column
Bottom end is prominent on the surface of the bottommost interlayer insulating film, and the method also includes being gone using additional chemical-mechanical planarization
Except the protruding portion of the multiple channel column.
16. according to the method described in claim 7, wherein, the step of forming rhythmic structure of the fence, includes:
Before forming the multiple channel column, is formed and sacrifice laminated construction, the sacrifice laminated construction includes multiple second sacrificial
Domestic animal layer, the multiple second sacrificial layer are alternately stacked with the multiple interlayer insulating film；It is formed and runs through the sacrifice laminated construction
Multiple through-holes, the multiple through-hole extends in first sacrificial layer,
After forming the multiple channel column, metal layer is used to replace the multiple second sacrificial layer to form the multiple grid
Pole conductor layer.
17. according to the method described in claim 7, further include:
Supplemental dielectric layer is formed on the surface of the top interlayer insulating film of the multiple interlayer insulating film；And
Multiple bit lines, a plurality of wordline, string selection line and source selection line and source electrode line are formed in the supplemental dielectric layer.
18. according to the method for claim 17, further includes:
By cmos circuit chip bonding on the Free Surface of the supplemental dielectric layer, to form bonding component.
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