CN109390349A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
- Publication number
- CN109390349A CN109390349A CN201811242026.1A CN201811242026A CN109390349A CN 109390349 A CN109390349 A CN 109390349A CN 201811242026 A CN201811242026 A CN 201811242026A CN 109390349 A CN109390349 A CN 109390349A
- Authority
- CN
- China
- Prior art keywords
- layer
- channel
- protective layer
- memory device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 239000010410 layer Substances 0.000 claims abstract description 255
- 239000011241 protective layer Substances 0.000 claims abstract description 61
- 239000004020 conductor Substances 0.000 claims abstract description 52
- 239000004065 semiconductor Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000005530 etching Methods 0.000 claims abstract description 29
- 230000001020 rhythmical effect Effects 0.000 claims abstract description 29
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 238000003860 storage Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 21
- 230000005641 tunneling Effects 0.000 claims description 18
- 239000000463 material Substances 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 208000005189 Embolism Diseases 0.000 description 7
- 238000000151 deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 2
- 238000000231 atomic layer deposition Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 102100032401 Charged multivesicular body protein 2a Human genes 0.000 description 1
- 102100024827 Dynamin-1-like protein Human genes 0.000 description 1
- 101000943253 Homo sapiens Charged multivesicular body protein 2a Proteins 0.000 description 1
- 101000909218 Homo sapiens Dynamin-1-like protein Proteins 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000007521 mechanical polishing technique Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Landscapes
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The 3D memory device includes: semiconductor substrate；Rhythmic structure of the fence is located at semiconductor substrate including the multiple grid conductors and multiple interlayer insulating films being alternately stacked；And multiple channel columns, run through rhythmic structure of the fence, channel column includes: epitaxial layer, is located at channel column bottom, and contact with semiconductor substrate；Protective layer is located above epitaxial layer, and contacts with epitaxial layer；And channel layer, it is located above protective layer, and contacted with protective layer.The 3D memory device above epitaxial layer by being arranged protective layer as etching stop layer, and the protection that epitaxial layer is protected layer will not be removed, to improve the breakdown voltage of 3D memory device.
Description
Technical field
The present invention relates to memory technologies, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, mainly include rhythmic structure of the fence, through rhythmic structure of the fence channel column with
And conductive channel, the grid conductor of selection transistor and memory transistor is provided using rhythmic structure of the fence, is provided using channel column
The channel layer of selection transistor and memory transistor and gate medium lamination, and the mutual of memory cell string is realized using conductive channel
Even.However, when forming contact of the channel layer with epitaxial layer, partial epitaxial layer can quilt for larger-size channel column
Removal causes the surface of epitaxial layer away from the in uneven thickness of the side wall of epitaxial layer, close to the thickness of the epitaxial layer of gate conductor portion
Degree is very thin, when forming channel layer, the uneven thickness of the channel layer contacted with epitaxial layer, close to the channel layer of gate conductor portion
Also can be very thin, close to gate conductor portion epitaxial layer be oxidized after, the channel layer of the part be easy after powered up it is breakdown,
To influence the reliability of device.
It is expected that the structure and its manufacturing method of 3D memory device are further improved, to improve the reliable of 3D memory device
Property.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, by setting above epitaxial layer
Protective layer is set as etching stop layer, epitaxial layer, which is protected, to be removed, to improve the breakdown potential of 3D memory device
Pressure.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: semiconductor substrate；Rhythmic structure of the fence, including
The multiple grid conductors and multiple interlayer insulating films being alternately stacked are located at the semiconductor substrate；And multiple channel columns,
Through the rhythmic structure of the fence, the channel column includes: epitaxial layer, is located at the channel column bottom, and serve as a contrast with the semiconductor
Bottom contact；Protective layer is located at the epitaxial layer upper surface, and contacts with the epitaxial layer, for protecting the epitaxial layer；And
Channel layer is located above the protective layer, and contacts with the protective layer.
Preferably, the channel column further includes contact layer, is connect positioned at the side wall of the channel column, and with the protective layer
Touching.
Preferably, the material of the protective layer includes metal.
Preferably, the epitaxial layer includes contact zone, is located at the epitaxial layer two sides, close to the institute of the semiconductor substrate
Grid conductor is stated to contact with the contact zone.
Preferably, other grid conductors are contacted with the contact layer.
Preferably, the rhythmic structure of the fence includes nucleus；And stepped area, surround the nucleus.
Preferably, the part channel column is located at the nucleus, and other channel columns are located at the stepped area.
The size for being preferably located at the channel column of the stepped area is greater than the ditch for being located at the nucleus
The size of road column.
Preferably, the semiconductor substrate includes peripheral circuit.
According to another aspect of the present invention, a kind of method for manufacturing 3D memory device is provided, comprising: on a semiconductor substrate
Rhythmic structure of the fence is formed, the rhythmic structure of the fence includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked；And
The step of forming the multiple channel columns for running through the rhythmic structure of the fence, forming the channel column includes: through the gate stack knot
Structure and the part semiconductor substrate form multiple channel holes；Epitaxial layer, the epitaxial layer are formed in the bottom in the channel hole
It is contacted with the semiconductor substrate；And protective layer is formed in the bottom in the channel hole and side wall, the protective layer is located at institute
It states above epitaxial layer, and is contacted with the epitaxial layer, wherein the protective layer is as etching stop layer.
Preferably, after forming the protective layer, the step of forming the channel column further includes covering the channel hole
Bottom and side wall, sequentially form block media layer, charge storage layer, tunneling medium layer and channel layer.
Preferably, after forming the channel layer, the step of forming the channel column further includes etching the channel hole
The channel layer, the tunneling medium layer, the charge storage layer and the block media layer of bottom, with expose portion
The protective layer, wherein the etching stops when reaching the protective layer.
Preferably, after protective layer described in expose portion, the step of forming the channel column further includes in the protection
Layer top re-forms the channel layer, and the channel layer is contacted with the protective layer.
Preferably, the step of forming the rhythmic structure of the fence includes: to form insulating laminate knot on the semiconductor substrate
Structure, the insulating laminate structure include the multiple interlayer insulating films and multiple sacrificial layers being alternately stacked；By the multiple sacrificial layer
It is patterned step-like；The multiple sacrificial layer is replaced as multiple grid conductors, to form the insulating laminate structure.
Preferably, the step of being formed before multiple grid conductors, forming the rhythmic structure of the fence further includes removal institute
It states multiple sacrificial layers and forms a plurality of cavities, the multiple cavity exposes the part protective layer and partial epitaxial layer, wherein sudden and violent
The protective layer being exposed in the cavity is oxidized, so that contact layer is formed, the epitaxial layer being exposed in the cavity
It is oxidized, to form contact zone.
Preferably, it is contacted close to the grid conductor of the semiconductor substrate with the contact zone, other grids
Conductor is contacted with the contact layer.
Preferably, after the multiple sacrificial layer being replaced as multiple grid conductors, the multiple grid conductor is in step
Shape, forms the stepped area of the rhythmic structure of the fence, and the stepped area surrounds nucleus.
Preferably, the part channel column is located at the nucleus, other described channel columns are located at the stepped area.
The size for being preferably located at the channel column of the stepped area is greater than the ditch for being located at the nucleus
The size of road column.
Preferably, the material of the protective layer includes metal.
3D memory device according to an embodiment of the present invention and its manufacturing method are made by the way that protective layer is arranged above epitaxial layer
For etching stop layer, the protection that epitaxial layer is protected layer will not be removed, on the protection layer it is rectangular at channel layer when, channel layer
It is uniformly distributed on the protection layer, and is contacted by protective layer with epitaxial layer, to improve the breakdown voltage of 3D memory device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory device according to an embodiment of the present invention.
Fig. 3 to Figure 15 shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
Figure 16 a, 16b show the effect analysis schematic diagram of 3D memory device according to an embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line (Bit-Line, BL), and second end is connected to
Source electrode line (Source Line, SL).Memory cell string 100 includes the multiple crystalline substances being connected in series between the first end and a second end
Body pipe, comprising: first choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.First choice crystal
The grid of pipe Q1 is connected to string selection line (Selection Gate for Drain, SGD), the grid of the second selection transistor Q2
It is connected to source selection line (Selection Gate for Source, SGS).The grid of memory transistor M1 to M4 is separately connected
To the respective word of wordline (Word-Line) WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include grid conductor 122 and 123, deposit
Storage transistor M1 to M4 respectively includes 4 grid conductors 121.In grid conductor 121,122 and 123 and memory cell string 100
The stacking order of transistor is consistent, is separated each other using interlayer insulating film between adjacent grid conductor, to form gate stack
Structure.Further, memory cell string 100 includes the first channel column 110.First channel column 110 it is adjacent with rhythmic structure of the fence or
Person runs through rhythmic structure of the fence.In the middle section of the first channel column 110, tunnelling is accompanied between grid conductor 121 and channel layer 111
Dielectric layer 112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.In the first channel column 110
Both ends, gate dielectric layer 114 is accompanied between grid conductor 122 and 123 and channel layer 111, thus formed selection transistor Q1 and
Q2。
In this embodiment, channel layer 111 is for example made of polysilicon, and tunneling medium layer 112 and gate dielectric layer 114 are distinguished
It is made of oxide, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, example
The silicon nitride of particle such as comprising metal or semiconductor, grid conductor 121,122 and 123 is made of metal, such as tungsten.Channel
Layer 111 is for providing control selection transistor and controlling the channel region of transistor, the doping type and selection transistor of channel layer 111
It is identical with the control type of transistor.For example, the selection transistor and control transistor, channel layer 111 for N-type can be N
The polysilicon of type doping.
In this embodiment, the core of the first channel column 110 is channel layer 111, tunneling medium layer 112, charge storage layer
113 and gate dielectric layer 114 formed surround core wall laminated construction.In alternate embodiments, the core of the first channel column 110
Portion is additional insulating layer, and channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around half
The laminated construction of conductor layer.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In the first channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In substitution
In embodiment, step independent of one another can be used, the semiconductor layer and gate dielectric layer of selection transistor Q1 and Q2 are respectively formed
And the semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In the first channel column 110, selection transistor Q1's and Q2
The semiconductor layer of semiconductor layer and memory transistor M1 to M4 is electrically connected to each other.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling effect
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, source selection line SGS is biased to greatly
About zero volts, so that the selection transistor Q2 corresponding to source selection line SGS is disconnected, string selection line SGD is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SGD.Further, bit line BL is grounded, and wordline WL2 is offset to
Program voltage VPG, such as 20V or so, remaining wordline are offset to low-voltage VPS1.Due to the word of only selected memory transistor M2
Line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 reaches electricity via tunneling medium layer 112
Lotus accumulation layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device
A insulating layer.The 3D memory device shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, and each storage is single
Member string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that this
To invent without being limited thereto, 3D memory device may include any number of memory cell strings, for example, 1024, each memory cell string
In number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Fig. 1 a to Fig. 2, in 3D memory device, memory cell string respectively includes respective first channel column 110,
And public grid conductor 121,122 and 123.Transistor in grid conductor 121,122 and 123 and memory cell string 100
Stacking order it is consistent, separated each other using interlayer insulating film between adjacent grid conductor, to form rhythmic structure of the fence
120.Interlayer insulating film is not shown in Fig. 2.
Rhythmic structure of the fence 120 is in step-like, and has nucleus, and the stepped area around nucleus.First
Channel column 110 is located at nucleus, and illusory channel column 130 is located at stepped area.Positioned at the illusory channel column 130 of stepped area
Size is greater than the size of the first channel column 110 positioned at nucleus.
The internal structure of first channel column 110 and illusory channel column 130 is as shown in Figure 1 b, no longer carries out herein specifically
It is bright.In the middle section of the first channel column 110, channel layer 111, tunnelling inside grid conductor 121 and the first channel column 110 are situated between
Matter layer 112, charge storage layer 113 and gate dielectric layer 114 together, form memory transistor M1 to M4.In the first channel column 110
Channel layer 111 and gate dielectric layer 114 inside both ends, grid conductor 122 and 123 and the first channel column 110 together, form selection
Transistor Q1 and Q2.
First channel column 110 runs through rhythmic structure of the fence 120, and is arranged in array, multiple first channel columns of same row
110 first end is commonly connected to same bit line, and second end is commonly connected to substrate 101, and second end is formed via substrate 100
Common source connection.
The grid conductor 122 of string select transistor Q1 is divided into different grid by grid line gap (gate line slit)
Line.Grid line with multiple first channel columns 110 of a line is commonly connected to same string selection line.
The grid conductor 121 of memory transistor M1 and M4 are separately connected integrally according to different levels.If storage is brilliant
The grid conductor 121 of body pipe M1 and M4 are divided into different grid lines by grid line gap, then the grid line of same level is via respective
Conductive channel reaches interconnection layer, thus it is interconnected amongst one another, then same wordline is connected to via conductive channel.
The grid conductor of source selection transistor Q2 links into an integrated entity.If the grid conductor 123 of source selection transistor Q2 by
Grid line gap is divided into different grid lines, then grid line reaches interconnection layer via respective conductive channel, thus it is interconnected amongst one another, then
Same source selection line SGS is connected to via conductive channel.
It preferably, include peripheral circuit, such as cmos circuit in substrate semiconductor substrate 101.It is mentioned using conductive channel
For being electrically connected between cmos circuit and external circuit.
Fig. 3 to Figure 15 shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention,
Wherein, Fig. 3 is the sectional view in Fig. 2 along line A-A to Figure 11, Figure 13 and Figure 15, and Figure 12, Figure 14 are cutting along line B-B in Fig. 2
Face figure.It is described in detail below in conjunction with manufacturing method of the Fig. 3 to Figure 15 to invention memory construction.
The method of the present embodiment manufacture 3D memory device starts from semiconductor substrate 101, is formed absolutely in semiconductor substrate 101
Edge laminated construction 130, as shown in Figure 3.
In this step, it can use depositing operation stacking interlayer insulating film 131 in semiconductor substrate 101 and sacrificing
Layer 132, wherein the material of interlayer insulating film 131 is selected from oxide, and the material of sacrificial layer 132 is selected from nitride, such as nitrogenizes
Silicon.
Further, insulating laminate structure 130 is patterned, makes 130 stepped of insulation layer structure, as shown in Figure 4.
In this step, it can use etching technics to perform etching insulating laminate structure, keep sacrificial layer 132 and interlayer exhausted
The size of edge layer 131 is successively successively decreased upwards from semiconductor substrate 101, to form nucleus 10 and around nucleus 10
Stepped area 20.
Further, covering insulating laminate structure 130 forms dielectric layer 133, as shown in Figure 5.
Further, multiple are formed through dielectric layer 133, insulating laminate structure 130 and part semiconductor substrate 101
One channel hole 102 and multiple second channels hole 103, and respectively in the first channel hole 102 and 103 bottom shape of multiple second channels hole
At the first epitaxial layer 115 and the second epitaxial layer 115 ', as shown in Figure 6.
In this step, it can use etching technics and depositing operation form multiple first channels hole 102 and multiple second
Channel hole 103 and the first epitaxial layer 115 and the second epitaxial layer 115 ', wherein the first channel hole 102 is located at nucleus, the
Two channel holes 103 are located at stepped area, and the size in the second channel hole 103 is greater than the size in the first channel hole 102.
Since the size in the second channel hole 103 is larger, the second epitaxial layer 115 ' be located at the depth in semiconductor substrate 101 compared with
Deep, the second epitaxial layer 115 ' is easy 103 side wall of the second channel hole at semiconductor substrate 101 and forms gap 104.
Further, it is covered each by the bottom in the first channel hole 102 and the second channel hole 103, side wall forms the first protection
Layer 116 and the second protective layer 116 ', as shown in Figure 7.
In this step, the first protective layer 116 cover the first channel hole 102 side wall and bottom, and with the first epitaxial layer
115 contacts, the second protective layer 116 ' cover side wall and the bottom in the second channel hole 103, and contact with the second epitaxial layer 115 ',
In, the material of the first protective layer 116 and the second protective layer 116 ' includes metal material.
Further, in the first channel hole 102, covering bottom and side wall sequentially form the first block media layer 114, the
One charge storage layer 113, the first tunneling medium layer 112 and the first channel layer 111 cover bottom in the second channel hole 103
Portion and side wall sequentially form the second block media layer 114 ', the second charge storage layer 113 ', the second tunneling medium layer 112 ' and
Second channel layer 111 ', as shown in Figure 8.
Further, the first channel layer 111 in the first channel hole 102 is removed, and removes 102 bottom of the first channel hole
Part the first block media layer 114, the first charge storage layer 113 and the first tunneling medium layer 112, thus expose portion
One protective layer 116 removes the second channel layer 111 ' in the second channel hole 103, and removes the part of 103 bottom of the second channel hole
Second block media layer 114 ', the second charge storage layer 113 ' and the second tunneling medium layer 112 ', thus expose portion second
Protective layer 116 ', as shown in Figure 9.
In this step, it can use silicon-oxide-nitride-oxide (SONO) etching technics to the first channel hole
102 perform etching in 103 bottom structure of the second channel hole, wherein etching reaches the first protective layer 116 and the second protective layer
Stop when 116 '.
Further, in the first channel hole 102, covering bottom and side wall re-form the first channel layer 111, second
In channel hole 103, covering bottom and side wall re-form the second channel layer 111 ', as shown in Figure 10.
In this step, it re-forms the first channel layer 111 to contact with the protective layer 116 of 102 bottom of the first channel hole, weight
New second channel layer 111 ' that formed is contacted with the protective layer 116 ' of 103 bottom of the second channel hole.
Further, the first insulating core 117 is filled in the first channel hole 102, and is covered the first insulating core 117 and existed
First embolism structure 118 is formed at 102 top of the first channel hole, and the second insulating core 117 ' is filled in the second channel hole 103, and
It covers the second insulating core 117 ' and forms the second embolism structure 118 ' on 103 top of the second channel hole, as shown in figure 11.
In this step, the first channel hole 102 can be filled using insulating materials first with depositing operation, is utilizing quarter
Etching technique and chemical mechanical polishing technique remove first channel layer 111 at 102 top of the first channel hole, the first tunneling medium layer
112 and first charge storage layer 113, finally the first insulating core 117, the first channel layer 111, the are covered using depositing operation
One tunneling medium layer 112 and the first charge storage layer 113 form the first embolism structure 118, wherein the first embolism structure 118
Respectively with the first channel layer 111, the first tunneling medium layer 112, the first charge storage layer 113 and the first block media layer 114
Contact, and the material of the first embolism structure 118 is identical as the material of the first channel layer 111.Similarly, the second insulating core 117 '
Identical as the formation process of the second embolism structure 118 ', details are not described herein again.
Further, using grid line gap 105 as etchant channel, sacrificial layer 132 is gone using isotropic etching
Except to form cavity 106, as shown in figure 12.
In this step, isotropic etching can be using the wet etching or gas phase etching of selectivity.In wet etching
It is middle to use etching solution as etchant, wherein in the etch solution by semiconductor structure submergence.Erosion is used in gas phase etching
Gas is carved as etchant, wherein semiconductor structure is exposed in etching gas.Interlayer in insulating laminate structure 130
In the case of insulating layer 131 and sacrificial layer 132 are made of silica and silicon nitride respectively, phosphoric acid can be used in wet etching
Solution can use C as etchant in gas phase etching4F8、C4F6、CH2F2And O2One of or it is a variety of.In etching step
In, etchant is full of grid line gap 105.The end of sacrificial layer 132 in insulating laminate structure 130 is exposed to grid line gap 105
Opening in, therefore, sacrificial layer 132 touches etchant.Etchant is from the opening in grid line gap 105 gradually to insulating laminate knot
The etched inside sacrificial layer 132 of structure 130.Due to the selectivity of etchant, the etching is relative to the layer in insulating laminate structure 130
Between insulating layer 131 remove sacrificial layer 132.
Further, using grid line gap 105 and cavity 106 as oxidation channel, first in cavity 106 will be exposed to
Protective layer 116 and the second protective layer 116 ' aoxidize, and are respectively formed the first contact layer 119 and the second contact layer 119 ', utilize grid line
Gap 105 and cavity 106 are as oxidation channel, by the first epitaxial layer 115 being exposed in cavity 106 and the second epitaxial layer 115 '
Oxidation, is respectively formed the first contact zone 107 and the second contact zone 107 ', as shown in figure 13.
In this step, the first protective layer 116 and the second protective layer 116 ' are oxidized to high dielectric constant (high-k)
Material, to form the first contact layer 119 and the second contact layer 119 '.
Further, using grid line gap 105 as deposit channel, using atomic layer deposition (ALD), in grid line gap
105 and cavity 106 in filling metal formed grid conductor 121,122,123, then carry out etch-back (etch back), again
Grid line gap 105 is formed, as shown in Figure 14, Figure 15.
In this step, metal is for example made of tungsten.Grid conductor 121,122,123 has replaced insulating laminate structure 130
In sacrificial layer 132 in step-like, so as to form rhythmic structure of the fence 120.
Wherein, the embolism structure 118, the first block media layer 114, contact layer 119 at the top of the first channel column 110 and
The grid conductor 122 of the top forms upper selection transistor, the first epitaxial layer 115 of 110 bottom of the first channel column, the first extension
The contact zone 107 of 115 two sides of layer and the selection transistor under the formation of grid conductor 123 of semiconductor substrate 101, the first ditch
First channel layer 111 at 110 middle part of road column, the first tunneling medium layer 112, the first charge storage layer 113, the first block media layer
114, contact layer 119 and grid conductor 121 form memory transistor.
Figure 16 a, Figure 16 b show the effect analysis figure of 3D memory device according to an embodiment of the present invention.
In ideal technology, for larger-size channel column, such as virtual channel lives 130, carves using SONO
Etching technique etches virtual channel and lives after 130 bottom-exposeds go out the second epitaxial layer 115 ', recycles depositing operation in the second epitaxial layer
The second channel layer 111 ' is deposited on 115 ', contacts the second channel layer 111 ' with the second epitaxial layer 115 '.However, etching virtual ditch
When 130 bottom is lived in road, the second epitaxial layer 115 ' of part can be removed, and formed and be similar to spherical cavity, lead to the second epitaxial layer
In uneven thickness, the very thin thickness of the second epitaxial layer 115 ' of close gate conductor portion, in formation second of 115 ' side wall
When channel layer 111 ', the uneven thickness of the second channel layer 111 ' contacted with the second epitaxial layer 115 ', close to gate conductor portion
The second channel layer 111 ' also can be very thin, when being oxidized to form contact zone close to the second epitaxial layer 115 ' of gate conductor portion
After 107 ', the second channel layer 111 ' of the part is easy breakdown after powered up.
And the 3D memory device of the embodiment of the present invention is as shown in figure 15, by 115 ' the top setting second of the second epitaxial layer
Protective layer 116 ' is used as etching stop layer, and the second epitaxial layer 115 ' will not be removed by the protection of the second protective layer 116 ', the
When two protective layers, 116 ' top forms the second channel layer 111 ', the second channel layer 111 ' is evenly distributed on the second protective layer 116 '
On, and contacted with the second epitaxial layer 115 ' by the second protective layer 116 ', by be not deposit in the second epitaxial layer 115 ' Figure 16 a,
Spherical cavity is similar in Figure 16 b, and the second channel layer 111 ' is located on the second protective layer 116 ', therefore, in grid conductor
At 123, the second channel layer 111 ' is evenly distributed with the second epitaxial layer 115 ', to improve the breakdown voltage of 3D memory device.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (20)
1. a kind of 3D memory device, comprising:
Semiconductor substrate；
Rhythmic structure of the fence is located at the semiconductor substrate including the multiple grid conductors and multiple interlayer insulating films being alternately stacked
Top；And
Multiple channel columns, run through the rhythmic structure of the fence, and the channel column includes:
Epitaxial layer is located at the channel column bottom, and contacts with the semiconductor substrate；
Protective layer is located at the epitaxial layer upper surface, and contacts with the epitaxial layer, for protecting the epitaxial layer；And
Channel layer is located above the protective layer, and contacts with the protective layer.
2. 3D memory device according to claim 1, wherein the channel column further includes contact layer, is located at the channel
The side wall of column, and contacted with the protective layer.
3. 3D memory device according to claim 1, wherein the material of the protective layer includes metal.
4. 3D memory device according to claim 2, wherein the epitaxial layer includes contact zone, is located at the epitaxial layer
Two sides, the grid conductor close to the semiconductor substrate are contacted with the contact zone.
5. 3D memory device according to claim 4, wherein other grid conductors are contacted with the contact layer.
6. -5 any 3D memory device according to claim 1, wherein the rhythmic structure of the fence includes
Nucleus；And
Stepped area surrounds the nucleus.
7. 3D memory device according to claim 6, wherein the part channel column is located at the nucleus, other
The channel column is located at the stepped area.
8. -7 any 3D memory device according to claim 1, wherein positioned at the channel column of the stepped area
Size is greater than the size of the channel column positioned at the nucleus.
9. -7 any 3D memory device according to claim 1, wherein the semiconductor substrate includes peripheral circuit.
10. a kind of method for manufacturing 3D memory device, comprising:
Form rhythmic structure of the fence on a semiconductor substrate, the rhythmic structure of the fence includes the multiple grid conductors being alternately stacked and more
A interlayer insulating film；And
The multiple channel columns for running through the rhythmic structure of the fence are formed, the step of forming the channel column includes:
Multiple channel holes are formed through the rhythmic structure of the fence and the part semiconductor substrate；
Epitaxial layer is formed in the bottom in the channel hole, the epitaxial layer is contacted with the semiconductor substrate；And
Form protective layer in the bottom in the channel hole and side wall, the protective layer is located above the epitaxial layer, and with it is described
Epitaxial layer contact,
Wherein, the protective layer is as etching stop layer.
11. according to the method described in claim 10, wherein, after forming the protective layer, forming the step of the channel column
Suddenly further includes bottom and the side wall for covering the channel hole, sequentially form block media layer, charge storage layer, tunneling medium layer,
And channel layer.
12. according to the method for claim 11, wherein after forming the channel layer, form the step of the channel column
It suddenly further include the channel layer for etching channel hole bottom, the tunneling medium layer, the charge storage layer and described
Block media layer, with protective layer described in expose portion,
Wherein, the etching stops when reaching the protective layer.
13. according to the method for claim 12, wherein after protective layer described in expose portion, form the channel column
The step of further include that the channel layer is re-formed above the protective layer, the channel layer is contacted with the protective layer.
14. according to the method described in claim 10, wherein, the step of forming the rhythmic structure of the fence, includes:
Insulating laminate structure is formed on the semiconductor substrate, and the insulating laminate structure includes the multiple interlayers being alternately stacked
Insulating layer and multiple sacrificial layers；
The multiple sacrificial layer is patterned step-like；
The multiple sacrificial layer is replaced as multiple grid conductors, to form the insulating laminate structure.
15. according to the method for claim 14, wherein formed before multiple grid conductors, form the gate stack
The step of structure further includes removing the multiple sacrificial layer to form a plurality of cavities, the multiple cavity by the part protective layer with
Partial epitaxial layer exposure,
Wherein, the protective layer being exposed in the cavity is oxidized, to form contact layer, is exposed in the cavity
The epitaxial layer is oxidized, to form contact zone.
16. according to the method for claim 15, wherein the grid conductor close to the semiconductor substrate connects with described
Area's contact is touched,
Other grid conductors are contacted with the contact layer.
17. according to the method for claim 14, wherein after the multiple sacrificial layer is replaced as multiple grid conductors,
The multiple grid conductor forms the stepped area of the rhythmic structure of the fence in step-like,
The stepped area surrounds nucleus.
18. according to the method for claim 15, wherein the part channel column is located at the nucleus, described in other
Channel column is located at the stepped area.
19. according to the method for claim 18, wherein the size positioned at the channel column of the stepped area is greater than position
In the size of the channel column of the nucleus.
20. any method of 0-19 according to claim 1, wherein the material of the protective layer includes metal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811242026.1A CN109390349B (en) | 2018-10-24 | 2018-10-24 | 3D memory device and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811242026.1A CN109390349B (en) | 2018-10-24 | 2018-10-24 | 3D memory device and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109390349A true CN109390349A (en) | 2019-02-26 |
| CN109390349B CN109390349B (en) | 2020-11-13 |
Family
ID=65426823
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811242026.1A Active CN109390349B (en) | 2018-10-24 | 2018-10-24 | 3D memory device and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109390349B (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110137178A (en) * | 2019-04-19 | 2019-08-16 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN110943089A (en) * | 2019-10-21 | 2020-03-31 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111199976A (en) * | 2020-01-08 | 2020-05-26 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111244095A (en) * | 2020-03-25 | 2020-06-05 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN111370418A (en) * | 2019-12-26 | 2020-07-03 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device |
| CN112071851A (en) * | 2020-08-10 | 2020-12-11 | 长江存储科技有限责任公司 | Stack structure and manufacturing method thereof, 3D NAND memory and manufacturing method thereof |
| CN112802845A (en) * | 2020-01-03 | 2021-05-14 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method of three-dimensional memory and electronic equipment |
| CN112928117A (en) * | 2021-03-15 | 2021-06-08 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| CN113097216A (en) * | 2020-01-16 | 2021-07-09 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN114203719A (en) * | 2020-09-18 | 2022-03-18 | 爱思开海力士有限公司 | Semiconductor memory device and method of manufacturing the same |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681687A (en) * | 2012-09-11 | 2014-03-26 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method for fabricating the same |
| US9755047B2 (en) * | 2015-10-27 | 2017-09-05 | United Microelectronics Corp. | Semiconductor process and semiconductor device |
| CN107871744A (en) * | 2017-11-09 | 2018-04-03 | 长江存储科技有限责任公司 | A kind of NAND string structure and preparation method thereof |
| CN108417576A (en) * | 2018-03-16 | 2018-08-17 | 长江存储科技有限责任公司 | Three-dimensional storage part and the method that epitaxial structure is formed in its raceway groove hole |
-
2018
- 2018-10-24 CN CN201811242026.1A patent/CN109390349B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681687A (en) * | 2012-09-11 | 2014-03-26 | 三星电子株式会社 | Three-dimensional semiconductor memory device and method for fabricating the same |
| CN108538847A (en) * | 2012-09-11 | 2018-09-14 | 三星电子株式会社 | The method for manufacturing three-dimensional semiconductor devices |
| US9755047B2 (en) * | 2015-10-27 | 2017-09-05 | United Microelectronics Corp. | Semiconductor process and semiconductor device |
| CN107871744A (en) * | 2017-11-09 | 2018-04-03 | 长江存储科技有限责任公司 | A kind of NAND string structure and preparation method thereof |
| CN108417576A (en) * | 2018-03-16 | 2018-08-17 | 长江存储科技有限责任公司 | Three-dimensional storage part and the method that epitaxial structure is formed in its raceway groove hole |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110137178B (en) * | 2019-04-19 | 2022-04-01 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN110137178A (en) * | 2019-04-19 | 2019-08-16 | 长江存储科技有限责任公司 | 3D memory device and its manufacturing method |
| CN110943089A (en) * | 2019-10-21 | 2020-03-31 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111370418B (en) * | 2019-12-26 | 2021-09-24 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device |
| CN111370418A (en) * | 2019-12-26 | 2020-07-03 | 长江存储科技有限责任公司 | Method for manufacturing 3D memory device |
| CN112802845B (en) * | 2020-01-03 | 2023-12-12 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method of three-dimensional memory and electronic equipment |
| CN112802845A (en) * | 2020-01-03 | 2021-05-14 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method of three-dimensional memory and electronic equipment |
| CN111199976A (en) * | 2020-01-08 | 2020-05-26 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111199976B (en) * | 2020-01-08 | 2023-10-17 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN113097216A (en) * | 2020-01-16 | 2021-07-09 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN111244095A (en) * | 2020-03-25 | 2020-06-05 | 长江存储科技有限责任公司 | Three-dimensional memory and preparation method thereof |
| CN112071851B (en) * | 2020-08-10 | 2023-09-05 | 长江存储科技有限责任公司 | Stacked structure and manufacturing method thereof, 3D NAND memory and manufacturing method thereof |
| CN112071851A (en) * | 2020-08-10 | 2020-12-11 | 长江存储科技有限责任公司 | Stack structure and manufacturing method thereof, 3D NAND memory and manufacturing method thereof |
| CN114203719A (en) * | 2020-09-18 | 2022-03-18 | 爱思开海力士有限公司 | Semiconductor memory device and method of manufacturing the same |
| CN112928117A (en) * | 2021-03-15 | 2021-06-08 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
| CN112928117B (en) * | 2021-03-15 | 2022-06-10 | 长江存储科技有限责任公司 | Three-dimensional memory device and method of fabricating the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109390349B (en) | 2020-11-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109390349A (en) | 3D memory device and its manufacturing method | |
| TWI713203B (en) | Memory device and method for fabricating the same | |
| CN109686739A (en) | 3D memory device and its manufacturing method | |
| CN110071112A (en) | 3D memory device and its manufacturing method | |
| CN110349966A (en) | The manufacturing method and 3D memory device of 3D memory device | |
| CN109148461A (en) | 3D memory device and its manufacturing method | |
| CN109390348A (en) | 3D memory device and its manufacturing method | |
| CN109346477A (en) | 3D memory device and its manufacturing method | |
| CN109712987A (en) | The manufacturing method and 3D memory device of 3D memory device | |
| CN109698201A (en) | 3D memory device and its manufacturing method | |
| CN109192735A (en) | 3D memory device and its manufacturing method | |
| CN109003983A (en) | 3D memory device and its manufacturing method | |
| CN109119426A (en) | 3D memory device | |
| CN109712988A (en) | 3D memory device and its manufacturing method | |
| CN110277404A (en) | 3D memory device and its manufacturing method | |
| CN109326557A (en) | Three-dimensional memory structure and manufacturing method | |
| CN110176460A (en) | 3D memory device and its manufacturing method | |
| CN109273453A (en) | The manufacturing method and 3D memory device of 3D memory device | |
| CN109712980A (en) | The manufacturing method and 3D memory device of 3D memory device | |
| CN109935596A (en) | 3D memory device and its manufacturing method | |
| CN109148459A (en) | 3D memory device and its manufacturing method | |
| CN109003981A (en) | 3D memory device and its manufacturing method | |
| CN109585454A (en) | 3D memory device and its manufacturing method | |
| CN109524416A (en) | Manufacture the method and memory device of memory device | |
| CN109712986A (en) | 3D memory device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |