CN109346477A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109346477A CN109346477A CN201811324416.3A CN201811324416A CN109346477A CN 109346477 A CN109346477 A CN 109346477A CN 201811324416 A CN201811324416 A CN 201811324416A CN 109346477 A CN109346477 A CN 109346477A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The 3D memory device includes: substrate；Laminated construction above substrate, the laminated construction include the multiple grid conductors and multiple interlayer insulating films being alternately stacked；Through multiple channel columns of the laminated construction；And the conductive channel through the laminated construction, the conductive channel is connected to the bottom end of the multiple channel column via the substrate, and it is separated from each other using oxide skin(coating) with the multiple grid conductor, wherein, the 3D memory device further includes barrier layer, and the multiple conductive channel and the oxide skin(coating) are separated from each other by the barrier layer.Barrier layer in the 3D memory device can increase the equivalent oxide thickness between grid conductor and conductive channel, breakdown voltage be improved, to improve the yield and reliability of 3D memory device.
Description
Technical field
The present invention relates to memory technologies, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor, using interconnection that run through laminated construction and the conductive channel realization memory cell string with laminated construction insulation.
With reference to Fig. 1 a-1c, in the prior art, the preparation process of above structure is as follows:
S1, with reference to Fig. 1 a, providing one has 1 laminated construction of channel groove, carries out the wet process of tungsten (W) 2 in grid line gap (GLS)
Etching；
S2 with reference to Fig. 1 b, the deposition of clearance layer oxide 3, and is etched back to clearance layer oxide 3；
S3 carries out ion implanting (IMP) deposition of TI/TIN in channel groove 1, then carries out common source tungsten with reference to Fig. 1 c
The deposition of wall 4 makes 4 surfaces of common source tungsten wall flat finally by chemical mechanical grinding.
Grid conductor and 4 mutual distance of common source tungsten wall in laminated construction is close, is isolated by silica therebetween.So
And be easily oxidized (in such as Fig. 1 c at dotted line) during silicon oxide deposition, and consistency is lower, so that grid conductor and conduction are logical
Breakdown potential between road is forced down, and causes the electric property of 3D memory device poor.It is expected that being further improved the knot of 3D memory device
Structure and its manufacturing method, to improve the yield and reliability of 3D memory device.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, wherein uses oxide skin(coating)
Grid conductor and conductive channel are separated from each other with barrier layer, to increase the equivalent oxide between grid conductor and conductive channel
Thickness degree improves the breakdown voltage between grid conductor and conductive channel.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: substrate；Lamination knot above substrate
Structure, the laminated construction include the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；Multiple channel columns run through institute
State laminated construction；Conductive channel runs through the laminated construction, and is insulated by separation layer and the laminated construction；And barrier
Layer, the multiple conductive channel and the separation layer are separated from each other.
Preferably, the separation layer is oxide skin(coating).
Preferably, the bottom end of the multiple channel column forms common source connection via the substrate, and the conductive channel mentions
The conductive path of source electrode line is connected to for the common source.
Preferably, the 3D memory device further includes the doped region in the substrate, the conductive channel with it is described
Doped region contact.
Preferably, the 3D memory device further include: stratum nucleare, on the surface of the interlayer insulating film.
Preferably, the 3D memory device further includes grid line gap, and the laminated construction is run through in the grid line gap, thus
The multiple grid conductor is divided into a plurality of grid line, the conductive channel is located in the grid line gap.
Preferably, the separation layer is located on the side wall in the grid line gap, and the conductive channel fills the grid line seam
Gap, the barrier layer is between the separation layer and the conductive channel.
Preferably, a part of the separation layer is located between interlayer insulating film adjacent in the laminated construction.
Preferably, the 3D memory device further includes barrier layer, between the barrier layer and conductive channel.
Preferably, the channel column include around center stack formed channel layer, tunneling medium layer, charge storage layer and
Gate dielectric layer.
According to another aspect of the present invention, a kind of method for manufacturing 3D memory device is provided, comprising: be formed on the substrate folded
Layer structure and multiple channel columns through the laminated construction, first laminated construction include that the multiple grids being alternately stacked are led
Body layer and multiple interlayer insulating films；Form the separation layer for closing the multiple grid conductor；Form the resistance for covering the separation layer
Interlayer；And form the conductive channel for running through the laminated construction；Wherein, the laminated construction passes through separation layer and the conduction
Channel insulation, the conductive channel are separated from each other by barrier layer and the separation layer.
Preferably, the separation layer is oxide skin(coating).
Preferably, before forming laminated construction, the first laminated construction is formed, first laminated construction includes alternating heap
Folded multiple sacrificial layers and multiple interlayer insulating films；The multiple sacrificial layer is replaced using multiple gate conductor layers, forms lamination
Structure.
Preferably, the step of forming laminated construction includes: the grid line gap to be formed through first laminated construction；Pass through
Grid line gap removes the multiple sacrificial layer in first laminated construction, to form the sky with the grid line gap area
Chamber；Metal layer is filled in the grid line gap and the cavity by grid line gap；And the metal layer is etched,
Grid line gap is re-formed, so that the metal layer to be divided into the multiple grid conductor of different level.
Preferably, the method for the manufacture 3D memory device further include: form doped region in the substrate.
Preferably, between the step of forming cavity and the step of filling metal layer, further includes: stitched via the grid line
Gap forms stratum nucleare on the surface of the multiple interlayer insulating film.
Preferably, in the step of re-forming grid line gap, the grid conductor of same level is divided in the grid line gap
It is cut into a plurality of grid line.
Preferably, before forming conductive channel further include: deposit barrier layer in the grid line gap.
3D memory device provided in an embodiment of the present invention and its manufacturing method, it is rectangular at including being alternately stacked on substrate
The laminated construction of grid conductor and interlayer insulating film not only forms the channel column for running through the laminated construction, but also is formed to run through and be somebody's turn to do
The conductive channel of laminated construction.The conductive channel is located in grid line gap, the conduction for being connected to source electrode line for providing common source
Path.Compared with the conductive channel formed in dedicated wiring region, the conductive channel formed in grid line gap can reduce core
Piece area occupied.The conductive channel is easy to implement the connection between 3D memory device and CMOS chip, and be easy to compared with
Technique is integrated, especially after the thickness of laminated construction is continuously increased, draws to be formed for source electrode line without etching laminated construction
Conductive channel out is conducive to the realization of technique and the continuous improvement of integrated level.
Further, grid conductor and conductive channel are separated using oxide skin(coating) and barrier layer, which is high K Jie
Matter layer effectively increases the equivalent oxide thickness between grid conductor and conductive channel, and improves grid conductor and conduction
Film quality between channel, effectively improves breakdown voltage, to improve the yield and reliability of 3D memory device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
Fig. 1 a to Fig. 1 c shows the sectional view in each stage of 3D memory device manufacturing method according to prior art；
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 2 a and Fig. 2 b；
Fig. 3 shows the perspective view of 3D memory device；
Fig. 4 a to Fig. 4 h shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 2 a and Fig. 2 b.In the implementation
Memory cell string shown in example includes the situation of 4 storage units.It is appreciated that the invention is not limited thereto, memory cell string
In number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 2 a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 is respectively connected to
The respective word of wordline WL1 to WL4.
As shown in Figure 2 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include gate conductor layer 122 and 123,
Memory transistor M1 to M4 respectively includes gate conductor layer 121.In gate conductor layer 121,122 and 123 and memory cell string 100
Transistor stacking order it is consistent, separated each other using interlayer insulating film between adjacent gate conductor layer, to form grid
Laminated construction.Further, memory cell string 100 includes channel column 110.Channel column 110 is adjacent with rhythmic structure of the fence or passes through
Wear rhythmic structure of the fence.In the middle section of channel column 110, tunneling medium layer is accompanied between gate conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110, grid
Gate dielectric layer 114 is accompanied between pole conductor layer 122 and 123 and channel layer 111, to form selection transistor Q1 and Q2.
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and gate dielectric layer 114
It is made of respectively oxide, such as silica, charge storage layer 113 is by the insulating layer group comprising quantum dot or nanocrystal
At, such as the silicon nitride of the particle comprising metal or semiconductor, gate conductor layer 121,122 and 123 be made of metal, such as
Tungsten.Channel layer 111 is used to provide control selection transistor and control the channel region of transistor, the doping type of channel layer 111 and choosing
It is identical with the control type of transistor to select transistor.For example, selection transistor and control transistor for N-type, channel layer 111
It can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In channel column 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of substitution
Example in, can use step independent of one another, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel column 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 3 shows the perspective view of 3D memory device.For the sake of clarity, it is not shown in Fig. 3 each in 3D memory device
A insulating layer.
The 3D memory device 200 shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage
Unit string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that
The invention is not limited thereto, and 3D memory device may include any number of memory cell strings, for example, 1024, each storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
In 3D memory device 200, memory cell string respectively includes respective channel column 110 and public grid is led
Body layer 121,122 and 123.The stacking order one of transistor in gate conductor layer 121,122 and 123 and memory cell string 100
It causes, is separated each other using interlayer insulating film between adjacent gate conductor layer, to form rhythmic structure of the fence 120.In figure not
Interlayer insulating film is shown.
The internal structure of channel column 110 is as shown in Figure 2 b, is no longer described in detail herein.In the centre of channel column 110
Channel layer 111, tunneling medium layer 112, charge storage layer 113 and grid inside part, gate conductor layer 121 and channel column 110
Dielectric layer 114 together, forms memory transistor M1 to M4.At the both ends of channel column 110, gate conductor layer 122 and 123 and channel
Channel layer 111 and gate dielectric layer 114 inside column 110 together, form selection transistor Q1 and Q2.
Channel column 110 runs through rhythmic structure of the fence 120, and is arranged in array, and the first of multiple channel columns 110 of same row
End is commonly connected to same bit line (i.e. one of bit line BL1 to BL4), and second end is commonly connected to substrate 101, second end via
Substrate 100 forms common source connection.
The grid conductor 122 of string select transistor Q1 is divided into different by grid line gap (gate line slit) 102
Grid line.Grid line with multiple channel columns 110 of a line is commonly connected to same string selection line (i.e. string selection line SSL1 to SSL4
One of).
The grid conductor 121 of memory transistor M1 and M4 are separately connected integrally according to different levels.If storage is brilliant
The grid conductor 121 of body pipe M1 and M4 are divided into different grid lines by grid line gap 161, then the grid line of same level is via respective
Conductive channel 131 reach interconnection layer 132, thus interconnected amongst one another, be then connected to same wordline via conductive channel 133
(i.e. one of wordline WL1 to WL4).
The grid conductor of ground selection transistor Q2 links into an integrated entity.If the grid conductor 123 of ground selection transistor Q2 by
Grid line gap 161 is divided into different grid lines, then grid line reaches interconnection layer 132 via respective conductive channel 131, thus each other
Interconnection, then via with the being connected to same selection line GSL of conductive channel 133.
Fig. 4 a to Fig. 4 h shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
The sectional view is intercepted along the AA line in Fig. 2.
This method starts from having been formed the semiconductor structure of channel column 110, as shown in fig. 4 a.
Interlayer insulating film 151 is formed on substrate 101 and sacrificial layer 152 is alternately stacked the laminated construction 150 to be formed, and
Form the channel column 110 for running through laminated construction 150.As described below, sacrificial layer 152 will be substituted for grid conductor.In the implementation
In example, substrate 101 is, for example, monocrystalline substrate, and interlayer insulating film 151 is for example made of silica, and sacrificial layer 152 is for example by nitrogen
SiClx composition.
For the sake of clarity, the internal structure of channel column 110 is not shown in fig.4.Referring to Fig. 1 b, in channel column 110
Middle section, channel column 110 include channel layer 111, tunneling medium layer 112, charge storage layer 113 and the gate medium stacked gradually
Layer 114, at the both ends of channel column 110, channel column 110 includes the channel layer 111 and gate dielectric layer 114 stacked gradually.
Further, such as on the surface of semiconductor structure photoresist mask is formed, anisotropy is then carried out
Etching forms grid line gap 161, as shown in Figure 4 b in laminated construction 150.
Anisotropic etching can use dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, swash
Light ablation.For example, by control etching period, so that the surface for being etched in substrate 101 nearby stops.After the etching by
Removal photoresist mask is dissolved or is ashed in solvent.
In this embodiment, grid line gap 161 is applied not only to for grid conductor to be divided into a plurality of grid line, and is used to form
The conductive channel of source electrode connection.For this purpose, grid line gap 161 reaches substrate 101 through laminated construction 150.
Preferably, via grid line gap 161 carry out ion implanting, in substrate 101 formed N-type (use N type dopant,
Such as P, As) or p-type (use P-type dopant, such as B) doped region 102.The contact that doped region 102 is connected as common source
Area, for reducing the contact resistance between the conductive channel and substrate 101 subsequently formed.
Further, using grid line gap 161 as etchant channel, laminated construction is removed using isotropic etching
Sacrificial layer 152 in 150 is to form cavity 162, as illustrated in fig. 4 c.
Isotropic etching can be using the wet etching or gas phase etching of selectivity.It is molten using etching in wet etching
Liquid is as etchant, wherein in the etch solution by semiconductor structure submergence.Use etching gas as erosion in gas phase etching
Carve agent, wherein semiconductor structure is exposed in etching gas.Interlayer insulating film 151 and sacrificial layer in laminated construction 150
In the case of 152 are made of silica and silicon nitride respectively, in wet etching can using phosphoric acid solution as etchant,
It can be using one of C4F8, C4F6, CH2F2 and O2 or a variety of in gas phase etching.In an etching step, etchant is full of grid
Linear slit gap 161.The end of sacrificial layer 152 in laminated construction 150 is exposed in the opening in grid line gap 161, therefore, sacrificial layer
152 touch etchant.Etchant is from the opening in grid line gap 161 gradually to the etched inside sacrificial layer of laminated construction 150
152.Due to the selectivity of etchant, which removes sacrificial layer 152 relative to the interlayer insulating film 151 in laminated construction 150.
Preferably, it after above-mentioned wet etch step, can be removed using additional etching step in layer insulation
The etch products (such as silica) adhered on layer 151, so that exposed surface of the interlayer insulating film 151 in cavity 162 is smooth.
Preferably, after above-mentioned wet etch step, using atomic layer deposition (ALD), in interlayer insulating film 151
Stratum nucleare 153 is formed on exposed surface, as shown in figure 4d.
In this embodiment, stratum nucleare 153 is for example made of the silicide of tungsten or nitride.
Further, using grid line gap 161 as deposit channel, using atomic layer deposition (ALD), in grid line gap
161 and cavity 162 in fill metal layer 154, as shown in fig 4e.
In this embodiment, metal layer 154 is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, six
Tungsten fluoride WF6, the reducing gas of use are, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of, utilize
The chemisorption of the reaction product of tungsten hexafluoride WF6 and silane SiH4 obtains tungsten material and realizes deposition process.
Metal layer 154 is formed on the surface of stratum nucleare 153, can improve forerunner source during atomic layer deposition on the surface
Chemisorptive properties, and adhesive strength of the metal layer 154 on interlayer insulating film 151 can be improved.
Further, photoresist mask is formed on the surface of semiconductor structure, then carries out etch-back (etch
Back), grid line gap 161 is re-formed in metal layer 154, as shown in fig. 4f.
The etch-back uses sulfur fluoride, nitrogen and chlorine as etchant, to remove the tungsten material in the grid line gap 161.Into one
Step ground, metal layer 154 is not only separated into different levels by grid line gap 161, so that grid conductor 121,122 and 123 is formed,
And the grid conductor of each level is separated into a plurality of grid line.On the side wall in grid line gap 161, grid conductor 121,122
With the end exposure in 123 adjacent grid line gaps 161.
Grid conductor 121,122 and 123 and the interlayer insulating film 151 formed in this step is alternately stacked, to be formed
Laminated construction 120.Compared with laminated construction 150, the grid conductor 121,122 and 123 in laminated construction 120 has replaced lamination knot
Sacrificial layer 152 in structure 150.
Further, using grid line gap 161 as deposit channel, separation layer 125 is formed, as shown in figure 4g.It is described
125 part of separation layer is located between interlayer insulating film 151 adjacent in the laminated construction.
In this embodiment, separation layer 125 can be identical with the material of interlayer insulating film 151, such as by silica group
At.In other embodiments, separation layer 125 and the material of interlayer insulating film 151 can also be different.
Preferably, etch-back (etch back) is carried out, plasticity is carried out to the separation layer 125 in grid line gap 161, wherein
Separation layer 125 forms certain thickness on the side wall in grid line gap 161.
Further, it is formed in grid line gap 161 and covers the barrier layer 141 of the separation layer 125 and fill in it
The conductive channel 142 in portion space, as shown in figure 4h.
In this embodiment, it is separated between conductive channel 142 and grid conductor 121,122 and 123 by barrier layer 141.Resistance
Interlayer 141 is made of high-k dielectric material, including but not limited to aluminium oxide, hafnium oxide, lanthana, yttrium oxide and/or tantalum oxide,
It can effectively prevent electric leakage to generate.Similar with channel column 110, conductive channel 142 runs through laminated construction 120.The of conductive channel 142
One end is connected with substrate 101, and second end extends to the top of laminated construction 120.In a preferred embodiment, conductive channel
Doped region 102 in 142 the first end in contact substrate 101, to realize the connection between substrate 101.
It is connected as described above, channel column 110 forms common source via substrate 100, conductive channel 142 provides common source connection
To the conductive path of source electrode line SL.
In a preferred embodiment, barrier layer (figure is also formed between the barrier layer 141 and conductive channel 142
In be not shown), which is for example made of titanium and titanium nitride (Ti/TiN) composite construction.The barrier layer is in order to avoid high activity
Metal expand in substrate.
The embodiment of the present invention is separated grid conductor and conductive channel using oxide skin(coating) and barrier layer, which is height
K dielectric layer effectively increases the equivalent oxide thickness between grid conductor and conductive channel, and improves grid conductor and lead
Film quality between electric channel, effectively improves breakdown voltage, to improve the yield and reliability of 3D memory device.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (18)
1. a kind of 3D memory device, comprising:
Substrate；
Laminated construction above substrate, the laminated construction include the multiple gate conductor layers and multiple interlayers being alternately stacked
Insulating layer；
Multiple channel columns run through the laminated construction；
Conductive channel runs through the laminated construction, and is insulated by separation layer and the laminated construction；And
The multiple conductive channel and the separation layer are separated from each other by barrier layer.
2. 3D memory device according to claim 2, wherein the separation layer is oxide skin(coating).
3. 3D memory device according to claim 1, wherein the bottom end of the multiple channel column is formed via the substrate
Common source connection, the conductive channel provide the conductive path that the common source is connected to source electrode line.
4. 3D memory device according to claim 1, wherein it further include the doped region in the substrate, it is described to lead
Electric channel is contacted with the doped region.
5. 3D memory device according to claim 1, further includes: stratum nucleare, on the surface of the interlayer insulating film.
6. 3D memory device according to claim 1, wherein further include grid line gap, the grid line gap is through described
Laminated construction, so that the multiple grid conductor is divided into a plurality of grid line, the conductive channel is located in the grid line gap.
7. 3D memory device according to claim 6, wherein the separation layer is located on the side wall in the grid line gap,
The conductive channel fills the grid line gap, and the barrier layer is between the separation layer and the conductive channel.
8. 3D memory device according to claim 7, wherein a part of the separation layer is located in the laminated construction
Between adjacent interlayer insulating film.
9. 3D memory device according to claim 5, wherein further include barrier layer, be located at the barrier layer and conduction is logical
Between road.
10. 3D memory device according to claim 1, wherein the channel column includes the ditch formed around center stack
Channel layer, tunneling medium layer, charge storage layer and gate dielectric layer.
11. a kind of method for manufacturing 3D memory device, comprising:
Laminated construction and multiple channel columns through the laminated construction is formed on the substrate, first laminated construction includes handing over
For the multiple gate conductor layers and multiple interlayer insulating films of stacking；
Form the separation layer for closing the multiple grid conductor；
Form the barrier layer for covering the separation layer；And
Form the conductive channel for running through the laminated construction；
Wherein, the laminated construction is insulated by separation layer and the conductive channel, and the conductive channel passes through barrier layer and institute
Separation layer is stated to be separated from each other.
12. according to the method for claim 11, the separation layer is oxide skin(coating).
13. according to the method for claim 11, before forming laminated construction, the first laminated construction of formation, described first
Laminated construction includes the multiple sacrificial layers and multiple interlayer insulating films being alternately stacked；
The multiple sacrificial layer is replaced using multiple gate conductor layers, forms laminated construction.
14. according to the method for claim 13, wherein formed laminated construction the step of include:
Form the grid line gap for running through first laminated construction；
The multiple sacrificial layer in first laminated construction is removed by grid line gap, is connected with being formed with the grid line gap
Logical cavity；
Metal layer is filled in the grid line gap and the cavity by grid line gap；And
The metal layer is etched, grid line gap is re-formed, so that the metal layer to be divided into the institute of different level
State multiple grid conductors.
15. according to the method for claim 11, further includes: form doped region in the substrate.
16. according to the method for claim 14, the step of forming cavity and fill metal layer the step of between, also wrap
It includes: via the grid line gap, forming stratum nucleare on the surface of the multiple interlayer insulating film.
17. according to the method for claim 14, wherein in the step of re-forming grid line gap, the grid line gap
The grid conductor of same level is divided into a plurality of grid line.
18. according to the method for claim 11, wherein before forming conductive channel further include:
Barrier layer is deposited in the grid line gap.
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