CN109037227A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109037227A CN109037227A CN201811110733.5A CN201811110733A CN109037227A CN 109037227 A CN109037227 A CN 109037227A CN 201811110733 A CN201811110733 A CN 201811110733A CN 109037227 A CN109037227 A CN 109037227A
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/40—EEPROM devices comprising charge-trapping gate insulators characterised by the peripheral circuit region
Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.3D memory device includes: laminated construction, and the laminated construction includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked；Through multiple channel columns of the laminated construction；Multiple bit lines in one of first surface and second surface positioned at the laminated construction；And common source line of the first surface and second surface on another positioned at the laminated construction, wherein one end of the multiple channel column is connected respectively to the respective bit line in the multiple bit lines, and the other end is commonly connected to the common source line.The 3D memory device uses the common source line and bit line for being located at the first surface and second surface of 3D memory device stacked structure, compared with single side wiring, wiring density can be reduced, increase wiring width, reduce dead resistance and parasitic capacitance, storage density and access speed are improved, to improve the yield and reliability of 3D memory device.
Description
Technical field
The present invention relates to memory technology fields, more particularly, to 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor provides being electrically connected for transistor and external circuit using a large amount of metal lines.The increase of metal line density will will affect
The yield and reliability of 3D memory device.It is expected that the structure and its manufacturing method of 3D memory device are further improved, to improve 3D
The yield and reliability of memory device.
Summary of the invention
In view of the above problems, the purpose of the present invention is to provide a kind of 3D memory device and its manufacturing methods, wherein public
Source line and bit line are located at the first surface and second surface of stacked structure, so that wiring density is reduced, to improve 3D storage
The yield and reliability of device.
According to an aspect of the present invention, a kind of 3D memory device is provided characterized by comprising laminated construction, it is described
Laminated construction includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked；Through multiple channels of the laminated construction
Column；Multiple bit lines in one of first surface and second surface positioned at the laminated construction；And it is located at the laminated construction
Common source line of the first surface and second surface on another, wherein one end of the multiple channel column is separately connected
To the respective bit line in the multiple bit lines, the other end is commonly connected to the common source line.
Preferably, the multiple channel column includes first group of channel column and second group of channel column adjacent to each other, and described
The multiple bit lines that one group of channel column is connected are located on the first surface of the laminated construction, first group of channel
The common source line that column is connected is located on the second surface of the laminated construction, and second group of channel column is connected
The multiple bit lines be located on the second surface of the laminated construction, the public affairs that second group of channel column is connected
Common source line is located on the first surface of the laminated construction.
Preferably, further includes: the CMOS electricity adjacent with the first surface and/or second surface of the laminated construction
Road.
Preferably, further includes: conductive channel runs through the laminated construction；The first surface of the laminated construction and second
Multiple bit lines on one of surface are connected to that another is adjacent with the first surface and second surface by the conductive channel
Cmos circuit.
The multiple bit lines and the common source line for being preferably located at the first surface are connected to and first table
The adjacent cmos circuit in face；It is connected to and described second positioned at the multiple bit lines of the second surface and the common source line
The adjacent cmos circuit in surface.
According to another aspect of the present invention, a kind of manufacturing method of 3D memory device is provided, comprising: in laminated construction
Multiple bit lines are formed in one of first surface and second surface；And the first surface and the second table in the laminated construction
Face forms common source line on another.
Preferably, further includes: form the laminated construction, the laminated construction includes the multiple grid conductors being alternately stacked
With multiple interlayer insulating films；Form the multiple channel columns for running through the laminated construction；Wherein, one end of the multiple channel column point
The respective bit line not being connected in the multiple bit lines, the other end are commonly connected to the common source line.
Preferably, the multiple channel column includes first group of channel column and second group of channel column adjacent to each other, and described
The multiple bit lines that one group of channel column is connected are located on the first surface of the laminated construction, first group of channel
The common source line that column is connected is located on the second surface of the laminated construction, and second group of channel column is connected
The multiple bit lines be located on the second surface of the laminated construction, the public affairs that second group of channel column is connected
Common source line is located on the first surface of the laminated construction.
The 3D memory device and its manufacturing method provided according to the present invention, using being located at 3D memory device stacked structure
The common source line and bit line of first surface and second surface can reduce wiring density compared with single side wiring, increase wiring
Width reduces dead resistance and parasitic capacitance, improves storage density and access speed, thus improve 3D memory device yield and
Reliability.
In the prior art, using a large amount of through silicon vias (TSV, Through Silicon Via) and through array contact portion
The two-sided wiring of (TAC, Through Array Contacts) realization 3D memory device.Compared with prior art, the present invention is real
Apply the 3D memory of example using the common source line for the first surface and second surface for being located at 3D memory device stacked structure and
Bit line, common source line and bit line can be directly connected to by plain conductor and external circuit, reduce through silicon via and through array
The demand of contact portion, simplifies manufacturing process, improves the yield and reliability of 3D memory device.
Further, in the 3D memory device, using the two sides up and down for being located at the 3D memory device stacked structure
A plurality of first common source line being interspersed and a plurality of second common source line, and be located at the 3D memory device stack knot
A plurality of first bit line of the two sides up and down of structure being interspersed and a plurality of second bit line, so as to realize staggered two-sided connect
Line, compared with the double-sided wiring of noninterlace, staggered double-sided wiring can use both common source line isolation between bit line,
To further decrease dead resistance and parasitic capacitance, storage density and access speed are improved, to improve 3D memory device
Yield and reliability.
Further, in the 3D memory device, using the CMOS electricity for the two sides up and down for being located at the 3D memory device
Road, the cmos circuit of upper and lower two sides are connected with the drain electrode of upper and lower two sides respectively, not only reduce wiring density, and improve 3D
The service speed of memory device.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 shows the perspective views of 3D memory device according to an embodiment of the present invention.
3D memory device sectional view according to an embodiment of the present invention is shown respectively in Fig. 3 a and 3b.
Fig. 4 a to 4t shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
Fig. 5 shows 3D memory device sectional view according to a first embodiment of the present invention.
Fig. 6 shows 3D memory device sectional view according to a second embodiment of the present invention.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
In this application, term " semiconductor structure " refers to that is formed in each step of manufacture memory device entirely partly leads
The general designation of body structure, including all layers formed or region.Many specific details of the invention are described hereinafter,
Such as structure, material, size, treatment process and the technology of device, to be more clearly understood that the present invention.But as this field
Technical staff it will be appreciated that as, can not realize the present invention according to these specific details.
In the 3D memory device of NAND structure, the grid of selection transistor and memory transistor is provided using laminated construction
Conductor provides electrical connection using a large amount of metal lines.The increase of metal line density will not only increase process costs and work
Skill complexity, and the problems such as meeting generation circuit short circuit, parasitic capacitance increase, dead resistance increase.In addition, being distributed in side
The increase that wiring will lead to cmos circuit complexity affects 3D memory device to reduce the service speed of 3D memory device
Yield and reliability.
Present inventor notices the problem of yield and reliability of above-mentioned influence 3D memory device, thus propose into
The improved 3D memory device of one step and its manufacturing method.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line BL, and second end is connected to source electrode line SL.It deposits
Storage unit string 100 includes the multiple transistors being connected in series between the first end and a second end, comprising: first choice transistor
Q1, memory transistor M1 to M4 and the second selection transistor Q2.The grid of first choice transistor Q1 is connected to string selection line
The grid of SSL, the second selection transistor Q2 are connected to the ground selection line GSL.The grid of memory transistor M1 to M4 is respectively connected to
The respective word of wordline WL1 to WL4.
As shown in Figure 1 b, the first choice transistor Q1 of memory cell string 100 and the second selection transistor Q2 are respectively included
Grid conductor 122 and 123, memory transistor M1 to M4 respectively include grid conductor 121.Grid conductor 121,122 and 123 with deposit
The stacking order of transistor in storage unit string 100 is consistent, is separated each other using interlayer insulating film between adjacent grid conductor,
To form rhythmic structure of the fence.Further, memory cell string 100 includes channel column 110.Channel column 110 runs through gate stack knot
Structure.In the middle section of channel column 110, tunneling medium layer 112, charge storage are accompanied between grid conductor 121 and channel layer 111
Layer 113 and block media layer 114, to form memory transistor M1 to M4.At the both ends of channel column 110,122 He of grid conductor
Block media layer 114 is accompanied between 123 and channel layer 111, to form first choice transistor Q1 and the second selection transistor
Q2。
In this embodiment, channel layer 111 is for example made of DOPOS doped polycrystalline silicon, tunneling medium layer 112 and block media layer
114 are made of oxide respectively, such as silica, and charge storage layer 113 is by the insulating layer comprising quantum dot or nanocrystal
Composition, such as the silicon nitride of the particle comprising metal or semiconductor, grid conductor 121,122 and 123 are made of metal, such as
Tungsten.Channel layer 111 is used to provide the channel region of control selection transistor and memory transistor, the doping type of channel layer 111 and choosing
It is identical with the type of memory transistor to select transistor.For example, for the selection transistor and memory transistor of N-type, channel layer 111
It can be the polysilicon of n-type doping.
In this embodiment, the core of channel column 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Block media layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core of channel column 110 is attached
The insulating layer added, channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer 114 are formed around core
Laminated construction.
In this embodiment, first choice transistor Q1 and the second selection transistor Q2, memory transistor M1 to M4 are used
Public channel layer 111 and block media layer 114.In channel column 110, channel layer 111 provides the source-drain area of multiple transistors
And channel layer.In alternate embodiments, step independent of one another can be used, first choice transistor Q1 and the is respectively formed
The semiconductor layer and block media layer of two selection transistor Q2 and the semiconductor layer and block media of memory transistor M1 to M4
Layer.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling efficiency
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, ground selection line GSL is biased to greatly
About zero volts, so that the selection transistor Q2 for corresponding to ground selection line GSL is disconnected, string selection line SSL is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SSL.Further, bit line BIT2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 shows the perspective views of 3D memory device.For the sake of clarity, it is not shown in Fig. 2 each in 3D memory device
A insulating layer.
The 3D memory device 200 shown in this embodiment includes that 4*4 amounts to 16 memory cell strings 100, each storage
Unit string 100 includes 4 storage units, to form the memory array that 4*4*4 amounts to 64 storage units.It is appreciated that
The invention is not limited thereto, and 3D memory device may include any number of memory cell strings, for example, 1024, each storage unit
Number of memory cells in string can be it is any number of, for example, 32 or 64.
In 3D memory device, memory cell string respectively includes respective channel column 110 and public grid conductor
121,122 and 123.Grid conductor 121,122 and 123 is consistent with the stacking order of transistor in memory cell string 100, adjacent
Grid conductor between separated each other using interlayer insulating film, to form rhythmic structure of the fence 120.It is exhausted interlayer is not shown in the figure
Edge layer.
In this embodiment, channel column includes the multiple first group of channel column 110a and multiple second group of channel being interspersed
The internal structure of column 110b, channel column 110a and 110b are as shown in Figure 1 b, are no longer described in detail herein.Channel column 110a and
110b runs through rhythmic structure of the fence 120, and is arranged in array.First common source line 103a (not shown) is located at substrate 101
On, the second common source line 103b is located above semiconductor structure.The first end of multiple first group of channel column 110a is commonly connected to
First common source line 103a, the second end of multiple first group of channel column 110a are commonly connected to a plurality of first bit line BL1.Multiple
The second end of two groups of channel column 110b is commonly connected to the second common source line 103b, the first end of multiple second group of channel column 110b
It is commonly connected to a plurality of first bit line BL1.
The grid conductor 122 of first choice transistor Q1 is divided into difference by grid line gap (gate line slit) 161
Grid line.With multiple channel columns 110 of a line grid line be commonly connected to same string selection line (i.e. string selection line SSL1 extremely
One of SSL3).
The grid conductor 121 of memory transistor M1 and M4 are respectively connected to corresponding wordline.If memory transistor M1 and
The grid conductor 121 of M4 is divided into different grid lines by grid line gap 161, then the grid line of same level is via respective conductive logical
Road reaches interconnection layer 132, thus it is interconnected amongst one another, then same wordline is connected to via conductive channel 133.
The grid conductor of second selection transistor Q2 links into an integrated entity.If the grid conductor of the second selection transistor Q2
123 are divided into different grid lines by grid line gap 161, then grid line reaches interconnection layer 132 via respective conductive channel, thus that
This interconnection, then via conductive channel with being connected to same selection line GSL.
It further, in this embodiment can also include false channel column (not shown), false channel column and channel column
110 internal structure can be identical, and at least across at least part grid conductor in rhythmic structure of the fence.However, false ditch
Road column is not connected with bit line, so that mechanical support effect is provided solely for, without being used to form selection transistor and storage
Transistor.Therefore, false channel column does not form effective storage unit yet.
3D memory device sectional view according to an embodiment of the present invention is shown respectively in Fig. 3 a and 3b.The sectional view is along vertical
It is intercepted in stacking direction.
As shown in Figure 3a, it on perpendicular to stacking direction, observes from top to bottom in the semiconductor structure, in stacked structure
On second surface, the second common source line 103b is alternately distributed with a plurality of first bit line BL1.Second common source line 103b and multiple the
The second end connection of two groups of channel column 110b, a plurality of first wordline BL1 are connect with the second end of multiple first group of channel column 110a.
As shown in Figure 3b, it on perpendicular to stacking direction, observes from lower to upper in the semiconductor structure, in stacked structure
On first surface, the first common source line 103a is alternately distributed with a plurality of second bit line BL2.First common source line 103a and multiple the
The first end connection of one group of channel column 110a, a plurality of second bit line BL2 are connect with the first end of multiple second group of channel column 110b.
Fig. 4 a to 4q shows the sectional view in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.Institute
Sectional view is stated to intercept along the AA line in Fig. 2.
This method starts from the semiconductor structure that multiple well regions are formed on substrate 101, as shown in fig. 4 a.In the reality
It applies in example, semiconductor substrate 101 is, for example, monocrystalline substrate.
In this embodiment, for the ease of being programmed operation to the storage unit in 3D memory device, in substrate 101
Form multiple well regions.High pressure p-well 103 and high pressure P of the multiple well region for example including deep N-well 102, in deep N-well 102
The adjacent high pressure N trap 105 of trap 103, the P+ doped region 104 in high pressure p-well 103, the N+ in high pressure N trap 105 mix
Miscellaneous area 106.In this embodiment, common source line of the high pressure p-well 103 as channel column, high pressure N trap 105 are used for common source line
Precharge, P+ doped region 104 and N+ doped region 106 are respectively as contact zone to reduce contact resistance.As described below, to this
After high pressure p-well 103 is etched, as the common source line 103a of multiple first group of channel column, under insulating laminate structure
Side.
Further, such as on the surface of semiconductor structure exposure mask is formed, exposure mask is, for example, photoresist mask, so
After carry out anisotropic etching, in substrate 101 formed groove 160, as shown in figure 4 b and 4 c.In this embodiment, respectively to different
Property etching can use dry etching, such as ion beam milling etching, plasma etching, reactive ion etching, laser ablation.For example, logical
Control etching period is crossed, so that the close beneath for being etched in deep N-well 102 stops.
Further, after the etching by dissolving in a solvent or being ashed removal photoresist mask, such as Fig. 4 d institute
Show.
Further, the first insulating regions 153 are formed in groove 160, as shown in fig 4e.In this embodiment, first
Insulating regions 153 are for example made of silica.
Further, insulation stack structure is formed on substrate 101, as shown in fig. 4f.The insulating laminate structure includes handing over
For the multiple interlayer insulating films 151 and multiple sacrificial layers 152 of stacking.In this embodiment, interlayer insulating film 151 is for example by aoxidizing
Silicon composition, sacrificial layer 152 are for example made of silicon nitride.
As described below, sacrificial layer 152 will be replaced as grid conductor 122, and grid conductor is connected to wordline into 122 1 steps.
In order to form the conductive channel for reaching wordline from grid conductor 122, multiple sacrificial layers 152 are for example patterned step-like, that is, every
The marginal portion of a sacrificial layer 152 provides electrical connection area relative to the sacrificial layer exposure of top.In the figure of multiple sacrificial layers 152
After patterning step, insulating laminate structure can be covered using insulating layer.In Fig. 4 f by the interlayer between multiple sacrificial layers 152
Insulating layer 151 and the interlayer insulating film of covering insulating laminate structure are integrally shown.However, the invention is not limited thereto, can use
Multiple independent deposition steps are formed between multiple sacrificial layers 152 and its interlayer insulating film of top.
Further, the intermediate region in insulation stack structure (core region) forms channel hole 161, such as Fig. 4 g
It is shown.In this embodiment, such as on the surface of semiconductor structure photoresist mask is formed, anisotropy is then carried out
Etching forms channel hole 161 in insulation stack structure.Anisotropic etching can use dry etching, as ion beam milling etching,
Plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in the first common source line
The close beneath of 103a stops, and is etched in the close beneath stopping of the first insulating regions 153.After the etching by molten
Removal photoresist mask is dissolved or is ashed in agent.
Further, channel column 110 is formed in channel hole 161, as shown in figure 4h.The lower part of channel column 110 includes half
Conductor layer 116, semiconductor layer 116 are, for example, silicon selective epitaxial growth layer.Further, channel column 110 includes from upper part
Extend to the channel layer 111 of semiconductor layer 116.As shown, channel column 110 includes successively in the middle section of channel column 110
Tunneling medium layer 112, charge storage layer 113 and the block media layer 114 being stacked on channel layer 111, the two of channel column 110
End, channel column 110 include the block media layer 114 being stacked on channel layer 111 or semiconductor layer 116.The lower end of channel column 110
It is in contact with the high pressure p-well 103 in semiconductor substrate 101.In final 3D memory device, the upper end and position of channel column 110
Line is connected, to form effective storage unit.The structure of the channel column 110 is, for example, ONOP (oxide-nitride-
Oxide-polysilicon)
Further, grid line gap 161 (referring to fig. 2) is formed in insulating laminate structure, using multiple interlayer insulating films
151 are used as etching stopping layer, cavity are formed by etching removal sacrificial layer 152 via grid line gap 161, and use metal
Layer filling cavity is to form grid conductor 122, wherein and multiple grid conductors 122 and multiple interlayer insulating films 151 are alternately stacked,
To which multiple channel columns 110 run through rhythmic structure of the fence, as shown in figure 4i.
When forming grid line gap 161, anisotropic etching can be used, is lost for example, by using dry etching, such as ion beam milling
Quarter, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in semiconductor lining
The surface at bottom 101 nearby stops.
In this embodiment, grid conductor 122 is divided into a plurality of grid line by grid line gap 161.For this purpose, grid line gap 161
Through insulating laminate structure.
It is folded using isotropic etching removal insulation using grid line gap 161 as etchant channel when forming cavity
Sacrificial layer 152 in layer structure is to form cavity.Isotropic etching can be using wet etching or the gas phase erosion of selectivity
It carves.Use etching solution as etchant in wet etching, wherein in the etch solution by semiconductor structure submergence.In gas
Mutually use etching gas as etchant in etching, wherein semiconductor structure is exposed in etching gas.
What interlayer insulating film 151 and sacrificial layer 152 in insulating laminate structure were made of silica and silicon nitride respectively
Under situation, in wet etching can using phosphoric acid solution as etchant, in gas phase etching can use C4F8, C4F6,
One of CH2F2 and O2 or a variety of.In an etching step, etchant is full of grid line gap 161.It is sacrificial in insulating laminate structure
The end of domestic animal layer 152 is exposed in the opening in grid line gap 161, and therefore, sacrificial layer 152 touches etchant.Etchant is by grid
The opening of linear slit gap 161 is gradually to the etched inside sacrificial layer 152 of insulating laminate structure.Due to the selectivity of etchant, the erosion
It carves and removes sacrificial layer 152 relative to the interlayer insulating film 151 in insulating laminate structure.
When forming grid conductor 122, using grid line gap 161 as deposit channel, using atomic layer deposition
(ALD), metal layer is filled in grid line gap 161 and cavity.
In this embodiment, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is, for example, hexafluoro
Change tungsten WF6, the reducing gas of use is, for example, silane SiH4 or diborane B2H6.In the atomic layer deposition the step of, six are utilized
The chemisorption of the reaction product of tungsten fluoride WF6 and silane SiH4 obtains tungsten material and realizes deposition process.
In the semiconductor structure, selection transistor and memory transistor are formd.In the middle section of channel column 110,
Channel layer 111, tunneling medium layer 112, charge storage layer 113 and block media layer inside grid conductor 122 and channel column 110
114 together, forms memory transistor.Channel layer at the both ends of channel column 110, inside grid conductor 122 and channel column 110
111 (or semiconductor layers 116) and block media layer 114 together, form selection transistor.
Further, it is formed in the insulating layer above first group of channel column 110a above the first common source line 103a recessed
Slot 162, as shown in figure 4j.In this embodiment, such as on the surface of semiconductor structure photoresist mask is formed, then
Anisotropic etching is carried out, forms groove 162 in insulation stack structure.Anisotropic etching can use dry etching, such as
Ion beam milling etching, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in
Stop at a certain distance from first group of channel column 110a interior surface above first common source line 103a.After the etching by
Removal photoresist mask is dissolved or is ashed in solvent.
Further, conductor layer 171a is formed in groove 162, as shown in fig. 4k.In this embodiment, conductor layer 171a
Being electrically connected between channel column and bit line is provided, conductor layer 171a is, for example, tungsten.
Further, groove 163 is formed above second group of channel column 110b being located above the first insulating regions 153,
As shown in Fig. 4 l and 4m.In this embodiment, such as on the surface of semiconductor structure form photoresist mask, then into
Row anisotropic etching forms groove 163 in insulation stack structure.Anisotropic etching can use dry etching, such as from
Son milling etching, plasma etching, reactive ion etching, laser ablation.For example, by control etching period, so that being etched in the
Stop at a certain distance from two groups of channel column 110b interior surfaces.It is photic by dissolving in a solvent or being ashed removal after the etching
Etching mask.
Further, the second common source line 103b is formed in groove 163, as shown in Fig. 4 n.In this embodiment, second
Common source line 103b is, for example, high voltage p-well.
Further, a plurality of first bit line BL1, and the shape on the second common source line 103b are formed on conductor layer 171a
At pad 182, the second end of multiple first group of channel column 110a is commonly connected to the first bit line BL1, in a plurality of first bit line BL1
And second fill insulant 183 around common source line 103b, with a plurality of first bit line BL1 of fixation and the second common source line
103b, and keep the surface of insulating materials 183 smooth, as shown in Fig. 4 o.First bit line BL1 and pad 182 are for example by Ti/TiN
Or W composition, insulating materials 183 are, for example, silica.The method for keeping the surface of insulating materials 183 smooth is, for example, that chemical machinery is thrown
Light.
Further, semiconductor structure is overturn, and keeps substrate thinning, as shown in Fig. 4 p.For example, passing through grinding and/or erosion
Make substrate thinning at quarter, etching includes that dry etching or wet etching make to be etched on oxide material by controlling etching period
Stop.
Further, conductor layer 171b is formed in the top of second group of channel column 110b, as shown in Fig. 4 q.Conductor layer
171b provides being electrically connected between channel column and bit line, and conductor layer 171 is, for example, tungsten.
Further, a plurality of second bit line BL2, and the shape on the first common source line 103a are formed on conductor layer 171b
At pad 182, the first end of multiple second group of channel column 110b is commonly connected to the second bit line BL2, as shown in Fig. 4 r.Second
Line BL2 and pad 182 are for example made of Ti/TiN or W.
Further, multiple conductive channels are formed on the rhythmic structure of the fence of semiconductor structure, as shown in Fig. 4 s.The 3D is deposited
Multiple conductive channels in memory device respectively include the conductive column 131 as core and the insulating layer 134 as separation layer, described
Insulating layer 134 is for conductive column 131 and the conductive material of surrounding to be separated from each other.The multiple conductive channel is for example including conduction
Channel SL1, HV1.Conductive channel SL1 and HV1 are in contact with P+ doped region 104 and N+ doped region 106 respectively, to provide public
Being electrically connected between source line and high pressure N trap and external circuit.
It further, in this embodiment, should for the ease of being programmed operation to the storage unit in 3D memory device
3D memory device further includes the cmos circuit 200 for driving selection transistor and memory transistor, as shown in Fig. 4 t.CMOS electricity
Road 200 for example, is formed directly in substrate, or is formed directly into above array, or independently forms and then be bonded to semiconductor
In structure.
In this embodiment, independently forming the step of cmos circuit is then attached to semiconductor structure includes: by CMOS electricity
The interconnection layer 232 on road 200 is aligned with the interconnection layer 132 of semiconductor structure, then makes the interconnection layer 232 of cmos circuit 200 and half
The interconnection layer 132 of conductor structure contacts with each other, and executes combination processing and has formed bonding interface.Combination processing is for example including plasma
Body treatment process, wet processing and/or heat treatment process, so that the surface of the interconnection layer 232 of cmos circuit 200 and semiconductor junction
The surface formation of the interconnection layer 132 of structure is managed or chemical bonding.In some embodiments, the interconnection layer of semiconductor structure 132
For example silicon oxide layer, the interconnection layer 232 of cmos circuit 200 are, for example, silicon nitride layer.In some embodiments, semiconductor structure
The interconnection layer 232 of interconnection layer 132 and cmos circuit 200 for example includes copper.
Fig. 5 shows 3D memory device sectional view according to a first embodiment of the present invention.The sectional view is along the AA in Fig. 2
Line interception.
As shown in figure 5, cmos circuit 200 for example above or below semiconductor structure, is located on semiconductor structure
Electrical connection is realized by multiple conductive channels between the drain electrode of lower two sides, is then bonded to external cmos circuit 200.In the implementation
In example, the drain electrode includes that a plurality of first bit line BL1 and a plurality of second bit line BL2, multiple conductive channels are respectively included as core
The conductive column 131 in portion and the insulating layer 134 of separation layer, the insulating layer 134 are used for the conductive material of conductive column 131 and surrounding
It is separated from each other, cmos circuit 200 can be simultaneously to first group of channel column 110a transistor constituted with rhythmic structure of the fence and second group
The transistor that channel column 110b is constituted with rhythmic structure of the fence is operated.
Fig. 6 shows 3D memory device sectional view according to a second embodiment of the present invention.The sectional view is along the AA in Fig. 2
Line interception.
As shown in fig. 6, cmos circuit 300 and cmos circuit 200 are for example located above and below semiconductor structure,
The drain electrode of two sides is connect with cmos circuit 300 and cmos circuit 200 respectively above and below semiconductor structure.In this embodiment,
The drain electrode includes that a plurality of first bit line BL1 and a plurality of second bit line BL2, multiple conductive channels respectively include leading as core
The insulating layer 134 of electric column 131 and separation layer, the insulating layer 134 be used for by the conductive material of conductive column 131 and surrounding each other every
It opens, cmos circuit 300 controls the transistor that first group of channel column 110a and rhythmic structure of the fence are constituted, the control of cmos circuit 200 the
The transistor that two groups of channel column 110b and rhythmic structure of the fence are constituted.The two sides distribution of cmos circuit reduces wiring density, and
Two groups of COMS circuits further improve the service speed of 3D memory device to the control respectively of two group transistors.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (8)
1. a kind of 3D memory device characterized by comprising
Laminated construction, the laminated construction include the multiple grid conductors and multiple interlayer insulating films being alternately stacked；
Through multiple channel columns of the laminated construction；
Multiple bit lines in one of first surface and second surface positioned at the laminated construction；And
Positioned at common source line of the first surface and second surface on another of the laminated construction,
Wherein, one end of the multiple channel column is connected respectively to the respective bit line in the multiple bit lines, and the other end connects jointly
It is connected to the common source line.
2. 3D memory device according to claim 1, wherein the multiple channel column includes first group of ditch adjacent to each other
Road column and second group of channel column,
The multiple bit lines that first group of channel column is connected are located on the first surface of the laminated construction, described
The common source line that first group of channel column is connected is located on the second surface of the laminated construction,
The multiple bit lines that second group of channel column is connected are located on the second surface of the laminated construction, described
The common source line that second group of channel column is connected is located on the first surface of the laminated construction.
3. 3D memory device according to claim 1, further includes: with the first surface of the laminated construction and/or
The adjacent cmos circuit of second surface.
4. 3D memory device according to claim 3, further includes:
Conductive channel runs through the laminated construction；
Multiple bit lines in one of first surface and second surface of the laminated construction by the conductive channel be connected to
Another adjacent cmos circuit of the first surface and second surface.
5. 3D memory device according to claim 3, wherein
It is connected to positioned at the multiple bit lines of the first surface and the common source line adjacent with the first surface
Cmos circuit；
It is connected to positioned at the multiple bit lines of the second surface and the common source line adjacent with the second surface
Cmos circuit.
6. a kind of manufacturing method of 3D memory device, comprising:
Multiple bit lines are formed in one of first surface and second surface of laminated construction；And
Common source line is formed on another in the first surface and second surface of the laminated construction.
7. manufacturing method according to claim 6, further includes:
The laminated construction is formed, the laminated construction includes the multiple grid conductors and multiple interlayer insulating films being alternately stacked；
Form the multiple channel columns for running through the laminated construction；
Wherein, one end of the multiple channel column is connected respectively to the respective bit line in the multiple bit lines, and the other end connects jointly
It is connected to the common source line.
8. manufacturing method according to claim 7, wherein the multiple channel column includes first group of channel adjacent to each other
Column and second group of channel column,
The multiple bit lines that first group of channel column is connected are located on the first surface of the laminated construction, described
The common source line that first group of channel column is connected is located on the second surface of the laminated construction,
The multiple bit lines that second group of channel column is connected are located on the second surface of the laminated construction, described
The common source line that second group of channel column is connected is located on the first surface of the laminated construction.
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