CN109698201A - 3D memory device and its manufacturing method - Google Patents
3D memory device and its manufacturing method Download PDFInfo
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- CN109698201A CN109698201A CN201811426714.3A CN201811426714A CN109698201A CN 109698201 A CN109698201 A CN 109698201A CN 201811426714 A CN201811426714 A CN 201811426714A CN 109698201 A CN109698201 A CN 109698201A
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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Abstract
This application discloses a kind of 3D memory device and its manufacturing methods.The 3D memory device, comprising: semiconductor substrate；Rhythmic structure of the fence is located in semiconductor substrate, including the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；And multiple channel holes, it is separately positioned in corresponding storage region, each channel hole is electrically connected through rhythmic structure of the fence and with semiconductor substrate；Multiple isolation structures are separately positioned in corresponding area of isolation, and each isolation structure is through rhythmic structure of the fence to realize the isolation between multiple storage regions；Multiple conducting channels, it is distributed in area of isolation and storage region, each conducting channel is electrically connected through rhythmic structure of the fence and with semiconductor substrate, and each channel hole is at least disposed adjacent with a conducting channel, and each conducting channel is used to power by semiconductor substrate to surrounding channel hole.3D memory device according to an embodiment of the present invention will not be because of the excessive damage for causing interlayer insulating film of etching.
Description
Technical field
The present invention relates to memory technologies, more particularly, to a kind of 3D memory device and its manufacturing method.
Background technique
The raising of the storage density of memory device and the progress of semiconductor fabrication process are closely related.With semiconductors manufacture
The characteristic size of technique is smaller and smaller, and the storage density of memory device is higher and higher.In order to further increase storage density,
Develop the memory device (that is, 3D memory device) of three-dimensional structure.3D memory device includes along the multiple of vertical direction stacking
Storage unit can double up integrated level on the chip of unit area, and can reduce cost.
Existing 3D memory device is mainly used as non-volatile flash memory.Two kinds of main non-volatile flash technology difference
Using NAND and NOR structure.Compared with NOR memory device, the reading speed in nand memory part is slightly slow, but writing speed
Fastly, erasing operation is simple, and smaller storage unit may be implemented, to reach higher storage density.Therefore, it uses
The 3D memory device of NAND structure has been widely used.
The 3D memory device of NAND structure includes: that rhythmic structure of the fence, the channel hole through rhythmic structure of the fence and conduction are logical
Road provides the gate conductor layer of selection transistor and memory transistor using rhythmic structure of the fence, and it is brilliant to provide selection using channel hole
The channel layer of body pipe and memory transistor and gate medium lamination, and the interconnection using conductive channel realization memory cell string.
However, in 3D memory device, firstly, in order to avoid tungsten is filled unevenly in grid line separate slot, Yi Jiwei
It avoids needing because of short circuit caused by insulating layer damage by grid line separate slot between the tungsten and gate conductor layer in grid line separate slot
It is sized for very greatly, since grid line separate slot occupies the big quantity space of memory device, for the storage density for guaranteeing memory device, needs
By the very little that is sized in channel hole, therefore improve the technology difficulty in production channel hole.
Secondly, need to remove the sacrificial layer of its two sides via grid line separate slot in the technique for forming gate conductor layer, by
It is spaced apart between each grid line separate slot, excessive etching is needed to guarantee to completely remove sacrificial layer, therefore can damage and lean on
The interlayer insulating film of nearly grid line separate slot.
Finally, due to which the conductive channel each formed in grid line separate slot needs to supply the multiple rows of channel hole for being located at its two sides
Electricity, the channel hole close to conductive channel and the channel hole far from conductive channel are since due to, the voltage of acquisition is simultaneously uneven.
It is expected that being further improved the structure and its manufacturing method of 3D memory device, channel hole is powered in realization real
Meanwhile further increasing the yield and reliability of device.
Summary of the invention
The object of the present invention is to provide a kind of improved 3D memory device and its manufacturing methods, pass through conducting channel Xiang Qizhou
The channel hole power supply enclosed, realizes the purpose of the yield and reliability that improve device.
According to an aspect of the present invention, a kind of 3D memory device is provided, comprising: semiconductor substrate；Rhythmic structure of the fence is located at
In the semiconductor substrate, including the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；Multiple channel holes, respectively
Be arranged in corresponding storage region, each channel hole through the rhythmic structure of the fence and with the semiconductor substrate electricity phase
Even；Multiple isolation structures are separately positioned in corresponding area of isolation, and each isolation structure runs through the rhythmic structure of the fence
To realize the isolation between multiple storage regions；And multiple conducting channels, it is distributed in the area of isolation and described deposits
In storage area domain, each conducting channel is electrically connected through the rhythmic structure of the fence and with the semiconductor substrate, each described
Channel hole is at least disposed adjacent with a conducting channel, each conducting channel be used for by the semiconductor substrate to
The surrounding channel hole power supply, wherein in each area of isolation, the isolation structure at least surrounds corresponding institute
State the side wall of conducting channel.
Preferably, each area of isolation is in a strip shape and is arranged in parallel in a second direction, is located at each isolated area
Multiple conducting channels in domain are arranged along first direction, wherein the second direction and the first direction are in 90 °.
Multiple conducting channels except each area of isolation are preferably located to arrange along the second direction.
Preferably, the multiple channel hole is arranged in array, and the channel hole of every row and the channel hole of adjacent rows are staggered.
Preferably, the area of isolation is set every the channel hole of predetermined number of lines, between the area of isolation described in two rows
Form a storage region.
Preferably, the predetermined number of lines includes 3 rows.
Preferably, in area of isolation in every line, at least partly described isolation structure is spaced in advance in a first direction
Set a distance forms channel, and the adjacent storage region is connected.
Preferably, along the first direction every the one column conducting channel of the channel hole of predetermined columns setting.
Preferably, one group of channel hole is provided with around each conducting channel, one group of channel hole is with hexagon point
Cloth is on the periphery of the conducting channel.
Preferably, further include second insulating layer, surround the conducting channel, the conducting channel insulate by described second
Layer is separated with the multiple gate conductor layer.
According to another aspect of the present invention, a kind of method for manufacturing 3D memory device is provided, comprising: serve as a contrast in the semiconductor
Rhythmic structure of the fence is formed on bottom, including the multiple gate conductor layers and multiple interlayer insulating films being alternately stacked；Respectively corresponding
In storage region, the multiple channel holes being electrically connected with the semiconductor substrate are formed through the rhythmic structure of the fence；Respectively in phase
In the area of isolation answered, multiple isolation structures are formed through the rhythmic structure of the fence, to realize between multiple storage regions
Isolation；And respectively in the corresponding storage region and the area of isolation, through the rhythmic structure of the fence formed with
Multiple conducting channels that the semiconductor substrate is electrically connected, each channel hole is at least adjacent with a conducting channel to be set
It sets, each conducting channel is used to power by the semiconductor substrate to the surrounding channel hole, wherein each
In the area of isolation, the isolation structure at least surrounds the side wall of the corresponding conducting channel.
Preferably, each area of isolation is in a strip shape and is arranged in parallel in a second direction, is located at each isolated area
Multiple conducting channels in domain are arranged along first direction, and the second direction and the first direction are in 90 °.
Multiple conducting channels except each area of isolation are preferably located to arrange along the second direction.
Preferably, forming institute includes: to form insulating laminate knot on the semiconductor substrate multiple the step of stating channel hole
Structure, including the multiple interlayer insulating film and multiple sacrificial layers being alternately stacked；In the storage region, run through the insulation
Laminated construction forms multiple first through hole；And channel layer, tunneling medium layer, charge storage layer are filled in the first through hole
And gate dielectric layer is to form the channel hole.
Preferably, the step of forming the multiple conducting channel include: in the storage region with the area of isolation
It is interior, multiple second through-holes are formed through the insulating laminate structure；And in second through-hole fill conductive material to
Form the conducting channel, wherein the multiple second through-hole is formed in same step with the multiple first through hole.
Preferably, the step of forming the isolation structure includes: to run through the insulating laminate knot in the area of isolation
It is configured to grid line gap；And fill oxide forms the isolation structure in the grid line gap.
Preferably, channel layer, tunneling medium layer, charge storage layer and gate dielectric layer are filled in the first through hole
Before step, the step of forming the multiple channel hole further include: the oxide is filled in the multiple first through hole；With
And fill the oxide in the multiple first through hole of removal, wherein the oxide in the multiple first through hole with
Oxide in the grid line gap is formed in same step.
Preferably, before the step of conductive material is filled in second through-hole, the multiple conducting channel is formed
Step further include: fill the oxide in the multiple second through-hole；And it is filled in the multiple second through-hole of removal
The oxide, wherein the oxide in the multiple second through-hole is with the oxide in the grid line gap same
It is formed in step.
It preferably, further include the second insulation of side wall formation in second through-hole before filling the conductive material
Layer, the second insulating layer are contacted with the gate conductor layer.
Preferably, the step of forming the rhythmic structure of the fence includes: in removing the multiple second through-hole described in filling
After the step of oxide, the multiple sacrificial layer is replaced with into the multiple grid conductor via the multiple second through-hole
Layer.
3D memory device according to an embodiment of the present invention and its manufacturing method, by being formed through rhythmic structure of the fence and with half
Multiple channel holes that conductor substrate is electrically connected, and formed be distributed in it is between multiple channel holes, through rhythmic structure of the fence and with
Multiple conducting channels that semiconductor substrate is electrically connected realize each conducting channel and pass through semiconductor substrate to surrounding channel
The purpose of hole power supply improves 3D memory device to channel hole using conducting channel instead of conductive channel in the prior art
The efficiency of power supply, each channel hole obtain unified voltage.
3D memory device according to an embodiment of the present invention and its manufacturing method, by through rhythmic structure of the fence and and semiconductor
Multiple conducting channels that substrate is electrically connected realize the purpose powered to surrounding channel hole, come relative to original conductive channel
It says, the technique for forming conducting channel is more easier, even if the tungsten or polysilicon filling in some conducting channel are uneven, causes this
Conducting channel cannot power to surrounding channel hole, and other conducting channels can also be worked normally to replace the conducting channel, and
Device will not be impacted.
3D memory device according to an embodiment of the present invention and its manufacturing method are saved due to eliminating original grid line separate slot
The space of memory device has been saved, the size in channel hole can be increased, to reduce the technology difficulty to form channel hole.
3D memory device according to an embodiment of the present invention and its manufacturing method, by the isolation for running through the rhythmic structure of the fence
Storage unit is separated into multiple storage regions by structure, further through the channel between isolation structure, by adjacent storage region phase
Even, achieved the purpose that for storage unit to be optionally combined.
3D memory device according to an embodiment of the present invention and its manufacturing method, by being arranged the second through-hole in first through hole
Between, surrounding sacrificial layer is replaced with into gate conductor layer via the second through-hole, interlayer will not be caused exhausted because of etching is excessive
The damage of edge layer.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from.
The equivalent circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.
Fig. 2 a shows the perspective view of 3D memory device according to an embodiment of the present invention.
Fig. 2 b shows the sectional view of the line A-A along Fig. 2 a.
Fig. 2 c shows the sectional view of the line B-B along Fig. 2 a.
Fig. 2 d shows the sectional view of the line C-C along Fig. 2 a.
Fig. 3 to Figure 12 shows the schematic diagram in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
Figure 13 a and Figure 13 b show effect analysis schematic diagram.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical element is using similar attached
Icon is remembered to indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown certain
Well known part.For brevity, the semiconductor structure obtained after several steps can be described in a width figure.
It should be appreciated that being known as being located at another floor, another area when by a floor, a region in the structure of outlines device
When domain " above " or " top ", can refer to above another layer, another region, or its with another layer, it is another
Also comprising other layers or region between a region.Also, if device overturn, this layer, a region will be located at it is another
Layer, another region " following " or " lower section ".
If will use " directly exist ... herein to describe located immediately at another layer, another region above scenario
Above " or " ... abut above and therewith " form of presentation.
Many specific details of the invention, such as structure, material, size, the processing work of device is described hereinafter
Skill and technology, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not press
The present invention is realized according to these specific details.
The present invention can be presented in a variety of manners, some of them example explained below.
The circuit diagram and structural schematic diagram of the memory cell string of 3D memory device is shown respectively in Fig. 1 a and 1b.In the embodiment
Shown in memory cell string include 4 storage units situation.It is appreciated that the invention is not limited thereto, in memory cell string
Number of memory cells can be to be any number of, for example, 32 or 64.
As shown in Figure 1a, the first end of memory cell string 100 is connected to bit line (Bit-Line, BL), and second end is connected to
Source electrode line (Source Line, SL).Memory cell string 100 includes the multiple crystalline substances being connected in series between the first end and a second end
Body pipe, comprising: first choice transistor Q1, memory transistor M1 to M4 and the second selection transistor Q2.First choice crystal
The grid of pipe Q1 is connected to string selection line (Selection Gate for Drain, SGD), the grid of the second selection transistor Q2
It is connected to source selection line (Selection Gate for Source, SGS).The grid of memory transistor M1 to M4 is separately connected
To the respective word of wordline (Word-Line) WL1 to WL4.
As shown in Figure 1 b, the selection transistor Q1 and Q2 of memory cell string 100 respectively include gate conductor layer 122 and 123,
Memory transistor M1 to M4 respectively includes gate conductor layer 121.In gate conductor layer 121,122 and 123 and memory cell string 100
Transistor stacking order it is consistent, separated each other using interlayer insulating film between adjacent gate conductor layer, to form grid
Laminated construction.Further, memory cell string 100 includes channel hole 110.Channel hole 110 is adjacent with rhythmic structure of the fence or passes through
Wear rhythmic structure of the fence.In the middle section in channel hole 110, tunneling medium layer is accompanied between gate conductor layer 121 and channel layer 111
112, charge storage layer 113 and gate dielectric layer 114, to form memory transistor M1 to M4.In the ideal case, in channel hole
110 both ends accompany gate dielectric layer 114 between gate conductor layer 122 and 123 and channel layer 111, to form selection transistor
Q1 and Q2.But since technique limits, tunneling medium layer 112, electricity can also be accompanied between gate conductor layer 122 and channel layer 111
Lotus accumulation layer 113 and gate dielectric layer 114, as shown in Figure 1 b.
In this embodiment, channel layer 111 is for example made of polysilicon, and tunneling medium layer 112 and gate dielectric layer 114 are distinguished
It is made of oxide, such as silica, charge storage layer 113 is made of the insulating layer comprising quantum dot or nanocrystal, example
The silicon nitride of particle such as comprising metal or semiconductor, gate conductor layer 121,122 and 123 is made of metal, such as tungsten.Ditch
Channel layer 111 is used to provide control selection transistor and control the channel region of transistor, the doping type and selection crystal of channel layer 111
It manages identical with the type of control transistor.For example, the selection transistor and control transistor, channel layer 111 for N-type can be
The polysilicon of n-type doping.
In this embodiment, the core in channel hole 110 is channel layer 111, tunneling medium layer 112,113 and of charge storage layer
Gate dielectric layer 114 forms the laminated construction for surrounding core wall.In alternate embodiments, the core in channel hole 110 is additional
Insulating layer, channel layer 111, tunneling medium layer 112, charge storage layer 113 and gate dielectric layer 114 are formed around semiconductor layer
Laminated construction.
In this embodiment, selection transistor Q1 and Q2, memory transistor M1 to M4 use public channel layer 111 and grid
Dielectric layer 114.In channel hole 110, channel layer 111 provides the source-drain area and channel layer of multiple transistors.In the implementation of substitution
Example in, can use step independent of one another, be respectively formed selection transistor Q1 and Q2 semiconductor layer and gate dielectric layer and
The semiconductor layer and gate dielectric layer of memory transistor M1 to M4.In channel hole 110, the semiconductor layer of selection transistor Q1 and Q2
It is electrically connected to each other with the semiconductor layer of memory transistor M1 to M4.
In write operation, memory cell string 100 writes data into memory transistor M1 into M4 using FN tunneling effect
Selected memory transistor.By taking memory transistor M2 as an example, while source electrode line SL ground connection, source selection line SGS is biased to greatly
About zero volts, so that the selection transistor Q2 corresponding to source selection line SGS is disconnected, string selection line SGD is biased to high voltage
VDD, so that corresponding to the selection transistor Q1 conducting of string selection line SGD.Further, bit line BL2 is grounded, wordline WL2 biasing
In program voltage VPG, such as 20V or so, remaining wordline is offset to low-voltage VPS1.Due to only selected memory transistor M2's
Word line voltage is higher than tunneling voltage, and therefore, the electronics of the channel region of memory transistor M2 is reached via tunneling medium layer 112
Charge storage layer 113, so that data are transformed into charge storage in the charge storage layer 113 of memory transistor M2.
In read operation, selected memory transistor of the memory cell string 100 according to memory transistor M1 into M4 is led
Logical state judges the quantity of electric charge in charge storage layer, to obtain the data of quantity of electric charge characterization.By taking memory transistor M2 as an example,
Wordline WL2, which is offset to, reads voltage VRD, remaining wordline is offset to high voltage VPS2.The on state of memory transistor M2 and its
Threshold voltage is related, i.e., related to the quantity of electric charge in charge storage layer, thus can be with according to the on state of memory transistor M2
Judge data value.Memory transistor M1, M3 and M4 are in the conductive state always, and therefore, the on state of memory cell string 100 takes
Certainly in the on state of memory transistor M2.Control circuit is according to the electric signal judgement storage detected on bit line BL and source electrode line SL
The on state of transistor M2, to obtain the data stored in memory transistor M2.
Fig. 2 a shows the perspective view of 3D memory device according to an embodiment of the present invention, and the X-direction in Fig. 2 a is 3D memory
The length direction of part, Y-direction are the width direction of 3D memory device, the short transverse that Z-direction is 3D memory device；Fig. 2 b is shown
Along the sectional view of the line A-A of Fig. 2 a；Fig. 2 c shows the sectional view of the line B-B along Fig. 2 a；Fig. 2 d shows cutting for the line C-C along Fig. 2 a
Face figure.For the sake of clarity, each insulating layer in 3D memory device is not shown in fig. 2 a.
As shown in Fig. 2 a to Fig. 2 d, 3D memory device shown in the present embodiment includes: semiconductor substrate 101, gate stack
Structure 120, multiple channel holes 110, multiple conducting channels 130, multiple isolation structures 140 and second insulating layer 150.
In the present embodiment, rhythmic structure of the fence 120 is located at the top of semiconductor substrate 101, and each channel hole 110 is at least with one
A conducting channel 130 is disposed adjacent, and in storage region 10, multiple channel holes 110 are served as a contrast through rhythmic structure of the fence 120 and semiconductor
Bottom 101 is electrically connected.In area of isolation 20, multiple isolation structures 140 extend through rhythmic structure of the fence 120 and semiconductor substrate
101 contacts, to realize the isolation between multiple storage regions 10.In storage region 10 and area of isolation 20, multiple conduction ditches
Road 130 is electrically connected through rhythmic structure of the fence 120 and semiconductor substrate 101, with to by semiconductor substrate 101 to surrounding ditch
Road hole 110 powers.
Specifically, multiple channel holes 110 are arranged in array, 110 staggered row of channel hole in every row channel hole 110 and adjacent rows
Cloth.The internal structure in each channel hole 110 is as shown in Figure 1 b, is no longer described in detail herein.
Rhythmic structure of the fence 120 includes the multiple gate conductor layers 121,122,123 and multiple interlayer insulating films being alternately stacked
161.Memory cell string respectively includes part corresponding to respective channel hole 110 and public gate conductor layer 121,122
With 123.The grid consistent, adjacent with the stacking order of transistor in memory cell string 100 of gate conductor layer 121,122 and 123
It is separated each other using interlayer insulating film 161 between the conductor layer of pole, to form rhythmic structure of the fence 120.
Multiple conducting channels 130 in each area of isolation 20 are arranged in X direction (first direction), are deposited positioned at each
Multiple conducting channels 130 in storage area domain 10 (except area of isolation 20) are arranged along Y-direction (second direction), second direction and institute
First direction is stated in 90 °.A line conducting channel 130 and isolation structure are set every the channel hole 110 of predetermined number of lines along Y-direction
140, a column conducting channel 130 is set every the channel hole 110 of predetermined columns in X direction.Multiple conducting channels 130 of same row
Or it can be commonly connected to same bit line with the first end of multiple conducting channels 130 of a line, second end is commonly connected to substrate
101, and common source connection is formed via substrate 101.
In certain embodiments, predetermined number of lines is 3 rows, and predetermined columns is 5 column, can around each conducting channel 130
With one group of channel hole 110, this group of channel hole 110 is distributed in the periphery of conducting channel 130 with hexagon, and conducting channel 130 can
To be powered by semiconductor substrate 101 to surrounding 6 channel holes 110.
Each area of isolation 20 is in a strip shape and is arranged in parallel along Y-direction, and multiple isolation structures 140 at least surround corresponding lead
The side wall of electric channel 130, in area of isolation 20 in every line, be at least partially isolated structure 140 be spaced in the X direction it is predetermined
Distance forms channel, and adjacent storage region 10 is connected.For example, showing two storage regions 10 and three in figure 2 c
Area of isolation 20 is located in the middle area of isolation 20 and respectively will separate the storage region 10 of its two sides, in figure 2d, due to
Among isolation structure 140 there are notch formed channel, therefore and be not present intermediate isolating region 20, to be deposited two adjacent
Storage area domain 10 is connected.Wherein, the material of isolation structure 140 includes oxide.
Second insulating layer 150 surrounds conducting channel 130, and conducting channel 130 is led by second insulating layer 150 and multiple grids
Body layer 121,122,123 separates, wherein the material of conducting channel 130 includes tungsten and/or polysilicon.
In some preferred embodiments, for example including cmos circuit in substrate semiconductor substrate 101.Using conducting channel
Being electrically connected between 130 offer cmos circuits and external circuit.
In some another preferred embodiments, the 3D memory device of the present embodiment further includes false channel hole, for providing machine
Tool supporting role.
Fig. 3 to Figure 12 shows the schematic diagram in each stage of 3D memory device manufacturing method according to an embodiment of the present invention.
It is described in detail below in conjunction with manufacturing method of the Fig. 3 to Figure 12 to invention memory construction.
The method of the embodiment of the present invention starts from semiconductor substrate 101, and formation is alternately stacked in semiconductor substrate 101
Multiple interlayer insulating films 161 and multiple sacrificial layers 162, to form insulating laminate structure 160, as shown in Figure 3.
In this step, for example, by using chemical vapor deposition process (Chemical Vapor Deposition, CVD), object
Physical vapor deposition technique (Physical Vapor Deposition, PVD) successively forms multiple layers in semiconductor substrate 101
Between insulating layer 161 and multiple sacrificial layers 162, wherein the material of multiple interlayer insulating films 161 includes oxide, such as silica,
The material of multiple sacrificial layers 162 includes nitride, such as silicon nitride.
Further, multiple second through-holes 102 and multiple first through hole 103 are formed through insulating laminate structure 160, such as schemed
Shown in 4a to Fig. 4 c, wherein Fig. 4 b shows the sectional view of the line A-A along Fig. 4 a, and Fig. 4 c shows the section of the line B-B along Fig. 4 a
Scheme, the X-direction in Fig. 4 a is the length direction of 3D memory device, the width direction that Y-direction is 3D memory device.
In this step, for example, by using photoetching, etching technics patterning insulating laminate structure 160 and part semiconductor substrate
101 form the multiple circular holes being arranged in array, and each column circular hole is staggered, and some of circular holes are used as second in the subsequent process
Through-hole 102 forms conducting channel, remaining circular hole is used as first through hole 103 to form channel hole in the subsequent process.
In the particular embodiment, one group of second through-hole is arranged in the first through hole 103 along Y-direction every the first predetermined number of lines
102, in every group of second through-hole 102, it is arranged one second every the first through hole 103 every the first predetermined columns in X direction
Through-hole 102, the first predetermined number of lines include two rows, and the first predetermined columns includes 4 column.However the embodiment of the present invention is not limited to
This, those skilled in the art can carry out other settings to the second through-hole 102 and the distribution of first through hole 103 as needed.
Further, grid line gap 104 is formed through insulating laminate structure 160 at the position of every the second through-hole of row 102,
Shown in as shown in Figure 5 a to 5 c, wherein Figure 5b shows that the sectional view of the line A-A along Fig. 5 a, Fig. 5 c shows cutting for the line B-B along Fig. 5 a
Face figure, the X-direction in Fig. 5 a is the length direction of 3D memory device, the width direction that Y-direction is 3D memory device.
In this step, insulating laminate structure 160, every row grid line gap 104 are patterned for example, by using photoetching, etching technics
The insulating laminate structure 160 of its two sides is separated.
In some preferred embodiments, it is spaced first in a first direction positioned at at least partly grid line gap 104 of colleague
Preset distance, for example, grid line gap 104 in every line is spaced the first preset distance in a first direction, as shown in Figure 2 a.
Further, covering insulating laminate 160 is respectively in the second through-hole 102, first through hole 103 and grid line gap 104
Middle fill oxide is to form the first insulating layer 170, as shown in Fig. 6 a to Fig. 6 c, wherein Fig. 6 b shows the line A-A along Fig. 6 a
Sectional view, Fig. 6 c shows the sectional view of the line B-B along Fig. 6 a, and the X-direction in Fig. 6 a is length direction, the Y of 3D memory device
Direction is the width direction of 3D memory device.
In this step, for example, by using chemical vapor deposition process, physical gas-phase deposition rapidly in the second through-hole
102, fill oxide in first through hole 103 and grid line gap 104, oxide may include silica.
Further, the first insulating layer 170 of covering forms the first mask 107, as shown in Fig. 6 a to Fig. 6 c.
In this step, the exposure of the first insulating layer 170 at first through hole will be located at by the first mask 107.
Further, the first insulating layer 170 is patterned using etching technics by the first mask 107, removes first through hole
Oxide in 103 so that expose first through hole 103 again, as shown in Fig. 7 a to Fig. 7 c, wherein Fig. 7 b shows the A- along Fig. 7 a
The sectional view of A line, Fig. 7 c show the sectional view of the line B-B along Fig. 7 a, and the X-direction in Fig. 7 a is the length side of 3D memory device
It is the width direction of 3D memory device to, Y-direction.
Further, remove the first mask 107, and in first through hole 103 formed include channel layer, tunneling medium layer,
The channel hole 110 of charge storage layer and gate dielectric layer, as shown in Fig. 8 a to Fig. 8 c, wherein Fig. 8 b shows the A-A along Fig. 8 a
The sectional view of line, Fig. 8 c show the sectional view of the line B-B along Fig. 8 a, the X-direction in Fig. 8 a be 3D memory device length direction,
Y-direction is the width direction of 3D memory device.
Further, the first insulating layer 170 of covering forms the second mask 108, as shown in Fig. 9 a to Fig. 9 b, wherein Fig. 9 b
The sectional view of line A-A along Fig. 9 a is shown, the X-direction in Fig. 9 a is the length direction of 3D memory device, Y-direction is 3D memory
The width direction of part.
In this step, the first insulating layer 170 exposure of the second through hole will be located at by the second mask 108.
Further, the first insulating layer 170 is patterned using etching technics by the second mask 108, removes the second through-hole
Oxide in 102 so that expose the second through-hole 102 again, as shown in Figure 10 a to Figure 10 b, wherein Figure 10 b is shown along Figure 10 a
Line A-A sectional view, the X-direction in Figure 10 a is the length direction of 3D memory device, the width that Y-direction is 3D memory device
Direction.
Further, using the second through-hole 102 as etchant channel, insulating laminate knot is removed using isotropic etching
Sacrificial layer 162 in structure 160 is to form cavity 109, as shown in Figure 11 a to Figure 11 b, wherein Figure 11 b to 11e is shown along figure
The sectional view of the line A-A of 11a, the X-direction in Figure 11 a is the length direction of 3D memory device, the width that Y-direction is 3D memory device
Spend direction.
In this step, isotropic etching can be using the wet etching or gas phase etching of selectivity.In wet etching
It is middle to use etching solution as etchant, and in the etch solution by semiconductor structure submergence.Etching is used in gas phase etching
Gas is exposed in etching gas as etchant, and by semiconductor structure.Interlayer insulating film in insulating laminate structure 160
161 and in the case of sacrificial layer 162 is made of silica and silicon nitride respectively, it can be made using phosphoric acid solution in wet etching
For etchant, C can be used in gas phase etching4F8、C4F6、CH2F2And O2One of or it is a variety of be used as etching gas.It is losing
It carves in step, etchant is full of the second through-hole 102.It is logical that the end of sacrificial layer 162 in insulating laminate structure 160 is exposed to second
In the opening in hole 102, therefore, sacrificial layer 162 touches etchant.Etchant is from the opening of the second through-hole 102 gradually to insulation
The etched inside sacrificial layer 162 of laminated construction 160.Due to the selectivity of etchant, the etching is relative to insulating laminate structure 160
In interlayer insulating film 161 remove sacrificial layer 162.
Further, using the second through-hole 102 as deposit channel, using atomic layer deposition (ALD), in cavity 104
Middle filling metal layer forms gate conductor layer 121,122,123, to form rhythmic structure of the fence 120, as shown in fig. 11c.
In this step, metal layer is for example made of tungsten.The forerunner source used in atomic layer deposition is e.g. lithium
Tungsten WF6, the reducing gas of use is, for example, silane SiH4Or diborane B2H6.In the atomic layer deposition the step of, utilization is lithium
Tungsten WF6With silane SiH4Reaction product chemisorption obtain tungsten material realize deposition process, since the second through-hole 102 also can
It is filled by metal layer, therefore, it is necessary to form photoresist mask on the surface of semiconductor structure, then carries out etch-back
(etch back) re-forms the second through-hole 102.
Further, again using the second through-hole 102 as etchant channel, removal is open adjacent with the second through-hole 102
Part of grid pole conductor layer 121,122,123, as illustrated in fig. 11d.
It in some preferred embodiments, can also be logical second again using the second through-hole 102 as ion implanting channel
Source ion is injected in the semiconductor substrate 101 of 102 bottom of hole.
In this step, for example, by using ion implantation technology, via the second through-hole 102 to semiconductor substrate 101 carry out from
Son injection forms N-type (use N type dopant, such as P, As) or p-type (using P-type dopant, such as B) in substrate 101
Doped region.The contact zone that doped region is connected as common source, for reducing the electric through post that subsequently forms and semiconductor substrate 101 it
Between contact resistance or directly as semiconductor devices for source electrode.
Further, the second insulation contacted with gate conductor layer 121,122,123 is formed in the side wall of the second through-hole 102
Layer 150, as illustrated in fig. 11e.
In this step, for example, using spin coating process (Spin On Dielectric, SOD) covering pole conductor 121,
122,123 the second through-hole 102 side wall formed second insulating layer 150.
Further, the conductive material contacted with semiconductor substrate 101 is filled in the second through-hole 102, is led to be formed
Electric channel 130, as shown in figure 12.In this step, conductive material includes tungsten or polysilicon.
Figure 13 a and Figure 13 b show effect analysis schematic diagram.Wherein, Figure 13 a is 3D memory device in the prior art
Perspective view, Figure 13 b are the top view of 3D memory device in the prior art, and the X-direction in Figure 13 a is the length of 3D memory device
Direction, Y-direction are the width direction of 3D memory device, the short transverse that Z-direction is 3D memory device.
As shown in Figure 13 a, Figure 13 b, in the prior art, is formed after rhythmic structure of the fence 120 ', needed in grid line separate slot
Middle to form the conductive channel 130 ' for running through rhythmic structure of the fence 120 ', which will pass through gate stack knot in the X direction
Structure 120 ' is divided into multiple portions, and the rhythmic structure of the fence 120 ' for extending through each part later forms channel hole 110 ', in the Y direction
On, conductive channel 130 ' is powered by substrate 101 to 4 channel holes 110 ' of two sides.In addition to this, it is also necessary to by the grid of top layer
Pole conductor separates, and top layer grid tangent line 103 ' is formed, so that storage unit is divided into multiple storage regions, in order to avoid tungsten exists
Filled in grid line separate slot it is uneven, and in order to avoid between the tungsten and gate conductor layer in grid line separate slot because insulating layer damages
It is bad to cause short circuit, it needs for grid line separate slot to be sized for very greatly, since grid line separate slot occupies the big quantity space of memory device,
It for the storage density for guaranteeing memory device, needs the very little that is sized in channel hole 110 ', therefore improves production channel hole
Technology difficulty.
In the technique for forming gate conductor layer 120 ', need to remove the sacrificial layer of its two sides via grid line separate slot, by
It is spaced apart between each grid line separate slot, excessive etching is needed to guarantee to completely remove sacrificial layer, therefore can damage and lean on
The interlayer insulating film of nearly grid line separate slot.
Since each conductive channel 130 ' formed in grid line separate slot is needed to the multiple rows of channel hole for being located at its two sides
110 ' power supplies, the channel hole 110 ' close to conductive channel 130' and the channel hole 110 ' far from conductive channel 130' are former due to distance
Cause, the voltage of acquisition are simultaneously uneven.
And 3D memory device according to an embodiment of the present invention and its manufacturing method, storage unit is separated using isolation structure
For multiple storage regions, top layer grid tangent line is eliminated, manufacturing process is simplified.
3D memory device according to an embodiment of the present invention and its manufacturing method, by being formed through rhythmic structure of the fence and with half
Multiple channel holes that conductor substrate is electrically connected, and formed be distributed in it is between multiple channel holes, through rhythmic structure of the fence and with
Multiple conducting channels that semiconductor substrate is electrically connected realize each conducting channel and pass through semiconductor substrate to surrounding channel
The purpose of hole power supply improves 3D memory device to channel hole using conducting channel instead of conductive channel in the prior art
The efficiency of power supply, each channel hole obtain unified voltage.
3D memory device according to an embodiment of the present invention and its manufacturing method, by through rhythmic structure of the fence and and semiconductor
Multiple conducting channels that substrate is electrically connected realize the purpose powered to surrounding channel hole, come relative to original conductive channel
It says, the technique for forming conducting channel is more easier, even if the tungsten or polysilicon filling in some conducting channel are uneven, causes this
Conducting channel cannot power to surrounding channel hole, and other conducting channels can also be worked normally to replace the conducting channel, and
Device will not be impacted.
3D memory device according to an embodiment of the present invention and its manufacturing method are saved due to eliminating original grid line separate slot
The space of memory device has been saved, the size in channel hole can be increased, to reduce the technology difficulty to form channel hole.
3D memory device according to an embodiment of the present invention and its manufacturing method, by the isolation for running through the rhythmic structure of the fence
Storage unit is separated into multiple storage regions by structure, further through the channel between isolation structure, by adjacent storage region phase
Even, achieved the purpose that for storage unit to be optionally combined.
3D memory device according to an embodiment of the present invention and its manufacturing method, by being arranged the second through-hole in first through hole
Between, surrounding sacrificial layer is replaced with into gate conductor layer via the second through-hole, interlayer will not be caused exhausted because of etching is excessive
The damage of edge layer.
In the above description, the technical details such as composition, the etching of each layer are not described in detail.But
It will be appreciated by those skilled in the art that can be by various technological means, come layer, the region etc. for forming required shape.In addition, being
Formation same structure, those skilled in the art can be devised by and process as described above not fully identical method.
In addition, although respectively describing each embodiment above, but it is not intended that the measure in each embodiment cannot be advantageous
Ground is used in combination.
The embodiment of the present invention is described above.But the purpose that these embodiments are merely to illustrate that, and
It is not intended to limit the scope of the invention.The scope of the present invention is limited by appended claims and its equivalent.This hair is not departed from
Bright range, those skilled in the art can make a variety of alternatives and modifications, these alternatives and modifications should all fall in of the invention
Within the scope of.
Claims (20)
1. a kind of 3D memory device, comprising:
Semiconductor substrate；
Rhythmic structure of the fence is located in the semiconductor substrate, exhausted including the multiple gate conductor layers being alternately stacked and multiple interlayers
Edge layer；
Multiple channel holes, are separately positioned in corresponding storage region, and the rhythmic structure of the fence is run through simultaneously in each channel hole
It is electrically connected with the semiconductor substrate；
Multiple isolation structures are separately positioned in corresponding area of isolation, and each isolation structure runs through the gate stack knot
Structure is to realize the isolation between multiple storage regions；And
Multiple conducting channels are distributed in the area of isolation and the storage region, and each conducting channel is through described
Rhythmic structure of the fence is simultaneously electrically connected with the semiconductor substrate, and each channel hole is at least adjacent with a conducting channel to be set
It sets, each conducting channel is used to power by the semiconductor substrate to the surrounding channel hole,
Wherein, in each area of isolation, the isolation structure at least surrounds the side wall of the corresponding conducting channel.
2. 3D memory device according to claim 1, wherein each area of isolation is in a strip shape and puts down in a second direction
Row setting,
Multiple conducting channels in each area of isolation are arranged along first direction, wherein the second direction
It is in 90 ° with the first direction.
3. 3D memory device according to claim 2, wherein multiple except each area of isolation described lead
Electric channel is arranged along the second direction.
4. 3D memory device according to claim 3, wherein the multiple channel hole is arranged in array, the channel of every row
Hole and the channel hole of adjacent rows are staggered.
5. 3D memory device according to claim 4, wherein the isolated area is arranged every the channel hole of predetermined number of lines
Domain, to form a storage region between the area of isolation described in two rows.
6. 3D memory device according to claim 5, wherein the predetermined number of lines includes 3 rows.
7. 3D memory device according to claim 5, wherein at least partly described in area of isolation in every line
Isolation structure is spaced a predetermined distance to form channel in a first direction, and the adjacent storage region is connected.
8. 3D memory device according to claim 4, wherein set along the first direction every the channel hole of predetermined columns
Set the column conducting channel.
9. 3D memory device according to claim 1, wherein be provided with one group of channel around each conducting channel
Hole, one group of channel hole are distributed in the periphery of the conducting channel with hexagon.
10. -9 any 3D memory device according to claim 1, further includes second insulating layer, the conducting channel is surrounded,
The conducting channel is separated by the second insulating layer and the multiple gate conductor layer.
11. a kind of method for manufacturing 3D memory device, comprising:
Rhythmic structure of the fence is formed on the semiconductor substrate, it is exhausted including the multiple gate conductor layers being alternately stacked and multiple interlayers
Edge layer；
Respectively in corresponding storage region, formed through the rhythmic structure of the fence be electrically connected with the semiconductor substrate it is multiple
Channel hole；
Respectively in corresponding area of isolation, multiple isolation structures are formed through the rhythmic structure of the fence, it is multiple described to realize
Isolation between storage region；And
Respectively in the corresponding storage region and the area of isolation, is formed through the rhythmic structure of the fence and partly led with described
Multiple conducting channels that body substrate is electrically connected, each channel hole are at least disposed adjacent with a conducting channel, each
The conducting channel is used to power by the semiconductor substrate to the surrounding channel hole,
Wherein, in each area of isolation, the isolation structure at least surrounds the side wall of the corresponding conducting channel.
12. according to the method for claim 11, wherein each area of isolation is in a strip shape and sets in parallel in a second direction
It sets,
Multiple conducting channels in each area of isolation are arranged along first direction, the second direction with it is described
First direction is in 90 °.
13. according to the method for claim 12, wherein multiple conductive ditches except each area of isolation
It arranges along the second direction in road.
14. according to the method for claim 13, wherein forming institute multiple the step of stating channel hole includes:
Form insulating laminate structure on the semiconductor substrate, including the multiple interlayer insulating film that is alternately stacked with it is multiple
Sacrificial layer；
In the storage region, multiple first through hole are formed through the insulating laminate structure；And
Channel layer, tunneling medium layer, charge storage layer and gate dielectric layer are filled in the first through hole to described in formation
Channel hole.
15. according to the method for claim 14, wherein the step of forming the multiple conducting channel include:
In the storage region and in the area of isolation, multiple second through-holes are formed through the insulating laminate structure；With
And
Conductive material is filled in second through-hole to forming the conducting channel,
Wherein, the multiple second through-hole is formed in same step with the multiple first through hole.
16. according to the method for claim 15, wherein the step of forming the isolation structure include:
In the area of isolation, grid line gap is formed through the insulating laminate structure；And
Fill oxide forms the isolation structure in the grid line gap.
17. according to the method for claim 16, wherein fill channel layer, tunneling medium layer, electricity in the first through hole
Before the step of lotus accumulation layer and gate dielectric layer, the step of forming the multiple channel hole further include:
The oxide is filled in the multiple first through hole；And
It removes and fills the oxide in the multiple first through hole,
Wherein, the oxide in the multiple first through hole and the oxide in the grid line gap shape in same step
At.
18. according to the method for claim 17, wherein before the step of filling conductive material in second through-hole,
The step of forming the multiple conducting channel further include:
The oxide is filled in the multiple second through-hole；And
It removes in the multiple second through-hole and fills the oxide,
Wherein, the oxide in the multiple second through-hole and the oxide in the grid line gap shape in same step
At.
19. further including in second through-hole according to the method for claim 18, before filling the conductive material
Side wall forms second insulating layer, and the second insulating layer is contacted with the gate conductor layer.
20. according to the method for claim 18, wherein the step of forming the rhythmic structure of the fence include:
After the step of filling the oxide in removing the multiple second through-hole, via the multiple second through-hole by institute
It states multiple sacrificial layers and replaces with the multiple gate conductor layer.
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| CN110600477A (en) * | 2019-08-16 | 2019-12-20 | 长江存储科技有限责任公司 | Photomask, preparation method of three-dimensional memory device and three-dimensional memory device |
| CN110739015A (en) * | 2019-09-17 | 2020-01-31 | 长江存储科技有限责任公司 | Three-dimensional memory, driving method thereof, driving device thereof, and electronic device |
| CN111211130A (en) * | 2020-01-16 | 2020-05-29 | 长江存储科技有限责任公司 | 3D memory device and method of manufacturing the same |
| CN111341777A (en) * | 2020-03-19 | 2020-06-26 | 长江存储科技有限责任公司 | Three-dimensional memory, preparation method thereof and electronic equipment |
| WO2023137829A1 (en) * | 2022-01-18 | 2023-07-27 | 长鑫存储技术有限公司 | Storage apparatus and manufacturing method and driving method therefor |
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| CN113206101A (en) | 2021-08-03 |
| CN109698201B (en) | 2021-05-04 |
| CN113206101B (en) | 2022-07-29 |
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