CN110600477A - Photomask, preparation method of three-dimensional memory device and three-dimensional memory device - Google Patents
Photomask, preparation method of three-dimensional memory device and three-dimensional memory device Download PDFInfo
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- CN110600477A CN110600477A CN201910757687.6A CN201910757687A CN110600477A CN 110600477 A CN110600477 A CN 110600477A CN 201910757687 A CN201910757687 A CN 201910757687A CN 110600477 A CN110600477 A CN 110600477A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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Abstract
The application provides a photomask, a preparation method of a three-dimensional storage device and the three-dimensional storage device, wherein the photomask is provided with a plurality of patterns which are sequentially connected, the patterns comprise a first pattern and a second pattern, the first pattern is provided with a first edge and a second edge which are oppositely arranged, the two second patterns are arranged in the middle of the first edge at intervals, and the other two second patterns and the two second patterns are correspondingly arranged on the second edge. The technical scheme of the application solves the problem that in the prior art, a conductor formed in the grid separation groove of the three-dimensional memory device is easy to contact with a conductor layer in the stacked structure to cause electric leakage.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a photomask, a preparation method of a three-dimensional memory device and the three-dimensional memory device.
Background
A three-dimensional (3D) memory is a memory device in which memory cells are three-dimensionally arranged over a substrate, and has advantages of high integration density, large storage capacity, and low power consumption, thereby being widely used in electronic products. However, in the conventional three-dimensional memory device, the conductor formed in the gate spacer is likely to contact the conductor layer in the stacked structure, which may cause leakage.
Disclosure of Invention
In view of this, embodiments of the present invention provide a photomask, which solves the problem of current leakage caused by the fact that the conductor formed in the gate spacer of the three-dimensional memory device in the prior art is likely to contact the conductor layer in the stacked structure.
The invention provides a photomask, wherein a plurality of patterns which are connected in sequence are arranged on the photomask, the patterns comprise a first pattern and a second pattern, the first pattern is provided with a first edge and a second edge which are arranged oppositely, two second patterns are arranged in the middle of the first edge at intervals, and the other two second patterns and the two second patterns are arranged on the second edge correspondingly.
Wherein, the interval between two second patterns on the same side is 1-2 times of the size of the second patterns in the length direction of the first pattern.
The distance between the second pattern correspondingly arranged on the first edge of the first pattern and the edge, away from the first pattern, of the second pattern arranged on the second edge is 2-4 times the width of the first pattern.
Wherein the first pattern has a first end and a second end opposite to each other, and a distance between the first end and the second pattern near the first end is equal to a distance between the second end and the second pattern near the second end.
And the interval between the two second patterns on the same side is 1-7 times of the distance between the second pattern close to the second end and the second end.
Wherein the pattern is opaque.
The photomask further comprises a mask base body, the first pattern and the second pattern are arranged on the mask base body, the patterns are transparent, and the mask base body is shading.
The mask base body comprises a first surface and a second surface which are arranged oppositely, and the pattern is a hollow structure which is formed on the mask base body and is communicated with the first surface and the second surface.
The photomask comprises a transparent substrate and a light shielding layer arranged on the substrate, wherein the substrate part provided with the light shielding layer forms the mask base body, and the substrate part not provided with the light shielding layer forms the pattern.
The invention also provides a preparation method of the three-dimensional memory device, which comprises the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a stacking structure and a substrate, the stacking structure comprises a stacking layer and a mask layer positioned on the stacking layer, the stacking structure is provided with a channel hole penetrating through the stacking layer and the mask layer, and a NAND string is formed in the channel hole; and
providing a first photomask, and photoetching the stacked structure from the surface of the mask layer, which is far away from the substrate, by using the first photomask to form a first grid isolation groove, wherein the first photomask is the photomask.
Wherein, after the step of forming the first gate spacer, the method comprises the following steps:
and filling a first insulating material into the first gate isolation groove.
Wherein, the first grid separating groove comprises a plurality of first sub-separating grooves which are communicated in sequence, each first sub-separating groove comprises a first part and a plurality of second parts which are respectively arranged at two ends of the first part, and after the first insulating material is filled in the separating groove, the preparation method comprises the following steps:
providing a second photomask; and
and photoetching the semiconductor structure from the surface of the mask layer, which is far away from the substrate, by using the second photomask to form second gate isolation grooves, wherein the second gate isolation grooves expose the substrate, the second gate isolation grooves comprise a plurality of second sub-isolation grooves arranged at intervals, and any two adjacent second sub-isolation grooves are spaced at the part far away from the substrate by the first insulating material filled in the first part of the first sub-isolation groove.
Wherein the stack layer comprises sacrificial layers and insulating layers which are alternately arranged, and after the step of forming the second gate separation groove, the preparation method comprises the following steps:
replacing the sacrificial layer with a conductor layer to form alternating insulator and conductor stack layers.
Wherein, after the replacing the sacrificial layer with a conductor layer to form alternating insulator and conductor stack layers, the method of making comprises:
depositing a second insulating material on the peripheral wall of the second gate spacer; and
and filling a conductive material in the second grid separation groove.
The present invention also provides a three-dimensional memory device, including:
a substrate;
a stack structure on the substrate and including a stack layer and a mask layer on the stack layer, the mask layer having a top surface facing away from the stack layer;
the first insulating part penetrates through the mask layer and extends into the stacked structure, and the first insulating part comprises a plurality of first sub-insulating parts arranged at intervals; and
the second insulating part penetrates through the stacked structure and extends into the substrate, the second insulating part comprises a plurality of second sub-insulating parts arranged at intervals, each second sub-insulating part is arranged between any two adjacent first sub-insulating parts and is connected with any two adjacent first sub-insulating parts, and a conductor is arranged in each second sub-insulating part; and wherein
The distance from any edge of the second insulating part departing from the electric conductor to the electric conductor is equal, the first sub-insulating part comprises a first straight section and first arc sections arranged at two ends of the first straight section, two opposite sides of each first arc section protrude out of two opposite sides of the first straight section, and the first arc sections at two ends of the first sub-insulating part are respectively connected with the corresponding second sub-insulating parts.
The electric conductor comprises a second straight section and second arc sections arranged at two ends of the second straight section, a second sub-insulating part is arranged between the first arc section and the second arc section, and the width of the first straight section is smaller than that of the second straight section.
The first straight section is provided with a first side edge, the first arc-shaped section is provided with a second side edge and a third side edge, the second side edge is located on the same side as the first side edge, the third side edge is back on the back of the second side edge, the first side edge is connected with the second side edge, and the shortest distance from the joint of the first side edge and the second side edge to the third side edge is greater than or equal to the thickness of the second sub-insulating part.
Wherein the distance between the joint of the first side edge and the second side edge and the conductor is 30-100 nm.
Wherein the stacked structure has a channel hole through the stacked layers and the mask layer, and a NAND string is formed in the channel hole; the stack layer comprises conducting layers and insulating layers which are alternately arranged.
According to the photomask provided by the embodiment of the application, the two second patterns are arranged at the middle part of the first edge of each first pattern at intervals, the two second patterns which are arranged opposite to the two second patterns arranged on the first edge are arranged on the second edge of each first pattern, and the three-dimensional memory device is subjected to photoetching through the photomask to form the gate isolation groove, so that the problem that a conductor formed in the gate isolation groove of the three-dimensional memory device in the prior art is easy to contact with a conductor layer in a stacked structure to cause electric leakage is solved.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a photomask according to an embodiment of the present disclosure.
FIG. 2 is a schematic diagram of another embodiment of the photomask provided in FIG. 1.
Fig. 3 is a schematic flowchart of a method for manufacturing a three-dimensional memory device according to an embodiment of the present disclosure.
Fig. 4 is a schematic cross-sectional structure of each process of the manufacturing method in fig. 3.
Fig. 5 is a schematic structural view of each process of the manufacturing method in fig. 3.
Fig. 6 is a schematic cross-sectional view of the semiconductor structure provided in fig. 5 along the a-a direction.
Fig. 7 is a schematic flow chart diagram of another embodiment of a method of fabricating the three-dimensional memory device provided in fig. 3.
Fig. 8 is a schematic cross-sectional structure of each process of the manufacturing method of fig. 7.
Fig. 9 is a schematic structural view of the second photomask of fig. 7.
Fig. 10 is a schematic structural view of each process of the manufacturing method in fig. 7.
Fig. 11 is a schematic cross-sectional view of the semiconductor structure provided in fig. 10 along the direction B-B.
Fig. 12 is a schematic cross-sectional structure of each process of the manufacturing method of fig. 7.
Fig. 13 is a schematic structural diagram of a three-dimensional memory device provided by the present application.
Fig. 14 is a schematic cross-sectional view of the three-dimensional memory device provided in fig. 13 along a direction C-C.
Detailed Description
Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it is to be understood that the invention may be practiced otherwise than as specifically described and that the invention is therefore not limited to the following embodiments.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a photomask 10 according to the present disclosure. The photomask 10 is provided with a plurality of patterns 1 which are connected in sequence, the patterns 1 comprise a first pattern 11 and a second pattern 12, the first pattern 11 is provided with a first edge 111 and a second edge 112 which are arranged oppositely, two second patterns 12 are arranged in the middle of the first edge 111 at intervals, and the other two second patterns 12 and the two second patterns 12 are arranged on the second edge 112 correspondingly.
For ease of understanding, the four second patterns in the pattern 1 are respectively denoted by 12a, 12b, 12c, 12d, wherein the second pattern 12a and the second pattern 12b are disposed at intervals on the first side 111, the second pattern 12c and the second pattern 12d are disposed at intervals on the second side 112, the second pattern 12a and the second pattern 12c are disposed opposite to each other, and the second pattern 12b and the second pattern 12d are disposed opposite to each other.
The photomask 10 provided by the embodiment of the application is used for assisting the formation of the gate isolation groove of the three-dimensional memory, two second patterns 12 are arranged at the middle part of the first edge 111 of each first pattern 11 at intervals, two second patterns 12 arranged opposite to the two second patterns 12 arranged on the first edge 111 are arranged on the second edge 112 of the first pattern 11, and the three-dimensional memory device is subjected to photoetching through the photomask 10 to form the gate isolation groove, so that the problem that a conductor formed in the gate isolation groove of the three-dimensional memory device in the prior art is easy to contact with a conductor layer in a stacked structure to cause electric leakage is solved.
The photomask 10 has various embodiments including, but not limited to, the following examples:
in one embodiment, as shown in fig. 1, the photomask 10 further includes a mask substrate 2, the pattern 1 is disposed on the mask substrate 2, the pattern 1 is transparent, that is, the first pattern 11 and the second pattern 12 are both transparent, and the mask substrate 2 is opaque. Specifically, the mask base 2 includes a first surface (not shown) and a second surface (not shown) which are oppositely disposed, and the pattern 1 is a hollow structure formed on the mask base 2 and communicating the first surface and the second surface. In the schematic diagram of the present embodiment, the sequentially connected patterns 1 provided on the photomask 10 are described by taking 3 patterns as an example, and actually, the number of the sequentially connected patterns 1 provided on the photomask 10 is set according to actual needs. Of course, in another embodiment, the photomask 10 includes a transparent substrate and a light-shielding layer provided on the substrate, and the substrate portion provided with the light-shielding layer constitutes the mask base 2, and the substrate portion not provided with the light-shielding layer constitutes the pattern 1.
In another embodiment, referring to fig. 2, fig. 2 is a schematic structural diagram of another photomask 10 provided in the present application. This embodiment is different from the previous embodiment in that the pattern 1 is opaque. Specifically, the photomask 10 includes a transparent substrate 2 'and a pattern 1 disposed on the substrate 2'. In the schematic diagram of the present embodiment, the sequentially connected patterns 1 provided on the photomask 10 are described by taking 3 patterns as an example, and actually, the number of the sequentially connected patterns 1 provided on the photomask 10 is set according to actual needs. Of course, in other embodiments, the pattern 1 is opaque and the pattern 1 directly forms the photomask 10.
Specifically, the first pattern 11 and the second pattern 12 of the pattern 1 in the photomask 10 include, but are not limited to, the following definitions.
Referring to fig. 2, the first pattern 11 has a first end 113 and a second end 114 opposite to the first end 113, and a distance between the first end 113 and a second pattern 12 near the first end 113 is equal to a distance between the second end 114 and a second pattern 12 near the second end 114. In other words, the distance from the second pattern 12a to the first end 113 is equal to the distance from the second pattern 12b to the second end 114, thereby facilitating the fabrication of the photomask 10. The spacing distance A between two second patterns 12 on the same side is 1-2 times the dimension B of the second pattern 12 in the length direction of the first pattern 11 and 1-7 times the distance C between the second pattern 12 close to the second end 114 and the second end 114, in other words, the spacing distance A between the second pattern 12a and the second pattern 12B is 1-2 times the dimension B of the second pattern 12a in the length direction of the first pattern 11, and the spacing distance A between the second pattern 12a and the second pattern 12B is 1-7 times the distance C between the second pattern 12B and the second end 114.
The distance D between the second patterns 12 correspondingly disposed on the first side 111 of the first pattern 11 and the side of the second patterns 12 disposed on the second side 112 away from the first pattern 11 is 2-4 times the width E of the first pattern 11, wherein the two second patterns 12 disposed relative to the same first pattern 11 are two second patterns 12 directly opposite to the same first pattern 11, in other words, the distance D between the sides of the second patterns 12a and the second patterns 12c away from the first pattern 11 is 2-4 times the width E of the first pattern 11.
By defining each of the first pattern 11 and the second pattern 12 of the photomask 10, the structure of the gate spacer formed by performing photolithography on the three-dimensional memory device through the photomask 10 is defined, so that the electric conductor formed in the gate spacer of the three-dimensional memory device is not easily contacted with the conductor layer in the stacked structure, thereby causing a problem of electric leakage. That is to say, by limiting the structure of the gate isolation groove, the thickness of the oxide formed between the conductor in the semiconductor structure and the conductor layer in the stacked structure is increased, the problem of electric leakage caused by contact between the conductor in the semiconductor structure and the conductor layer in the stacked structure is effectively reduced, and the performance of the three-dimensional memory device is improved.
Fig. 3 is a schematic flow chart of a method for manufacturing a three-dimensional memory device according to the present application. As shown in fig. 3, the method for fabricating the three-dimensional memory device includes S110 and S120 as follows.
The invention also provides a preparation method of the three-dimensional memory device, which comprises the following steps:
s110: providing a semiconductor structure 20, as shown in fig. 4, the semiconductor structure 20 including a stacked structure 21 and a substrate 22, the stacked structure 21 including a stacked layer 211 and a mask layer 212 on the stacked layer 211, the stacked structure 21 having a channel hole 23 penetrating through the stacked layer 211 and the mask layer 212, and a NAND string 24 formed in the channel hole 23.
Specifically, the stacked layer 211 includes sacrificial layers 2111 and insulating layers 2112 which are alternately disposed.
S120: providing a first photomask 10, referring to fig. 5, performing photolithography on the stacked structure 21 from the surface 2121 of the mask layer 212 away from the substrate 22 by using the first photomask 10 to form a first gate isolation trench 25, wherein the first photomask 10 is the photomask described above.
Specifically, as shown in fig. 2, a plurality of patterns 1 connected in sequence are disposed on the first photomask 10, where the patterns 1 include first patterns 11 and second patterns 12, each of the first patterns 11 has a first edge 111 and a second edge 112 disposed opposite to each other, two second patterns 12 are disposed at an interval in the middle of the first edge 111, and two second patterns 12 disposed opposite to the two second patterns 12 disposed on the first edge 111 are disposed on the second edge 112.
Correspondingly, referring to fig. 5 and 6, the first gate isolation groove 25 formed through the first photomask 10 includes a plurality of first sub-isolation grooves 250 sequentially connected, each of the first sub-isolation grooves 250 includes a first portion 251 and a plurality of second portions 252 respectively disposed at two ends of the first portion 251, in this embodiment, there are two second portions 252, and the second portion 252 of one first sub-isolation groove 250 is connected to the second portion 252 adjacent to the first sub-isolation groove 250 adjacent thereto. The shape of the first portions 251 of the first gate spacers 25 formed through the first photomask 10 is somewhat different from the second pattern 12 of the first photomask 10 due to the etching process. The width of the middle portion of the first portion 251 is the same as that of the second portion 252, and the width of the opposite ends of the first portion 251 is greater than that of the middle portion of the first portion 251. In this embodiment, the bottom wall of the first gate spacer 25 is located on the third sacrificial layer 2111 in the semiconductor structure 20 in the direction from the mask layer 212 to the substrate 22, and is close to the third sacrificial layer 2111. Two first gate isolation trenches 25 are formed in the semiconductor structure 20, and each first gate isolation trench 25 is exemplified by 3 first sub-trenches 250 which are sequentially connected, and actually, the number of the first gate isolation trenches 25 having the sequentially connected first sub-trenches 250 is set according to actual needs. Of course, in other embodiments, the bottom wall of the first gate spacer 25 is located on any sacrificial layer 2111 in the semiconductor structure 20 in the direction from the mask layer 212 towards the substrate 22. The number of the first gate isolation trenches 25 formed on the semiconductor structure 20 can be set according to actual needs.
The semiconductor structure 20 is subjected to photolithography through the first photomask 10 to form the first gate spacer 25, so that the conductor formed in the semiconductor structure 20 is not easily brought into contact with the conductor layer in the stacked structure 21, thereby causing a problem of leakage. That is, by limiting the structure of the first gate spacer 25 such that the widths of the two opposite ends of the first portion 251 are greater than the width of the middle portion of the first portion 251, the thickness of the insulator formed between the conductor in the semiconductor structure 20 and the conductor layer in the stacked structure 21 is increased, the problem of leakage caused by the contact between the conductor in the semiconductor structure 20 and the conductor layer in the stacked structure 21 is effectively reduced, and the performance of the three-dimensional memory device is improved.
Fig. 7 is a schematic flow chart of another method for manufacturing a three-dimensional memory device according to the present application. As shown in fig. 7, the method of fabricating the three-dimensional memory device includes the following steps S710, S720, S730, S740, and S750.
The invention also provides a preparation method of the three-dimensional memory device, which comprises the following steps:
s710: as shown in fig. 4, a semiconductor structure 20 is provided, the semiconductor structure 20 including a stacked structure 21 and a substrate 22, the stacked structure 21 including a stacked layer 211 and a mask layer 212 on the stacked layer 211, the stacked structure 21 having a channel hole 23 penetrating the stacked layer 211 and the mask layer 212, and a NAND string 24 formed in the channel hole 23.
S720: as shown in fig. 5 and 6, a first photomask 10 is provided, and the stacked structure 21 is subjected to photolithography from the surface of the mask layer 212 away from the substrate 22 using the first photomask 10 to form a first gate isolation trench 25, where the first photomask is the photomask 10.
In this embodiment, the specific operations of S710 and S720 are the same as the specific operations of S110 and S120, and are not described again here.
S730: a first insulating material is filled into the first gate spacer 25.
Specifically, as shown in fig. 8, a first insulating layer 26 is filled into the first gate isolation groove 25, in this embodiment, the first insulating material is silicon oxide, and the first insulating material is filled into the first gate isolation groove 25 by atomic layer deposition to form the first insulating layer 26. The first insulating material filled in the first gate spacer 25 is flush with a surface 2121 of the mask layer 212 facing away from the substrate 22. In other embodiments, the first insulating material may be filled in the first gate isolation trench 25 by other deposition methods, and the first insulating material may also be other insulating materials.
S740: as shown in fig. 9, 10 and 11, a second photomask 50 is provided; and photoetching the semiconductor structure 20 from the surface of the mask layer 212, which is far away from the substrate 22, by using the second photomask 50 to form second gate isolation grooves 27, wherein the second gate isolation grooves 27 expose the substrate 22, the second gate isolation grooves 27 comprise a plurality of second sub-isolation grooves 270 arranged at intervals, and any two adjacent second sub-isolation grooves 270 pass through the first insulating material interval filled in the first part 251 of the first sub-isolation groove 250 at the part, which is far away from the substrate 22, of the first sub-isolation grooves 250.
Specifically, as shown in fig. 9, a plurality of third patterns 51 are disposed on the second photomask 50 at intervals, the third patterns 51 include an intermediate section 511 and edge sections 512 connected to two ends of the intermediate section 511, and a width of the intermediate section 511 is smaller than a width of the edge sections 512. When the semiconductor structure 20 is etched from the surface of the mask layer 212 facing away from the substrate 22 by using the second photomask 50, the second photomask 50 and the first photomask 10 are located at the same position for etching the semiconductor structure 20, the middle section 511 and a part of the edge section 512 close to the middle section 511 of the third pattern 51 correspond to two second portions 252 connected to two adjacent first sub-partitioned slots 250, and the edge section 512 of the third pattern 51 far from the middle section 511 corresponds to an edge portion of the corresponding first portion 251, in other words, the third pattern 51 corresponds to the second portion 252 and a part of the first portion 251 close to the second portion 252. As shown in fig. 10 and 11, the second gate isolation trench 27 formed on the semiconductor structure 20 includes a plurality of second sub-isolation trenches 270 arranged at intervals, and any two adjacent second sub-isolation trenches 270 are spaced apart at a portion far away from the substrate 22 by the first insulating material filled in the first portion 251 of the first sub-isolation trench 250, that is, any two adjacent second sub-isolation trenches 270 are spaced apart at a portion far away from the substrate 22 by the first insulating layer 26 located in the first portion 251. The shape of both end edges of the second sub-compartment groove 270 formed through the second photo mask 30 is somewhat different from the edge section 512 of the second photo mask 30 due to the etching process. In the application, the second sub-isolation grooves 270 are arranged at intervals, so that the semiconductor structure 20 is effectively prevented from deflecting, the operation accuracy of the subsequent process of the semiconductor structure 20 is ensured, and the performance of the three-dimensional memory device is improved.
S750: depositing a second insulating material on the peripheral wall of said second gate spacer 27; a conductive material is filled in the second gate spacer 27.
In particular, as shown in fig. 11 and 12, the exposed portion of the substrate 22 surrounding the bottom of the second gate spacer 27 is doped to form a doped region 28 before depositing the second insulating material and the conductive material in said second gate spacer 27. Doped region 28 may be formed using ion implantation or diffusion of dopants into substrate 22. The dopant may include any p-type dopant (e.g., boron) or any n-type dopant (e.g., phosphorus).
The sacrificial layer is then replaced with a conductor layer 2111a to form alternating insulator and conductor stack layers 211. The sacrificial layer may be removed by a suitable etching process, such as isotropic dry etching or wet etching. The etching process may have a sufficiently high etch selectivity to the material of the sacrificial layer relative to the material of other portions of the semiconductor structure 20 to enable the etching process to have a minimal impact on other portions of the semiconductor structure 20. In some embodiments, the sacrificial layer comprises silicon nitride and the etchant of the isotropic dry etch comprises one or more of CF4, CHF3, C4F8, C4F6, and CH2F 2. The Radio Frequency (RF) power of the isotropic dry etch may be less than about 100W and the bias voltage may be less than about 10V. In some embodiments, the sacrificial layer comprises silicon nitride and the etchant of the wet etch comprises phosphoric acid. In some embodiments, the insulating layer 2112 may be removed so that there is an empty space (vacuum) between the conductor layers. The vacuum space between the conductor layers acts as an insulating layer 2112 and can help reduce parasitic capacitance. In this embodiment, the conductor layer may include a conductor material including, but not limited to, W, Co, Cu, Al, doped silicon, silicide, or any combination thereof. The conductor layer may be deposited using a suitable deposition method such as CVD, sputtering, MOCVD and/or ALD into the areas left by the removal of the sacrificial layer.
Next, a second insulating material, which may comprise an oxide or any other electrically insulating material, such as silicon oxide, is deposited on the circumferential wall of said second gate spacer 27 to form a barrier layer 29. The second insulating material is formed by atomic layer deposition on the peripheral wall of the second gate spacer 27 to form a barrier layer 29. The barrier layer 29 in the second gate spacer 27 is flush with a surface 2121 of the mask layer 212 facing away from the substrate 22. In other embodiments, the second insulating material may be formed on the peripheral wall of the second gate spacer 27 by other deposition means, such as any suitable deposition technique, such as sputtering, evaporation or Chemical Vapor Deposition (CVD), to form the barrier layer 29. The second insulating material is the same as or different from the first insulating material and the second insulating material.
A layer of conductive material 30 is then formed on the surface of said barrier layer 29 and the doped regions 28 facing the openings of the second gate spacers 27, the layer of conductive material 30 being formed of titanium, a metallic material, or another conductive material. A layer of conductive material 30 is formed by Physical Vapor Deposition (PVD) on the barrier layer 29 and on the surface of the doped region 28 facing the opening of the second gate spacer 27. Of course, in other embodiments, the conductive material layer 30 may be formed on the surface of the barrier layer 29 and the doped region 28 facing the opening of the second gate spacer 27 by other deposition methods. Finally, a third insulating material is filled in the second gate isolation trench 27 to form a third insulating pillar 31, and the third insulating material is filled in the space surrounded by the conductive material layer 30 to form the third insulating pillar 31. A portion of the third insulating pillar 31 extending through the mask layer 212 and into the stacked structure 21 is removed, and the second gate spacer 27 with the third insulating pillar 31 removed is filled with a conductive material to form a conductive body 32, wherein the conductive body 32 is flush with a surface of the mask layer 212 facing away from the substrate 22. The third insulating material may be polysilicon or other insulating material. The conductive material may include a metal such as tungsten, or any other conductive material such as Co, Cu, Al, doped silicon, silicide, or any combination thereof. Any suitable electroplating or electroless plating technique may be used to fill the third insulating column 31 and the conductive body 32.
The semiconductor structure 20 is subjected to photolithography by the first photomask 10 and the second photomask 50 to form the first gate isolation groove 25 and the second gate isolation groove 27, so that the electric conductor 32 formed in the second gate isolation groove 27 is not easily contacted with the conductor layer 2111a in the stacked structure 21 through the conductive material layer 30 to cause the problem of electric leakage, that is, by limiting the structure of the first gate isolation groove 25 so that the widths of the opposite ends of the first portion 251 are larger than the width of the middle portion of the first portion 251, the increase in the thickness of the electric conductor 32 formed in the second gate isolation groove 27 and the insulator (i.e., the first insulating layer 26 and the barrier layer 29) between the conductive material layer 30 and the conductor layer 2111a in the stacked structure 21 is ensured, the problem of electric leakage caused by the electric conductor 32 in the second gate isolation groove 27 being contacted with the conductor layer 2111a in the stacked structure 21 through the conductive material layer 30 is effectively reduced, thereby improving the performance of the three-dimensional memory device. And the second sub-isolation grooves 270 are arranged at intervals, so that the semiconductor structure 20 is effectively prevented from deflecting, the operation accuracy of the subsequent process of the semiconductor structure 20 is ensured, and the performance of the three-dimensional memory device is improved.
As shown in fig. 13 and 14, the present invention provides a three-dimensional memory device 40, where the three-dimensional memory device 40 includes a substrate 41, a stacked structure 42, a first insulating portion 43, and a second insulating portion 44. The stacked structure 42 is located on the substrate 41, the stacked structure 42 includes a stacked layer 421 and a mask layer 422 located on the stacked layer 421, and the mask layer 422 has a top surface 4221 facing away from the stacked layer 421. The first insulating portion 43 penetrates the mask layer 422 and extends into the stacked structure 42, and the first insulating portion 43 includes a plurality of first sub-insulating portions 430 arranged at intervals. The second insulating portions 44 penetrate through the stacked structure 42 and extend into the substrate 41, each second insulating portion 44 includes a plurality of second sub-insulating portions 440 arranged at intervals, each second sub-insulating portion 440 is arranged between any two adjacent first sub-insulating portions 430 and connected to any two adjacent first sub-insulating portions 430, and each second sub-insulating portion 440 is provided with an electrical conductor 45. The second insulating part 44 has equal distances from any edge of the conductive body 45 to the conductive body 45, the first sub-insulating part 430 includes a first straight section 431 and first arc-shaped sections 432 disposed at two ends of the first straight section 431, two opposite sides of the first arc-shaped section 432 protrude from two opposite sides of the first straight section 431, and the first arc-shaped sections 432 at two ends of the first sub-insulating part 430 are respectively connected with the corresponding second sub-insulating parts 440.
The first arc-shaped section 432 and the second insulating part 44 are arranged between the conductive layer 45 in the second insulating part 44 and the conductive layer 4211 in the stacked structure 42 of the three-dimensional memory device 40, so that the thickness of the insulating part formed between the conductive layer 45 in the second insulating part 44 and the conductive layer 4211 in the stacked structure 42 is ensured to be thick enough, the problem of electric leakage caused by the contact between the conductive layer 45 in the second insulating part 44 and the conductive layer 4211 in the stacked structure 42 is effectively reduced, and the performance of the three-dimensional memory device 40 is improved. And the second insulating portions 44 are arranged at intervals, so that the three-dimensional memory device 40 is effectively prevented from deflecting, the operation precision of the subsequent process of the three-dimensional memory device 40 is ensured, and the performance of the three-dimensional memory device 40 is improved.
The stacked structure 42 has a channel hole 46 penetrating the stacked layer 421 and the mask layer 422, and a NAND string 47 is formed in the channel hole 46, the stacked layer 421 including conductive layers 4211 and insulating layers 4212 alternately arranged. Each of the second sub-insulating portions 440 is disposed between any two adjacent first sub-insulating portions 430, and a portion of each of the second sub-insulating portions 440 away from the substrate 41 is connected to the first sub-insulating portion 430. The first flat section 431 has a first side 4311, the first arc-shaped section 432 has a second side 4321 located on the same side as the first side 4311 and a third side 4322 opposite to the second side 4321, the first side 4311 is connected to the second side 4321, the shortest distance from the connection point of the first side 4311 and the second side 4321 to the third side 4322 is greater than or equal to the thickness of the second sub-insulating part 440, and specifically, the distance from the connection point of the first side 4311 and the second side 4321 to the electrical conductor 45 is 30 to 100nm, so as to ensure that the thicknesses of the insulating parts (i.e., the first insulating part 430 and the second insulating part 440) formed between the electrical conductor 45 in the second insulating part 44 and the conductive layer 4211 in the stacked structure 42 are sufficiently thick, thereby effectively reducing the problem of electrical leakage caused by the contact between the electrical conductor 45 in the second insulating part 44 and the conductive layer 4211 in the stacked structure 42, thereby improving the performance of the three-dimensional memory device 40.
The three-dimensional memory device 40 further includes a conductive material layer 48 and a third insulating pillar 49, wherein the third insulating pillar 49 and the conductive body 45 are sequentially stacked and penetrate through the stacked structure 42 and extend into the substrate 41, the conductive body 45 is disposed adjacent to the mask layer 422, one end of the conductive body 45 adjacent to the mask layer 422 is flush with the top surface 4221, and the conductive material layer 48 is disposed between the third insulating pillar 49 and the conductive body 45 and the second insulating portion 44, and between the third insulating pillar 49 and the substrate 41.
The conductive body 45 includes a second straight section 451 and second arc-shaped sections 452 disposed at two ends of the second straight section 451, a second sub-insulating portion 440 is disposed between the first arc-shaped section 432 and the second arc-shaped sections 452, and the width of the first straight section 431 is smaller than that of the second straight section 451, so that the area of the first insulating portion 43 is effectively reduced, that is, the material forming the first insulating portion 43 is reduced, and the material cost is reduced.
In the present application, the first arc-shaped segment 432 and the second insulating portion 44 are disposed between the conductive portion (i.e., the conductive body 45 and the conductive material layer 48) in the second insulating portion 44 and the conductive layer 4211 in the stacked structure 42 of the three-dimensional memory device 40, so that the thickness of the insulating portion between the conductive portion in the second insulating portion 44 and the conductive layer 4211 in the stacked structure 42 is ensured to be thick enough, the problem of electric leakage caused by the contact between the conductive portion in the second insulating portion 44 and the conductive layer 4211 in the stacked structure 42 is effectively reduced, and the performance of the three-dimensional memory device 40 is further improved. And the second insulating portions 44 are arranged at intervals, so that the three-dimensional memory device 40 is effectively prevented from deflecting, the operation precision of the subsequent process of the three-dimensional memory device 40 is ensured, and the performance of the three-dimensional memory device 40 is improved. By limiting the width of the first straight section 431, the material forming the first insulating portion 43 is effectively reduced, and the material cost is reduced.
The foregoing is illustrative of the present invention and it will be appreciated by those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and are intended to be within the scope of the invention.
Claims (19)
1. The photomask is characterized in that a plurality of patterns which are connected in sequence are arranged on the photomask, the patterns comprise a first pattern and a second pattern, the first pattern is provided with a first edge and a second edge which are arranged oppositely, two second patterns are arranged in the middle of the first edge at intervals, and the other two second patterns and the two second patterns are arranged on the second edge correspondingly.
2. The photomask according to claim 1, wherein an interval between two of the second patterns on the same side is 1 to 2 times a dimension of the second patterns in a length direction of the first pattern.
3. The photomask according to claim 2, wherein a distance between the second pattern correspondingly disposed on the first side of the first pattern and a side of the second pattern disposed on the second side, which side faces away from the first pattern, is 2 to 4 times a width of the first pattern.
4. The photomask of claim 3, wherein the first pattern has opposing first and second ends, and the second pattern near the first end is equidistant from the first end as the second pattern near the second end.
5. The photomask according to claim 4, wherein the interval between two second patterns on the same side is 1 to 7 times the distance between the second pattern near the second end and the second end.
6. The photomask of any of claims 1-5, wherein the pattern is opaque.
7. The photomask of any of claims 1-5, further comprising a mask substrate on which the pattern is disposed, wherein the pattern is light transmissive and the mask substrate is light opaque.
8. The photomask of claim 7, wherein the mask substrate comprises a first surface and a second surface arranged oppositely, and the pattern is a hollow structure formed on the mask substrate and communicating the first surface and the second surface.
9. The photomask of claim 7, wherein the photomask comprises a transparent substrate and a light-shielding layer disposed on the substrate, a portion of the substrate on which the light-shielding layer is disposed constituting the mask base, and a portion of the substrate on which the light-shielding layer is not disposed constituting the pattern.
10. A preparation method of a three-dimensional memory device is characterized by comprising the following steps:
providing a semiconductor structure, wherein the semiconductor structure comprises a stacking structure and a substrate, the stacking structure comprises a stacking layer and a mask layer positioned on the stacking layer, the stacking structure is provided with a channel hole penetrating through the stacking layer and the mask layer, and a NAND string is formed in the channel hole; and
providing a first photomask, and photoetching the stacked structure from the surface of the mask layer, which is far away from the substrate, by using the first photomask to form a first gate isolation groove, wherein the first photomask is the photomask according to any one of claims 1 to 9.
11. The method of claim 10, wherein after said "forming first gate spacer" comprises:
and filling a first insulating material into the first gate isolation groove.
12. The method of claim 11, wherein the first gate isolation trench comprises a plurality of first sub-isolation trenches sequentially connected to each other, each of the first sub-isolation trenches comprises a first portion and a plurality of second portions respectively disposed at two ends of the first portion, and after the step of filling the first insulating material into the isolation trenches, the method comprises:
providing a second photomask; and
and photoetching the semiconductor structure from the surface of the mask layer, which is far away from the substrate, by using the second photomask to form second gate isolation grooves, wherein the second gate isolation grooves expose the substrate, the second gate isolation grooves comprise a plurality of second sub-isolation grooves arranged at intervals, and any two adjacent second sub-isolation grooves are spaced at the part far away from the substrate by the first insulating material filled in the first part of the first sub-isolation groove.
13. The method of manufacturing of claim 12, wherein the stacked layers comprise sacrificial layers and insulating layers alternately disposed, and after the step of forming the second gate spacer, the method comprises:
replacing the sacrificial layer with a conductor layer to form alternating insulator and conductor stack layers.
14. The method of manufacturing of claim 13, wherein after said replacing the sacrificial layer with a conductor layer to form alternating insulator and conductor stack layers, the method of manufacturing comprises:
depositing a second insulating material on the peripheral wall of the second gate spacer; and
and filling a conductive material in the second grid separation groove.
15. A three-dimensional memory device, comprising:
a substrate;
a stack structure on the substrate and including a stack layer and a mask layer on the stack layer, the mask layer having a top surface facing away from the stack layer;
the first insulating part penetrates through the mask layer and extends into the stacked structure, and the first insulating part comprises a plurality of first sub-insulating parts arranged at intervals; and
the second insulating part is embedded in the substrate from the top surface and comprises a plurality of second sub insulating parts arranged at intervals, each second sub insulating part is arranged between any two adjacent first sub insulating parts and is connected with any two adjacent first sub insulating parts, and a conductor is arranged in each second sub insulating part; and wherein
The distance from any edge of the second insulating part departing from the electric conductor to the electric conductor is equal, the first sub-insulating part comprises a first straight section and first arc sections arranged at two ends of the first straight section, two opposite sides of each first arc section protrude out of two opposite sides of the first straight section, and the first arc sections at two ends of the first sub-insulating part are respectively connected with the corresponding second sub-insulating parts.
16. The three-dimensional memory device of claim 15, wherein the conductive body comprises a second straight section and second arc-shaped sections disposed at two ends of the second straight section, a second sub-insulating portion is disposed between the first arc-shaped section and the second arc-shaped section, and a width of the first straight section is smaller than a width of the second straight section.
17. The three-dimensional memory device of claim 16, wherein the first flat segment has a first side, the first curved segment has a second side on the same side as the first side and a third side opposite the second side, the first side and the second side are connected, and a shortest distance from a connection of the first side and the second side to the third side is greater than or equal to a thickness of the second sub-insulating portion.
18. The three-dimensional memory device of claim 17, wherein a distance between a junction of the first side and the second side and the electrical conductor is 30-100 nm.
19. The three-dimensional memory device of claim 18, wherein the stacked structure has a channel hole through the stacked layers and the mask layer, and a NAND string is formed within the channel hole; the stack layer comprises conducting layers and insulating layers which are alternately arranged.
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