CN111048516B - 3D NAND memory device and method of manufacturing the same - Google Patents
3D NAND memory device and method of manufacturing the same Download PDFInfo
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- CN111048516B CN111048516B CN202010000209.3A CN202010000209A CN111048516B CN 111048516 B CN111048516 B CN 111048516B CN 202010000209 A CN202010000209 A CN 202010000209A CN 111048516 B CN111048516 B CN 111048516B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
Abstract
The invention relates to the field of semiconductor devices, and discloses a 3D NAND memory device and a manufacturing method thereof. The above 3D NAND memory device includes: a substrate; a stacked layer on the substrate, the stacked layer comprising a plurality of laterally extending gate layers and first insulating layers disposed at staggered intervals; a channel structure extending longitudinally through the stacked layers, the channel structure comprising a memory functional layer, a channel layer, and a channel fill layer; gate spacers extending longitudinally through the stacked layers, adjacent ones of the gate spacers including a plurality of the channel structures therebetween; wherein air gaps are formed in the plurality of first insulating layers. According to the 3D NAND memory device provided by the invention, the air gap is formed in the first insulating layer in the stacked layer, so that the parasitic capacitance is reduced, and the operation speed and the stability of the memory device are improved.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to a 3D NAND memory device and a manufacturing method thereof.
Background
The 3D NAND memory device is a nonvolatile memory product with low power consumption, light weight, and good performance, and is widely used in electronic products, particularly in memory applications of mobile electronic products such as digital cameras, MP3 players, mobile phones, Global Positioning Systems (GPS), high-end notebook computers, and tablet computers.
In the 3D NAND memory device structure, a manner of vertically stacking a plurality of gate layers and insulating layers in a staggered manner is adopted, a channel deep hole is formed in a stacked layer (or "stack"), a memory cell string is formed in the channel deep hole, and the gate layer in the stacked layer is used as a gate line of each layer of memory cells, thereby realizing the stacked 3D NAND memory device.
However, as the storage density of the 3D NAND memory device increases, the size of the 3D NAND memory device is smaller and smaller, and the distance between adjacent conductive layers in the device is closer and closer, so that the parasitic capacitance between the conductive layers is increased, and the capacitance not only affects the operation speed of the 3D NAND memory device, but also has a serious influence on the stability of the device.
Disclosure of Invention
To solve the above technical problems, the present invention provides a 3D NAND memory device and a method of manufacturing the same.
In one aspect, the present invention provides a 3D NAND memory device, comprising:
a substrate;
a stacked layer on the substrate, the stacked layer comprising a plurality of laterally extending gate layers and first insulating layers disposed at staggered intervals;
a channel structure extending longitudinally through the stacked layers, the channel structure comprising a memory functional layer, a channel layer, and a channel fill layer;
gate spacers extending longitudinally through the stacked layers, adjacent ones of the gate spacers including a plurality of the channel structures therebetween;
wherein air gaps are formed in the plurality of first insulating layers.
According to a preferred embodiment of the present invention, a portion of the first insulating layer adjacent to the channel deep hole includes a silicon oxynitride layer.
According to a preferred embodiment of the present invention, the lateral width of the silicon oxynitride layer is greater than 5 nm.
According to a preferred embodiment of the present invention, a second insulating layer on sidewalls of the gate spacer and a gate spacer filling layer surrounded by the second insulating layer are further formed in the gate spacer.
In another aspect, the present invention provides a method of manufacturing a 3D NAND memory device, including:
providing a substrate;
forming a stacked layer on the substrate, the stacked layer including a plurality of laterally extending interlayer insulating layers and dielectric layers arranged at staggered intervals;
forming a longitudinally extending channel recess in a first region of said stacked layers;
removing part of the interlayer insulating layer adjacent to the channel deep holes in the interlayer insulating layer so that the interlayer insulating layer is positioned between the channel deep holes to form an inner shrinkage interlayer insulating layer and a transverse vacant part;
filling dielectric material into the vacant part, and making the side face of the dielectric material be level with the side wall of the deep hole of the channel;
sequentially forming a storage function layer, a channel layer and a channel filling layer on the side wall of the channel deep hole to form a channel structure;
forming longitudinally extending gate spacers in a second region of the stack of layers, adjacent gate spacers including a plurality of the channel structures therebetween;
removing the dielectric layer by using the gate isolation groove and replacing the dielectric layer with a gate layer;
removing at least part of the retracted interlayer insulating layer;
and filling a grid isolation groove filling layer in the grid isolation groove.
According to a preferred embodiment of the present invention, the dielectric material comprises silicon oxynitride.
According to a preferred embodiment of the invention, the lateral width of the void portion is greater than 5 nm.
According to a preferred embodiment of the present invention, the step of removing at least a portion of the inter-layer insulation layer includes removing at least a portion of the inter-layer insulation layer using vaporized hydrofluoric acid to form an air gap.
According to a preferred embodiment of the present invention, the step of filling the gate spacer filling layer in the gate spacer includes:
and sequentially forming a second insulating layer and a gate separation groove filling layer surrounded by the second insulating layer on the side wall of the gate separation groove.
The invention has the beneficial effects that: according to the 3D NAND memory device provided by the invention, the air gap is formed in the first insulating layer in the stacked layer, and the parasitic capacitance between the conductive layers of the 3D NAND memory is smaller due to the smaller dielectric constant of the air, so that the operation speed and the stability of the 3D NAND memory device are improved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1a to 1e are schematic structural views in a process of forming a 3D NAND memory device according to a manufacturing method of an embodiment of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
The embodiment of the invention is used for solving the problem that the size of the existing 3D NAND memory device is continuously reduced along with the increase of the storage density, so that the parasitic capacitance is increased, and further the operation speed and the stability of the 3D NAND memory device are seriously influenced.
As shown in fig. 1a to 1e, an embodiment of the present invention provides a method of manufacturing a 3D NAND memory device, the method including the steps of: providing a substrate (not shown); forming a stacked layer 110 on the substrate, the stacked layer 110 including a plurality of laterally extending interlayer insulating layers 113 and dielectric layers 112 arranged at staggered intervals; forming a longitudinally extending channel recess (channel) 121 in a first region of said stack of layers 110; removing a part of the interlayer insulating layer 113 adjacent to the channel deep hole 121 in the interlayer insulating layer 113, so that the interlayer insulating layer 113 is between the channel deep holes 121, and forming a retracted interlayer insulating layer 113' and a transverse vacant part 1131; backfilling a dielectric material in the vacant part 1131 to form a dielectric material layer 1132, and making the side surface of the dielectric material layer 1132 be flush with the side wall of the channel deep hole 121; sequentially forming a storage function layer 122, a channel layer 123 and a channel filling layer 124 on the side wall of the channel deep hole 121 to form a channel structure 120; forming longitudinally extending Gate spacer grooves (GLS, Gate Line Slit, or "Gate slits") 130 in a second region of the stacked layer 110, wherein a plurality of the channel structures 120 are included between adjacent Gate spacer grooves 130; removing the dielectric layer 112 by using the gate isolation groove 130 and replacing the gate layer 114; removing at least a portion of the retracted interlayer insulating layer 113'; a gate spacer filling layer 132 is filled in the gate spacer 130.
Specifically, as shown in fig. 1a, the stacked layer 110 is formed on a substrate (not shown), and the stacked layer 110 includes a plurality of laterally extending interlayer insulating layers 113 and dielectric layers 112 disposed at staggered intervals. The number of stacked layers 110 is determined according to the number of memory cells required to be formed in the vertical direction, and the number of stacked layers 110 may be, for example, 8, 32, 64, or the like. The interlayer insulating layer 113 and the dielectric layer 112 may be sequentially deposited at intervals in an alternating manner by using chemical vapor deposition, atomic layer deposition, or other suitable deposition method to form the stack layer 110. Wherein the material of the interlayer insulating layer 113 may be silicon oxide (SiO)x) The material of the dielectric layer 112 may be silicon nitride (SiN)x)。
Further, the stacked layer 110 further includes a hard mask layer 111 located at the topmost layer, and the material of the hard mask layer 111 may be at least one of polysilicon, oxide, and nitride, so as to ensure that the pattern is not changed after the subsequent patterning process of the stacked layer 110.
It should be understood by those skilled in the art that the figures only show a partial structure of the 3D NAND memory device, but not limited thereto, and although not shown in the figures, the 3D NAND memory device provided by the present invention is formed On a semiconductor substrate, which may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) or a GOI (Germanium On Insulator) or the like. In other embodiments, the semiconductor substrate may also be a substrate including other element semiconductors or compound semiconductors, such as SiC, and may also be a stacked structure, such as Si/SiGe or the like. Further, in other embodiments, the semiconductor substrate may comprise a doped epitaxial layer.
In a first region of the stacked layer 110, a channel deep hole (channel) 121 is formed perpendicular to the substrate. Specifically, in an embodiment of the present invention, a patterned photoresist is formed on the first region of the stack layer 110, and then, the stack layer 110 is etched by using an etching technique, for example, RIE (reactive ion etching), to form the channel deep hole 121.
As shown in fig. 1b, a portion of the interlayer insulating layer 113 adjacent to the channel deep hole 121 in the interlayer insulating layer 113 is removed, so that the interlayer insulating layer 113 is between the channel deep holes 121, and an inter-layer insulating layer 113' and a lateral vacant portion 1131 are formed.
The above step of removing the portion of the interlayer insulating layer 113 adjacent to the deep channel hole 121 may be performed by wet etching. Since only a part of the interlayer insulating layer 113 needs to be removed, an etchant having a high selection ratio of the interlayer insulating layer 113 to the dielectric layer 112 is selected when the etchant is selected. In an embodiment of the present invention, diluted liquid hydrofluoric acid (HF) is used as the etchant, and the dilution ratio may be 200: 1 or 100: 1.
further, the lateral etching width of the vacancy portion 1131 is greater than 5nm, preferably 5 to 12nm, and the most preferred lateral etching width is 10 nm.
After the interlayer insulating layer 113 is partially etched, the structure shown in fig. 1b is obtained.
FIG. 1c shows the structure after backfilling the void 1131.
Specifically, a dielectric material is filled into the vacant part 1131, a dielectric material layer 1132 is formed, and the side surface of the dielectric material layer 1132 is aligned with the side wall of the channel deep hole 121.
In an embodiment of the present invention, the dielectric material may be silicon oxynitride (SiON). The vacant portions 1131 are backfilled with silicon oxynitride, so that damage to the backfilled portions when the dielectric layer 112 is replaced with the gate layer 114 in a subsequent process is avoided.
Further, the side face of the silicon oxynitride layer 1132 formed by backfilling the silicon oxynitride is aligned with the side wall of the channel deep hole 121, so that the gap 1131 is blocked, and the channel structure 120 is prevented from being damaged when at least part of the retracted interlayer insulating layer 113' is subsequently removed.
After the dielectric material layer 1132 is formed, the hard mask layer 111 and the channel deep hole 121 are acid-washed. In one embodiment of the present invention, high temperature phosphoric acid (H) is used at a temperature greater than 150 deg.C3PO4) The surface of the hard mask layer 111, as well as the sidewalls and bottom of the channel recess 121, are acid cleaned to remove excess dielectric material.
Fig. 1d shows a schematic structure diagram after forming the channel structure 120 via the channel deep hole 121, forming the gate spacer 130 in the second region of the stacked layer 110, and replacing the dielectric layer 112 with a gate layer 114.
Specifically, a memory function layer 122, a channel layer 123 and a channel filling layer 124 are sequentially formed on the sidewall of the channel deep hole 121.
In an embodiment of the invention, the storage function layer 122 is a charge trap type storage structure, and specifically, the storage function layer 122 is an ONO (Oxide-SiN-Oxide) structure, and includes a charge blocking layer 1221, a charge storage layer 1222, and a tunneling layer 1223. The charge blocking layer 1221, the tunneling layer 1223, and the channel filling layer 124 may be made of silicon oxide (SiO)x) Said electricityThe material of the charge storage layer 1222 may be silicon nitride (SiN)x) The material of the channel layer 123 may be polysilicon.
Further, the memory function layer 122 is only one embodiment of the present invention, and in other embodiments, the memory function layer may be a floating gate type memory structure or any other known structure.
In the above steps, the storage function layer 122, the channel layer 123 and the channel filling layer 124 may be deposited by using a chemical vapor deposition or atomic layer deposition method.
After forming the channel structures 120, the gate spacer 130 extending in the longitudinal direction is formed in the second region of the stacked layer 110 by patterning, wherein a plurality of channel structures 120 are included between adjacent gate spacers 130. The dielectric layer 112 is removed using the gate spacer 130 and replaced with the gate layer 114. Specifically, after the dielectric layer 112 is exposed through the gate isolation trench 130, the dielectric layer 112 is wet etched through the gate isolation trench 130, so as to remove the dielectric layer 112, so as to form a groove structure (not shown), and the groove structure is filled with a conductive material to form the gate layer 114.
The conductive material of the gate layer 114 may include a metal, for example, may be tungsten (W); it may also comprise polysilicon or a metal silicide material, for example a metal silicide material may be provided as a silicide material comprising a metal selected from tungsten (W) and titanium (Ti).
Fig. 1e shows the structure after at least a portion of the inter-layer insulation layer 113' is removed to form air gaps 1133(air gaps), and the gate trench filling layer 132 is filled in the gate trenches 130.
Specifically, removing at least a portion of the inter-layer insulating layer 113 'includes removing at least a portion of the inter-layer insulating layer 113' using vaporized hydrofluoric acid to form an air gap. In an embodiment of the present invention, the adopted hydrofluoric acid is diluted hydrofluoric acid, and the dilution ratio may be 200: 1 or 100: 1.
further, when the interlayer insulating layer 113 ' is removed to form the air gap 1133, a portion of the interlayer insulating layer 113 ' may remain, and thus, the finally formed first insulating layer 113 ″ may include a silicon oxynitride layer, i.e., the dielectric material layer 1132, the air gap 1133, and the remaining interlayer insulating layer 113 '.
Due to the fact that the dielectric constant of air is small, the air gap 1133 is formed in the first insulating layer 113 ", so that parasitic capacitance between the conductive layers of the 3D NAND memory provided by the invention is small, and therefore the operation speed and stability of the 3D NAND memory device are improved.
Filling a gate spacer filling layer 132 in the gate spacer 130, including:
a second insulating layer 131 and a gate spacer filling layer 132 surrounded by the second insulating layer 131 are sequentially formed on sidewalls of the gate spacer 130.
Specifically, in an embodiment of the present invention, the second insulating layer 131 and the gate spacer filling layer 132 are sequentially formed on the sidewalls of the gate spacer 130 by a Plasma Enhanced Chemical Vapor Deposition (PECVD). Wherein the material of the gate spacer filling layer 132 includes polysilicon and tungsten, and the material of the second insulating layer 131 may be silicon oxide (SiO)x)。
Yet another embodiment of the present invention also provides a 3D NAND memory device manufactured by the above method, referring to fig. 1e, the memory device comprising a substrate (not shown in the figure); a stack layer 110 on the substrate, the stack layer 110 comprising a plurality of laterally extending gate layers 114 and first insulating layers 113 "arranged at staggered intervals; a channel structure 120 extending longitudinally through the stacked layers 110, the channel structure 120 including a memory functional layer 122, a channel layer 123, and a channel fill layer 124; gate spacers 130 extending longitudinally through the stack 110, adjacent gate spacers 130 including a plurality of the channel structures 120 therebetween; wherein air gaps 1133 are formed in the plurality of first insulating layers 113 ″.
Further, the stack layer 110 further includes a hard mask layer 111 at the topmost layer, and the material of the hard mask layer 111 may be at least one of polysilicon, oxide and nitride, so as to ensure that the channel structure 120 and other patterns of the 3D NAND memory device are not changed and maintain the stability of the device structure.
In the 3D NAND memory device provided in the embodiment of the present invention, a portion of the first insulating layer 113 ″ adjacent to the channel deep hole 121 includes a silicon oxynitride layer 1132, and a lateral width of the silicon oxynitride layer 1132 is greater than 5nm, preferably, a lateral width of the silicon oxynitride layer ranges from 5nm to 12nm, and more preferably, a lateral width of the silicon oxynitride layer is 10 nm.
In the 3D NAND memory device provided in the embodiment of the present invention, the storage function layer 122 is a charge trap type storage structure, and specifically, the storage function layer 122 is an ONO (Oxide-SiN-Oxide) structure, and includes a charge blocking layer 1221, a charge storage layer 1222, and a tunneling layer 1223. The charge blocking layer 1221, the tunneling layer 1223, and the channel filling layer 124 may be made of silicon oxide (SiOx), the charge storage layer 1222 may be made of silicon nitride (SiNx), and the channel layer 123 may be made of polysilicon.
Further, the 3D NAND memory device provided by the embodiment of the present invention is merely exemplified herein, and in other embodiments, the memory function layer 122 may also be a floating gate type memory structure or any other known structure.
In the 3D NAND memory device according to the embodiment of the present invention, a second insulating layer 131 on sidewalls of the gate spacer 130 and a gate spacer filling layer 132 surrounded by the second insulating layer 131 are further formed in the gate spacer 130.
The material of the gate spacer filling layer 132 includes polysilicon and tungsten, and the material of the second insulating layer 131 may be silicon oxide (SiOx).
Further, the gate spacer filling layer 132 includes a half of polysilicon and a half of tungsten, which reduces the formation of voids and reduces the resistance of the gate spacer filling layer 132 while increasing the filling performance of the gate spacer filling layer 132.
The gate separation groove 130 divides the 3D NAND memory device into a plurality of memory blocks (blocks), and the second insulating layer 131 formed in the gate separation groove 130 realizes electrical isolation between the memory blocks, so that interference between the memory blocks can be effectively reduced, and the memory device has better working performance and higher use stability.
According to the above embodiment: according to the 3D NAND memory device and the manufacturing method thereof provided by the invention, the air gap 1133 is formed in the first insulating layer 113 ″ in the stack layer 110, and the parasitic capacitance between the conductive layers of the 3D NAND memory is smaller due to the smaller dielectric constant of the air, so that the operation speed and the stability of the 3D NAND memory device are improved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (9)
1. A 3D NAND memory device, comprising:
a substrate;
a stacked layer on the substrate, the stacked layer comprising a plurality of laterally extending gate layers and first insulating layers disposed at staggered intervals;
a channel structure extending longitudinally through the stacked layers, the channel structure comprising a memory functional layer, a channel layer, and a channel fill layer;
gate spacers extending longitudinally through the stacked layers, adjacent ones of the gate spacers including a plurality of the channel structures therebetween;
wherein the first insulating layer comprises a plurality of layers of dielectric material surrounding the channel structure, and air gaps between the layers of dielectric material and the gate spacer.
2. The 3D NAND memory device of claim 1 wherein the portion of the first insulating layer adjacent to the channel deep hole comprises a silicon oxynitride layer.
3. The 3D NAND memory device of claim 2 wherein the lateral width of the silicon oxynitride layer is greater than 5 nm.
4. The 3D NAND memory device of claim 1 wherein a second insulating layer on sidewalls of the gate spacer and a gate spacer filling layer surrounded by the second insulating layer are further formed within the gate spacer.
5. A method of manufacturing a 3D NAND memory device, comprising:
providing a substrate;
forming a stacked layer on the substrate, the stacked layer including a plurality of laterally extending interlayer insulating layers and dielectric layers arranged at staggered intervals;
forming a longitudinally extending channel recess in a first region of said stacked layers;
removing part of the interlayer insulating layer adjacent to the channel deep holes in the interlayer insulating layer so that the interlayer insulating layer is positioned between the channel deep holes to form an inner shrinkage interlayer insulating layer and a transverse vacant part;
filling dielectric material into the vacant part, and making the side face of the dielectric material be level with the side wall of the deep hole of the channel;
sequentially forming a storage function layer, a channel layer and a channel filling layer on the side wall of the channel deep hole to form a channel structure;
forming longitudinally extending gate spacers in a second region of the stack of layers, adjacent gate spacers including a plurality of the channel structures therebetween;
removing the dielectric layer by using the gate isolation groove and replacing the dielectric layer with a gate layer;
removing at least part of the retracted interlayer insulating layer;
and filling a grid isolation groove filling layer in the grid isolation groove.
6. The method of manufacturing a 3D NAND memory device of claim 5 wherein the dielectric material comprises silicon oxynitride.
7. The method of manufacturing a 3D NAND memory device in accordance with claim 5, wherein the lateral width of the vacant part is larger than 5 nm.
8. The method of manufacturing a 3D NAND memory device of claim 5 wherein the step of removing at least a portion of the inter-layer insulating layer includes removing at least a portion of the inter-layer insulating layer with vaporized hydrofluoric acid to form an air gap.
9. The method of manufacturing a 3D NAND memory device of claim 5 wherein the step of filling the gate spacer filling layer in the gate spacer includes:
and sequentially forming a second insulating layer and a gate separation groove filling layer surrounded by the second insulating layer on the side wall of the gate separation groove.
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