CN110289265B

CN110289265B - Method for forming 3D NAND memory

Info

Publication number: CN110289265B
Application number: CN201910575102.9A
Authority: CN
Inventors: 王香凝; 耿静静; 王攀; 张慧; 刘新鑫; 吴佳佳; 肖梦
Original assignee: Yangtze Memory Technologies Co Ltd
Current assignee: Yangtze Memory Technologies Co Ltd
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2020-04-10
Anticipated expiration: 2039-06-28
Also published as: CN110289265A

Abstract

After the stacked structure is etched and a plurality of grid separation grooves penetrating through the stacked structure are formed, a filling layer is formed in the grid separation grooves and fills the grid separation grooves; after the filling layer is formed, etching the stacked structures on two sides of the grid separation groove to form a plurality of channel through holes penetrating through the stacked structures; forming a storage structure in the trench via; after the storage structure is formed, removing the filling layer to expose the grid isolation groove; removing the sacrificial layer, and correspondingly forming a control gate at the position where the sacrificial layer is removed; forming an array common source in the gate spacer. In the invention, the grid separation groove forming step is formed before the step of forming the channel through hole and the storage structure positioned in the channel through hole, so that the grid separation groove cannot incline, and the grid separation groove and the channel through hole are prevented from being short-circuited.

Description

Method for forming 3D NAND memory

Technical Field

The invention relates to the field of semiconductor manufacturing, in particular to a method for a 3D NAND memory.

Background

The NAND flash memory is a nonvolatile memory product with low power consumption, light weight and good performance, and is widely applied to electronic products. At present, NAND flash memories with a planar structure are approaching the limit of practical expansion, and in order to further increase the storage capacity and reduce the storage cost per bit, 3D NAND memories with a 3D structure are proposed.

The formation process of existing 3D NAND memories generally includes: forming a stacked structure in which isolation layers and sacrificial layers are alternately stacked on a substrate; etching the stacked structure to form a channel through hole in the stacked structure, etching the substrate at the bottom of the channel through hole after the channel through hole is formed, and forming a groove in the substrate; forming an Epitaxial silicon layer, also commonly referred to as SEG, in the recess at the bottom of the trench via by Selective Epitaxial Growth (Selective Epitaxial Growth); forming a charge storage layer and a channel layer in the channel through hole, wherein the channel layer is connected with the epitaxial silicon layer; and removing the sacrificial layer, and forming a control gate or a word line at the position where the sacrificial layer is removed.

The conventional memory generally includes a plurality of memory blocks (blocks), and the memory blocks are generally separated by Gate Line Slots (GLS) penetrating through the stacked structure in a vertical direction, but in the manufacturing process of the conventional 3D NAND memory, the Gate slots in a partial region are easily inclined, which results in a short circuit between the Gate slots and the channel via.

Disclosure of Invention

The technical problem to be solved by the invention is how to prevent the gate separation groove from inclining, thereby preventing short circuit between the gate separation groove and the channel through hole.

The invention provides a method for forming a 3D NAND memory, which comprises the following steps:

providing a semiconductor substrate, wherein a stacked structure in which sacrificial layers and isolation layers are alternately stacked is formed on the semiconductor substrate;

etching the stacked structure to form a plurality of grid isolation grooves penetrating through the stacked structure;

forming a filling layer in the grid isolation groove, wherein the filling layer fills the grid isolation groove;

after the filling layer is formed, etching the stacked structures on two sides of the grid separation groove to form a plurality of channel through holes penetrating through the stacked structures;

forming a storage structure in the trench via;

after the storage structure is formed, removing the filling layer to expose the grid isolation groove;

removing the sacrificial layer, and correspondingly forming a control gate at the position where the sacrificial layer is removed;

forming an array common source in the gate spacer.

Optionally, the stacked structure includes a core region and a step region located on one side of the core region, the gate spacer traverses the core region and the step region, and the channel via is located in the step region.

Optionally, after the gate separation groove and the filling layer are formed, a dummy channel through hole is formed in the step region, and the dummy channel through hole is located in the step regions on two sides of the gate separation groove; a dummy channel structure is formed in the dummy channel via.

Optionally, at a boundary between the step region and the core region, the densities of the dummy channel structures and the dummy channel through holes in the step region are less than the densities of the channel through holes and the storage structures in the core region.

Optionally, the material of the filling layer is the same as that of the sacrificial layer.

Optionally, the material of the filling layer is different from that of the isolation layer.

Optionally, after forming the storage structure, forming a capping layer on the stacked structure; forming an opening in the covering layer to expose the surface of the filling layer; and removing the filling layer along the opening.

Optionally, the opening has an outwardly inclined sidewall, and a size of a bottom of the opening is equal to or greater than a size of the gate spacer.

Optionally, the memory structure includes a charge storage layer on a sidewall surface of the channel via and a channel layer on a sidewall surface of the charge storage layer.

Optionally, the charge storage layer includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.

Optionally, after removing the filling layer, the sacrificial layer in the stacked structure is removed along the gate spacer.

Optionally, after the control gate is formed, an array common source is formed in the gate isolation trench.

Compared with the prior art, the technical scheme of the invention has the following advantages:

according to the forming method of the 3D NAND memory, after the stacked structure is etched to form the plurality of grid isolation grooves penetrating through the stacked structure, the filling layer is formed in the grid isolation grooves and is filled in the grid isolation grooves; after the filling layer is formed, etching the stacked structures on two sides of the grid separation groove to form a plurality of channel through holes penetrating through the stacked structures; forming a storage structure in the trench via; after the storage structure is formed, removing the filling layer to expose the grid isolation groove; removing the sacrificial layer, and correspondingly forming a control gate at the position where the sacrificial layer is removed; forming an array common source in the gate spacer. In the invention, the step of forming the grid separation groove is formed before the step of forming the channel through hole and the storage structure positioned in the channel through hole, so that when the grid separation groove is formed, the stress in each film layer in the stacked structure is consistent, namely the grid separation groove is not influenced by the difference of the film layer stress caused by the difference of the pattern density at different positions in the stacked structure, and a certain part of the grid separation groove is not inclined, thereby preventing the grid separation groove from being short-circuited with the channel through hole.

Further, the stacked structure comprises a core region and a step region located on one side of the core region, the gate separation groove traverses the core region and the step region, the channel through hole is located in the step region, the channel through hole and the storage structure are formed after the gate separation groove and the filling layer are formed, a pseudo channel through hole is formed in the step region after the gate separation groove and the filling layer are formed, and the pseudo channel through hole is located in the step region on two sides of the gate separation groove; a dummy channel structure is formed in the dummy channel via. Since the gate spacer forming step is formed before the step of forming the channel via and the memory structure in the channel via in the core region and the step of forming the dummy channel via and the dummy channel structure in the dummy channel via in the step region, stress in the film layer on both sides or in the vicinity of the boundary between the core region and the step region is uniform when the gate spacer is formed, that is, the gate spacer is not affected by a difference in film layer stress caused by a difference in pattern density on both sides of the boundary between the core region and the step region (density of the channel via and the memory structure in the core region on both sides or in the vicinity of the interface and density of the dummy channel via and the dummy channel structure in the step region on both sides or in the vicinity of the interface), so that a portion of the gate spacer formed at the boundary between the core region and the step region is not inclined, thereby preventing the gate spacer adjacent the interface from shorting to the channel via.

Furthermore, the material of the filling layer is the same as that of the sacrificial layer, so that the filling layer and the sacrificial layer can be removed in the same step through a wet etching process, and the process steps are saved.

Furthermore, the opening formed in the covering layer is provided with an outward inclined side wall, and the size of the bottom of the opening is equal to or larger than that of the grid spacer groove, so that on one hand, the filling layer on the upper part of the grid spacer groove can be completely removed; on the other hand, when the position of the sacrificial layer is subsequently removed to form the control gate and the array common source is formed in the gate separation groove, the material layer is prevented from closing the opening of the gate separation groove in advance, and the control gate and the array common source cannot be filled.

Drawings

FIGS. 1-14 are schematic structural diagrams illustrating a 3D NAND formation process according to a first embodiment of the present invention;

FIGS. 15-33 are schematic structural diagrams illustrating a 3D NAND formation process in accordance with a second embodiment of the present invention;

FIGS. 34-36 are schematic structural diagrams illustrating a 3D NAND formation process according to a third embodiment of the present invention.

Detailed Description

As mentioned in the background, in the conventional 3D NAND memory manufacturing process, the gate spacer is easily inclined in a partial region, which results in a short circuit between the gate spacer and the channel via.

Research shows that the inclined area of the conventional grid separation groove is the boundary of a core area and a step area, the core area is an area for forming a channel through hole, and the step area is an area for forming a plug connected with a control grid and an area for forming a pseudo channel through hole.

Further research shows that in the manufacturing process of a 3D NAND memory, a stacked structure with alternately stacked sacrificial layers and isolation layers needs to be provided, wherein the stacked structure comprises a core area and a step area; forming a plurality of trench vias in the core region; forming a plurality of pseudo channel through holes in the step area; forming a storage structure in the trench via; forming a dummy channel structure in the dummy channel via; after forming the pseudo channel structure and the storage structure, etching the stacked structure to form a grid separation groove penetrating through the stacked structure, wherein the grid separation groove transversely penetrates through the core region and the step region; after forming the grid isolation groove, removing the sacrificial layer, and forming a control grid at the position where the sacrificial layer is removed; an array common source is formed in the gate spacer. When the gate isolation groove is formed, because the density of the pseudo channel through holes and the pseudo channel structures at the junction of the step region and the core region is greatly different from that of the channel through holes and the storage structures (the density of the pseudo channel through holes and the pseudo channel structures in the step region near the junction of the step region and the core region is smaller or far smaller than that of the channel through holes and the storage structures in the core region near the junction), so that there is a large difference in the stress of the films in the stacked structure at or near the two sides of the intersection of the step region and the core region, therefore, when the gate spacer is formed by etching the stacked structure at the boundary between the stepped region and the core region, the sidewall of the gate spacer at the boundary between the stepped region and the core region is easily inclined under the influence of the stress difference at the two sides of the boundary, when the condition is serious, the inclined grid separation groove exposes the channel through hole near the junction, so that the grid separation groove and the channel through hole are short-circuited.

The forming method of the 3D NAND memory comprises the steps of etching the stacked structure to form a plurality of grid isolation grooves penetrating through the stacked structure, and forming a filling layer in the grid isolation grooves, wherein the filling layer fills the grid isolation grooves; after the filling layer is formed, etching the stacked structures on two sides of the grid separation groove to form a plurality of channel through holes penetrating through the stacked structures; forming a storage structure in the trench via; after the storage structure is formed, removing the filling layer to expose the grid isolation groove; removing the sacrificial layer, and correspondingly forming a control gate at the position where the sacrificial layer is removed; forming an array common source in the gate spacer. In the invention, the step of forming the grid separation groove is formed before the step of forming the channel through hole and the storage structure positioned in the channel through hole, so that when the grid separation groove is formed, the stress in each film layer in the stacked structure is consistent, namely the grid separation groove is not influenced by the difference of the film layer stress caused by the difference of the pattern density at different positions in the stacked structure, and a certain part of the grid separation groove is not inclined, thereby preventing the grid separation groove from being short-circuited with the channel through hole.

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In describing the embodiments of the present invention in detail, the drawings are not to be considered as being enlarged partially in accordance with the general scale, and the drawings are only examples, which should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.

Fig. 1-14 are schematic structural diagrams illustrating a 3D NAND formation process according to a first embodiment of the invention.

Referring to fig. 1 and 2, fig. 2 is a schematic cross-sectional structure view along a direction of a cutting line CD of fig. 1, and a semiconductor substrate 100 is provided, and a stacked structure 111 in which a sacrificial layer 103 and an isolation layer 104 are alternately stacked is formed on the semiconductor substrate 100.

The material of the semiconductor substrate 100 may be single crystal silicon (Si), single crystal germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); or silicon-on-insulator (SOI), germanium-on-insulator (GOI); or may be other materials such as group iii-v compounds such as gallium arsenide. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon (Si).

The stacked structure 111 includes several sacrificial layers 103 and isolation layers 104 stacked alternately, the sacrificial layers 103 are subsequently removed to form a cavity, and then a control gate or a word line is formed at a position where the sacrificial layers 103 are removed. The isolation layer 104 is used for electrical isolation between control gates of different layers, and between control gates and other devices (conductive contacts, trench vias, etc.).

The sacrificial layer 103 and the isolation layer 104 are alternately stacked, that is: after forming a layer of sacrificial layer 103, a layer of isolation layer 104 is formed on the surface of sacrificial layer 103, and then the steps of forming sacrificial layer 103 and isolation layer 104 on sacrificial layer 103 are sequentially performed cyclically. In this embodiment, the bottom layer of the stacked structure 111 is a sacrificial layer 103, and the top layer is an isolation layer 104.

The number of layers of the stacked structure 111 (the number of layers of the dual-layer stacked structure of the sacrificial layer 103 and the isolation layer 104 in the stacked structure 111) is determined according to the number of memory cells required to be formed in the vertical direction, the number of layers of the stacked structure 111 may be 8, 32, 64, or the like, and the greater the number of layers of the stacked structure 111, the higher the integration level is.

The sacrificial layer 103 and the isolation layer 104 are made of different materials, and when the sacrificial layer 103 is removed subsequently, the sacrificial layer 103 has a high etching selectivity relative to the isolation layer 104, so that when the sacrificial layer 103 is removed, the etching amount of the isolation layer 104 is small or negligible, and the integrity of the isolation layer 104 is ensured.

The isolation layer 104 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, and the sacrificial layer 103 may be made of one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, amorphous silicon, amorphous carbon, and polysilicon. In this embodiment, the isolation layer 104 is made of silicon oxide, the sacrificial layer 103 is made of silicon nitride, and the isolation layer 104 and the sacrificial layer 103 are formed by a chemical vapor deposition process.

In this embodiment, a topmost sacrificial layer in the stacked structure 111 is used as the top selection gate sacrificial layer 106, the top selection gate sacrificial layer 106 is subsequently removed, and a Top Selection Gate (TSG) is formed at a position where the top selection gate sacrificial layer 106 is removed. Taking the bottom sacrificial layer in the stacked structure 111 as the bottom selection gate sacrificial layer 105, subsequently removing the bottom selection gate sacrificial layer 105, and forming a Bottom Selection Gate (BSG) at the position where the bottom selection gate sacrificial layer 105 is removed.

In an embodiment, please refer to fig. 1 and fig. 3, fig. 3 is a schematic cross-sectional structure diagram of fig. 1 along a cutting line AB, the stacked structure 111 includes a core region 11 and a step region 12 at one side of the core region 11, the core region 11 is used for forming a memory array (including a trench via and a memory structure in the trench via) of a 3DNAND memory, the step region 12 is used for forming steps and a metal plug connected to each step, and a dummy trench via in the step region and a dummy trench structure in the dummy trench via, referring to fig. 3, a plurality of steps 107 are formed in the step region 12 of the stacked structure 111, each step 107 includes a sacrificial layer 103 and an isolation layer 104 on the sacrificial layer 103, and after removing the sacrificial layer, a control gate is formed at a position where the sacrificial layer is removed, and a corresponding step region formed by a plurality of control gate layers in the step region 12 (each step region includes a control gate and a control gate located at a corresponding position of the control gate and a corresponding step region includes a control The upper isolation layer).

The stacked structure may further include a plurality of gate spacer regions 22, each gate spacer region 22 crossing the core region 11 and the step region 12.

Referring to fig. 4 and 5, fig. 5 is a schematic cross-sectional view along the direction of the cutting line CD in fig. 4, and the stacked structure 111 is etched to form a plurality of gate spacers 107 penetrating through the stacked structure 111.

In this embodiment, the gate isolation trench 107 is formed in the gate isolation trench region 22 (refer to fig. 4), and the gate isolation trench 107 traverses the core region 11 and the step region 12.

The stack structure 111 may be etched using an anisotropic dry etching process, such as a plasma etching process.

In the present application, since the gate spacer 107 forming step is formed before the step of forming the channel via and the memory structure located in the channel via in the core region 11 and the step of forming the dummy channel via and the dummy channel structure located in the dummy channel via in the step region 12, when the gate spacer 107 is formed, the stress in the film layer on both sides or in the vicinity of the boundary between the core region 11 and the step region 12 is uniform, that is, the gate spacer 107 is not affected by the difference in the film layer stress caused by the difference in the pattern density on both sides of the boundary between the core region 11 and the step region 12 (the density of the channel via and the memory structure located in the channel via in the core region 11 on both sides or in the vicinity of the interface and the density of the dummy channel via and the dummy channel structure located in the dummy channel via in the step region 12 on both sides or in the vicinity of the interface), and thus the portion of the gate spacer 107 formed at the boundary between the core region 11 and the step region 12 is not inclined, thereby preventing the gate spacer 107 near the interface from shorting to the channel via.

Referring to fig. 6, fig. 6 is performed on the basis of fig. 5, and a filling layer 108 is formed in the gate isolation trench, and the filling layer 108 fills the gate isolation trench.

The filling layer 108 serves as a sacrificial layer to facilitate subsequent processes.

In this embodiment, the material of the filling layer 108 is the same as that of the sacrificial layer 103, and specifically, the material of the filling layer 108 is silicon nitride. Therefore, the subsequent filling layer 108 and the sacrificial layer 103 can be removed in the same step through a wet etching process, and the process steps are saved.

In other embodiments, the filling layer 108 may be made of other materials, and it is only necessary that the material of the filling layer 108 is different from the material of the isolation layer 104, so that when the filling layer 108 is removed, the isolation layer 104 is not erroneously etched or the amount of etching of the isolation layer 104 is very small or negligible. The material of the filling layer 107 may be polysilicon or amorphous carbon.

In one embodiment, the forming process of the filling layer 108 includes: a layer of filling material is formed in the gate spacer 107 (see fig. 5) and on the surface of the top isolation layer 104, and the layer of filling material can be formed by Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Thermal chemical vapor deposition (Thermal CVD), High Density Plasma Chemical Vapor Deposition (HDPCVD). The filling material layer higher than the surface of the top isolation layer 104 is not required to be removed in this embodiment, and is just used as a hard mask material required in the subsequent forming process of the trench hole storage structure, and the filling material layer higher than the surface of the top isolation layer 104 is consumed in the forming process of the trench hole storage structure.

Referring to fig. 7 and 8, fig. 8 is a schematic cross-sectional view along the direction of the cutting line CD in fig. 7, after forming the filling layer 108, etching the stacked structures 111 on both sides of the gate spacer to form a plurality of trench vias penetrating through the stacked structures 111; a memory structure 119 is formed in the trench via.

In this embodiment, the trench via and the memory structure 119 are formed in the stacked structure 111 of the core region 11.

The memory structure 119 includes a charge storage layer 118 on a sidewall surface of the channel via and a channel layer 117 on a sidewall surface of the charge storage layer 118.

In one embodiment, the charge storage layer 118 includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer; the channel layer 117 fills the remaining channel vias. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The charge trapping layer may comprise silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof, and the channel layer 117 material may be polysilicon doped with N-type impurity ions, such as phosphorus ions. In a specific embodiment, the charge storage layer 118 may be a composite layer of silicon oxide/silicon oxynitride (or silicon nitride)/silicon oxide (ONO).

In one embodiment, the formation of the memory structure 119 includes: forming a charge storage layer on the sidewall and bottom of the trench hole, the charge storage layer 118 including a blocking layer on the sidewall and bottom surfaces of the trench via, a charge trapping layer on the sidewall surface of the blocking layer, and a tunneling layer on the sidewall surface of the charge trapping layer; forming a first channel layer on the charge storage layer; etching to remove the first channel layer and the charge storage layer on the bottom of the channel hole, and forming an opening exposing the surface of the epitaxial semiconductor layer 116; a second channel layer is formed in the opening and on the surface of the first channel layer, the second channel layer and the first channel layer constituting a channel layer 117.

In one embodiment, before forming the memory structure 119 in the trench via, the semiconductor substrate 100 exposed at the bottom of the trench via is etched, and a groove is formed in the semiconductor substrate 100; forming a first semiconductor epitaxial layer 116 in the groove and the partial channel through hole, wherein the top surface of the first semiconductor epitaxial layer 116 is higher than the top surface of the bottom selection gate sacrificial layer 105, and the material of the first semiconductor epitaxial layer 116 can be silicon, germanium or silicon germanium; forming a memory structure 119 in the trench via on the first semiconductor epitaxial layer 116; etching back to remove a part of the thickness of the memory structure 119, so that the top surface of the remaining memory structure 119 is higher than the top surface of the top-layer selection gate sacrificial layer 106 and lower than the top surface of the topmost isolation layer 104; a second semiconductor layer 120 is formed in the trench via on the remaining memory structure 119, and the material of the second semiconductor layer 120 may be silicon, germanium, or silicon germanium.

In an embodiment, referring to fig. 7 and 9, fig. 9 is a schematic cross-sectional structure view along the cutting line AB of fig. 7, further including: forming a plurality of dummy channel through holes vertically penetrating through the stacked structure 111 in the step region 12; a dummy channel structure 122 is formed in the dummy channel via, and the dummy channel structure 122 is used to support the stack structure when the sacrificial layer 103 is subsequently removed.

The formation step of the memory structure 119 and the formation step of the dummy channel structure 122 may be performed simultaneously, and the dummy channel via 122 may be filled with the same structure as the channel via.

In other embodiments, the step of forming the memory structure 119 and the step of forming the dummy channel structure 122 may be separate, and the memory structure may be formed first, and the dummy channel via is filled through the via sacrificial layer when the memory structure is formed, and after the memory structure is formed, the via sacrificial layer is removed, and then the dummy channel structure is formed in the dummy channel via, so that after the memory structure 119 is formed, the film structures of the memory structure 119 are formed without removing the dummy channel via filling, and then the dummy channel structure is formed in the dummy channel via, thereby simplifying the process steps. In other embodiments, the dummy channel structure 122 may be formed first and then the memory structure 119 may be formed.

In an embodiment, at the boundary between the mesa region 12 and the core region 11, the density of the dummy channel structures 122 and the dummy channel vias in the mesa region 12 is less than the density of the channel vias and the memory structures 119 in the core region 11. It should be noted that the density in this embodiment refers to an area occupied by a pattern in a range of areas, for example, the density of the dummy channel structures 122 (or dummy channel vias) refers to an area occupied by the dummy channel structures 122 (or dummy channel vias) in a stacked structure with a certain area, and the density of the memory structures 119 (or channel vias) refers to an area occupied by the memory structures 119 (or channel vias)) in a stacked structure with a certain area.

In one embodiment, referring to fig. 10 and 11, fig. 10 is performed on the basis of fig. 8, after forming the memory structure 119 (and the dummy channel structure 122), forming a capping layer 109 (see fig. 10) on the stacked structure 111; an opening 110 (refer to fig. 11) exposing the surface of the filling layer 108 is formed in the capping layer 109.

The covering layer 109 is used as a top isolation layer of the storage structure 119 and the gate spacer formed in the channel through hole, and is mainly used for protecting the formed storage structure 119 and avoiding damage to the storage structure 119 caused by subsequent processes such as planarization or ion etching during forming of the gate spacer; the capping layer 109 may also serve as a mask for subsequent removal of the fill layer 108.

In one embodiment, the material of the capping layer 109 may be silicon oxide, or other suitable mask material different from the filling layer and the sacrificial layer.

In another embodiment, the cover layer 109 may be a single layer or a stacked structure of multiple layers.

In one embodiment, the opening 110 formed in the capping layer 109 has sidewalls that are inclined outward, and the size of the bottom of the opening 110 is equal to or greater than the size of the gate spacer, so as to ensure that the filling layer on the upper portion of the gate spacer can be completely removed; on the other hand, when the position of the sacrificial layer is subsequently removed to form the control gate and the array common source is formed in the gate separation groove, the material layer is prevented from closing the opening of the gate separation groove in advance, and the control gate and the array common source cannot be filled.

Referring to fig. 12 and 13, fig. 12 is performed on the basis of fig. 11, and after forming the memory structure 119, the filling layer is removed to expose the gate spacer 107; the sacrificial layer 103 is removed.

In this embodiment, the filling layer 108 is removed along the opening 110 (refer to fig. 11), and the removal of the filling layer 108 and the removal of the sacrificial layer 103 may be performed in the same wet etching process, where an etching solution adopted in the wet etching process is hot phosphoric acid.

The sacrificial layer 103 is removed while removing the bottom selection gate sacrificial layer 105 and the top selection gate sacrificial layer 106 (refer to fig. 12).

In other embodiments, when the material of the filling layer 108 is different from the material of the sacrificial layer 103, the filling layer 108 is removed first, and then the sacrificial layer 103 is removed along the exposed gate isolation trench, and different etching solutions are used for removing the filling layer 108 and the sacrificial layer 103.

Referring to fig. 14, a control gate 133 is formed at a position where the sacrificial layer 103 (refer to fig. 13) is removed; an array common source 123 is formed in the gate spacer 107 (refer to fig. 13).

In this embodiment, the control gate 133 is formed at the position where the sacrificial layer 103 is removed, the top select gate 131 is formed at the position where the top select gate sacrificial layer 106 (refer to fig. 12) is removed, and the bottom select gate 132 is formed at the position where the bottom select gate sacrificial layer 105 (refer to fig. 12) is removed.

The control gate 133, the top selection gate 131 and the bottom selection gate 132 both include a gate dielectric layer and a gate electrode on the gate dielectric layer, in this embodiment, the gate dielectric layer is made of a high-K dielectric material, and the gate electrode is made of a metal. The K dielectric material is HfO₂、TiO₂、HfZrO、HfSiNO、Ta₂O₅、ZrO₂、ZrSiO₂、Al₂O₃、SrTiO₃Or BaSrTiO. The metal is one or more of W, Al, Cu, Ti, Ag, Au, Pt and Ni.

After the control gate 133 is formed, the array common source 123 is formed in the gate spacer.

The array common source 123 is made of polysilicon or metal. In an embodiment, the array common source 141 may include a polysilicon layer and a metal layer on the polysilicon layer.

In an embodiment, before the array common source 123 is formed, an isolation side wall 124 is further formed on a side wall of the gate spacer, and a material of the isolation side wall 124 may be one or both of silicon oxide and silicon nitride.

In an embodiment, the specific process of forming the control gate 133 and the array common source 123 includes: removing the sacrificial layers in the stacked structure to form a plurality of cavities; forming a gate dielectric material layer on the side walls of the gate isolation groove and the cavity; forming a gate electrode material layer on the gate dielectric layer; etching back to remove the gate electrode material layer and the gate dielectric material layer on the side wall and the bottom surface of the gate isolation groove, and forming a control gate 133 in the cavity; forming isolation spacers 124 on sidewalls of the gate spacers 107 and sidewalls of the openings 110 (see fig. 13); an array common source 123 is formed in the gate spacer between the isolation spacers 124, and the array common source 123 fills the gate spacer 107 and the opening 110.

Fig. 15-33 are schematic structural diagrams of a 3D NAND forming process according to a second embodiment of the present invention, where a portion of a structure similar to or the same as that in the first embodiment is defined in the second embodiment, and other definitions or descriptions of the structure similar to or the same as that in the first embodiment in the second embodiment are not repeated in the second embodiment, and specific reference is made to the definitions or descriptions of corresponding portions in the first embodiment.

Referring to fig. 15-19, fig. 16 is a schematic cross-sectional structure view along a direction of a cutting line CD of fig. 15, fig. 17 is a schematic cross-sectional structure view along a direction of a cutting line GH of fig. 15, fig. 18 is a schematic cross-sectional structure view along a direction of a cutting line EF of fig. 15, fig. 19 is a schematic cross-sectional structure view along a direction of a cutting line AB of fig. 15, a semiconductor substrate 100 is provided, a stacked structure 111 in which a sacrificial layer 103 and an isolation layer 104 are alternately stacked is formed on the semiconductor substrate 100, the stacked structure 111 includes a core region 11 and a step region 12 located on one side of the core region 11, the stacked structure 111 further includes a plurality of gate isolation groove regions 22, the gate isolation groove regions 22 cross over the core region 11 and the step region 12, the core region 11 on both sides of the gate isolation groove regions 22 has a channel via adjusting region 14, the step regions 12 on both sides of the gate isolation groove regions 22, and the channel through hole adjusting region 14 and the dummy channel through hole adjusting region 13 are in contact and are respectively located at both sides of the interface of the core region 11 and the stepped region 12.

The channel through hole adjusting region 14 is a partial region in the core region 11, the pseudo channel through hole adjusting region 13 is a partial region in the step region 12, the channel through hole adjusting region 14 is in contact with the pseudo channel through hole adjusting region 13, and the two contacted channel through hole adjusting regions 14 and the two contacted pseudo channel through hole adjusting regions 13 are respectively positioned on two sides of an interface of the core region 11 and the step region 12. In an embodiment, the number of the channel via adjustment regions 14 and the dummy channel via adjustment regions 13 may be multiple, and on the interface between the core region 11 and the step region 12, one channel via adjustment region 14 is distributed in the core region 11 on both sides of each gate spacer region 22, and on the interface between the core region 11 and the step region 12, one dummy channel via adjustment region 13 is distributed in the step region 12 on both sides of each gate spacer region 22.

Referring to fig. 20 to 24, fig. 21 is a schematic cross-sectional view taken along a direction of a cutting line CD in fig. 20, fig. 22 is a schematic cross-sectional view taken along a direction of a cutting line GH in fig. 20, fig. 23 is a schematic cross-sectional view taken along a direction of a cutting line EF in fig. 20, and fig. 24 is a schematic cross-sectional view taken along a direction of a cutting line AB in fig. 20, wherein a plurality of dummy channel vias 113 are formed in the dummy channel via adjustment regions 13 and the step regions 12 outside the dummy channel via adjustment regions 13; a plurality of channel vias 112 are formed in the channel via adjustment region 14 and the core region 11 outside the channel via adjustment region 14, the density of channel vias 112 in the channel via adjustment region 14 being less than the density of channel vias 112 in the core region 11 outside the channel via adjustment region 14, such that the difference between the density of dummy channel vias 113 in the dummy channel via adjustment region 13 and the density of channel vias 112 in the channel via adjustment region 14 is reduced.

Research finds that the density of the pseudo channel through holes and the pseudo channel structures at the junction of the step area and the core area is greatly different from that of the channel through holes and the storage structures (the density of the pseudo channel through holes and the pseudo channel structures in the step area near the junction of the step area and the core area is far smaller than that of the channel through holes and the storage structures in the core area near the junction), so that the stress of films in the stacked structures at two sides or near the junction of the step area and the core area is greatly different, and therefore when the stacked structures at the junction of the step area and the core area are etched to form the gate separation groove, the side wall of the gate separation groove at the junction of the step area and the core area is easily inclined under the influence of the stress difference at two sides of the junction. In the present embodiment, therefore, by making the density of the channel vias 112 formed in the channel via adjustment region 14 smaller than the density of the channel vias 112 formed in the core region 11 outside the channel via adjustment region 14, so that the difference between the density of the dummy channel vias 113 formed in the dummy channel via adjustment region 13 and the density of the channel vias 112 formed in the channel via adjustment region 14 is reduced, and correspondingly, the dummy channel structures are subsequently formed in the dummy channel vias 113, and when the memory structures are formed in the channel vias 112, the density of the memory structures in the channel vias 112 in the channel via adjustment region 14 is smaller than the density of the memory structures in the channel vias 112 in the core region 11 outside the channel via adjustment region 14, so that the difference between the density of the dummy channel structures in the dummy channel vias 113 in the dummy channel via adjustment region 13 and the density of the memory structures in the channel vias 112 in the channel via adjustment region 14 is reduced, therefore, the difference of the stress of the film in the stacked structure 111 on two sides of or near the boundary of the stepped region 12 and the core region 11 is reduced, and when the gate spacer is formed by etching the stacked structure at the boundary of the stepped region and the core region, the sidewall of the gate spacer etched at the boundary of the stepped region and the core region is not inclined or the inclination is greatly reduced, so that the gate spacer is prevented from being short-circuited with the channel through hole. Moreover, since only the density of the channel vias 112 in the channel via adjustment region 14 is changed, the density of the channel vias 112 in other parts of the core region remains unchanged from the prior art, and thus the influence on the prior design and manufacturing process is not negligible.

In one embodiment, the density of the trench vias 14 at different locations in the trench via adjustment region 14 remains uniform. Specifically, the density of the storage structures in the channel via 112 in the channel via adjustment region 14 is less than the density of the storage structures in the channel via 112 in the core region 11 outside the channel via adjustment region 14, and the density of the channel via 112 in the channel via adjustment region 14 is equal to the density of the dummy channel via 113 in the dummy channel via adjustment region 13.

In another embodiment, the density of the storage structures in the channel vias 112 in the channel via adjustment region 14 is less than the density of the storage structures in the channel vias 112 in the core region 11 outside the channel via adjustment region 14, and the absolute value of the difference between the density of the channel vias 112 in the channel via adjustment region 14 and the density of the dummy channel vias 113 in the dummy channel via adjustment region 13 is less than a density threshold. The density threshold is a maximum value of a difference between the density of the channel via 112 in the channel via-adjusting region 14 and the density of the dummy channel via 113 in the dummy channel via-adjusting region 13 when no tilt defect is formed on the sidewall of the gate spacer at the boundary between the core region 11 and the step region 12 when the gate spacer is formed. Specifically, the density threshold may be obtained experimentally or set empirically.

In an embodiment, the density of the storage structures in the channel via 112 in the channel via adjustment region 14 is less than the density of the storage structures in the channel via 112 in the core region 11 outside the channel via adjustment region 14, and the density of the channel via 14 in the channel via adjustment region 14 gradually decreases from the core region 11 to the step region 12. Specifically, the density value of the channel through holes 14 in the channel through hole adjustment region 14 is decreased from the density value of the channel through holes 14 in the core region outside the channel through hole adjustment region 14 to the density value of the dummy channel through holes 113 in the dummy channel through hole adjustment region 13 in the direction in which the density value of the channel through holes 14 points from the core region 11 to the step region 12, so that the stress in the film layer near the interface between the core region 11 and the step region 12 is increased or decreased without sudden change, and the sidewall of the gate spacer formed near the interface between the core region 11 and the step region 12 is further prevented from being inclined.

It should be noted that, when the memory structures are subsequently formed in the trench vias 112 in the trench via adjustment region 14, the density distribution and arrangement of the memory structures in the trench via adjustment region 14 are the same as those in the trench via adjustment region 14. When a dummy channel structure is subsequently formed in the dummy channel via 113 in the dummy channel via adjustment region 13, the density distribution and arrangement of the dummy channel structure in the dummy channel via adjustment region 13 are the same as those of the dummy channel via 113 in the dummy channel via adjustment region 13.

It should be noted that, in this embodiment and subsequent embodiments, the density of the dummy channel vias (or the density of the dummy channel structures) in the dummy channel via adjustment region refers to an area occupied by the density of all dummy channel vias (or the density of the dummy channel structures) in the dummy channel via adjustment region with a certain area, and the density of the channel vias (or the density of the memory structures) in the channel via adjustment region refers to an area occupied by all channel vias (or the memory structures) in the channel via adjustment region with a certain area.

Referring to fig. 25-29, fig. 26 is a schematic cross-sectional view taken along a cutting line CD of fig. 25, fig. 27 is a schematic cross-sectional view taken along a cutting line GH of fig. 25, fig. 28 is a schematic cross-sectional view taken along a cutting line EF of fig. 25, and fig. 29 is a schematic cross-sectional view taken along a cutting line AB of fig. 25, wherein a dummy channel structure 122 is formed in the dummy channel via; a memory structure 119 is formed in the trench via.

Forming dummy channel structures 122 in the dummy channel vias, after forming the memory structures 119 in the channel vias, the density of the memory structures 119 in the channel vias in the corresponding channel via adjustment region 14 being less than the density of the memory structures 119 in the channel vias in the core region 11 outside the channel via adjustment region 14, such that the difference between the density of the dummy channel structures 122 in the dummy channel vias in the dummy channel via adjustment region 13 and the density of the memory structures 119 in the channel vias in the channel via adjustment region 14 is reduced.

In this embodiment, the dummy channel structure 122 and the memory structure 119 have the same structure, and the dummy channel structure 122 and the memory structure 119 are formed in the same process step.

In other embodiments, the dummy channel structure 122 is different from the structure of the memory structure 119, and the material hardness of the dummy channel structure 122 is greater than the material hardness of the memory structure 119, and since the density of channel vias 112 in the channel via accommodating region 14 is less than the density of channel vias 112 in the core region 11 outside the channel via accommodating region 14, so that the difference between the density of dummy channel vias 113 in the dummy channel via adjustment region 13 and the density of channel vias 112 in the channel via adjustment region 14 is reduced, thereby making it easier and even further reduced to thereby make the difference in stress of the films in stacked structure 111 on both sides or near the intersection of stepped region 12 and core region 11, therefore, when the gate separation groove is formed in the stacked structure at the boundary of the etching step area and the core area, the effect that the side wall of the gate separation groove at the boundary of the etching step area and the core area cannot incline or the inclination is greatly reduced is better.

Referring to fig. 30-32, fig. 31 is a schematic cross-sectional view taken along the cutting line CD of fig. 30, after the dummy channel structure 122 and the memory structure 119 are formed, a gate spacer 107 is formed in the gate spacer region 22 to traverse the core region 11 and the step region 12.

The gate spacer 107 penetrates the stacked structure 111 in a vertical direction.

Referring to fig. 32 and 33, fig. 33 is a schematic cross-sectional view of fig. 32 along the direction of the cutting line CD, after forming the gate isolation trench, removing the sacrificial layer, and forming a control gate 133 at the position where the sacrificial layer is removed; after forming the control gate 133, the array common source 123 is formed in the gate spacer.

The bottom selection gate sacrificial layer 105 and the top selection gate sacrificial layer 106 are simultaneously removed when the sacrificial layer 103 (refer to fig. 31) is removed.

A control gate 133 is formed at a position where the sacrificial layer 103 is removed, a top selection gate 131 is formed at a position where the top selection gate sacrificial layer 106 (refer to fig. 31) is removed, and a bottom selection gate 132 is formed at a position where the bottom selection gate sacrificial layer 105 (refer to fig. 31) is removed.

In an embodiment, before the array common source 123 is formed, an isolation sidewall spacer 124 is further formed on the sidewall of the gate spacer.

The second embodiment of the present invention also provides a 3D NAND memory, referring to fig. 32 and 33, including:

a semiconductor substrate 100, wherein a stacked structure 111 formed by alternately stacking control gates 133 and isolation layers 104 is formed on the semiconductor substrate 100, the stacked structure 111 includes a core region 11 and a step region 12 located on one side of the core region 11, the stacked structure 111 further includes a plurality of gate isolation groove regions 22, the gate isolation groove regions 22 cross over the core region 11 and the step region 12, channel via adjusting regions 14 are provided in the core region 11 on both sides of the gate isolation groove regions 22, dummy channel via adjusting regions 13 are provided in the step regions 12 on both sides of the gate isolation groove regions 22, and the channel via adjusting regions 14 and the dummy channel via adjusting regions 13 are in contact and located on both sides of an interface between the core region 11 and the step regions 12 respectively;

a plurality of dummy channel through holes in the step region 12 outside the dummy channel through hole adjusting region 13 and the dummy channel through hole adjusting region;

a plurality of channel vias located in the channel via adjustment region 14 and the core region 11 outside the channel via adjustment region, the density of channel vias in the channel via adjustment region 14 being less than the density of channel vias in the core region 11 outside the channel via adjustment region, such that the difference between the density of dummy channel vias in the dummy channel via adjustment region 13 and the density of channel vias in the channel via adjustment region 14 is reduced;

a dummy channel structure 122 in the dummy channel via;

a memory structure 119 located in the trench via;

gate spacers crossing the core region and the step region in the gate spacer region 22;

an array common source 123 located in the gate spacer.

Accordingly, the density of the memory structures 119 in the channel vias in the channel via adjustment region 14 is less than the density of the memory structures 119 in the channel vias in the core region 11 outside the channel via adjustment region, so that the difference between the density of the dummy channel structures 122 in the dummy channel vias in the dummy channel via adjustment region 13 and the density of the memory structures 119 in the channel vias in the channel via adjustment region 14 is reduced.

In one embodiment, the density of the channel via in the channel via adjustment region gradually decreases from the core region toward the step region.

In one embodiment, the density of the channel vias in the channel via adjustment region is equal to the density of the dummy channel vias in the dummy channel via adjustment region, or an absolute value of a difference between the density of the channel vias in the channel via adjustment region and the density of the dummy channel vias in the dummy channel via adjustment region is less than a density threshold.

And the density threshold is the maximum value of the difference value between the density of the channel through holes in the channel through hole adjusting region and the density of the pseudo channel through holes in the pseudo channel through hole adjusting region when the inclined defect cannot be formed on the side wall of the gate separation groove at the junction of the core region and the step region when the gate separation groove is formed.

In one embodiment, the dummy channel structure and the memory structure are identical in structure.

In one embodiment, the dummy channel structure and the memory structure are different in structure, and the material hardness of the dummy channel structure is greater than that of the memory structure.

The memory structure includes a charge storage layer on a sidewall surface of the channel via and a channel layer on a sidewall surface of the charge storage layer.

In one embodiment, the charge storage layer includes a blocking layer on a sidewall surface of the trench via, a charge trapping layer on a sidewall surface of the blocking layer, and a tunneling layer on a sidewall surface of the charge trapping layer.

FIGS. 34-36 are schematic structural diagrams illustrating a 3D NAND formation process according to a third embodiment of the present invention. The main differences between the third embodiment and the second embodiment are: the density of channel through holes in the channel through-hole regulation region is smaller than the density of channel through holes in the core region outside the channel through-hole regulation region in the second embodiment, so that the difference between the density of dummy channel through holes in the dummy channel through-hole regulation region and the density of channel through holes in the channel through-hole regulation region is reduced, while the density of dummy channel through holes in the dummy channel through-hole regulation region is larger than the density of dummy channel through holes in the step region outside the dummy channel through-hole regulation region in the third embodiment, so that the difference between the density of dummy channel through holes in the dummy channel through-hole regulation region and the density of channel through holes in the channel through-hole regulation region is reduced, and the other portions of the 3D NAND memory and the entire formation process of the 3D NAND memory in the third embodiment are substantially the same as the other portions of the 3D NAND memory and the entire formation process of the 3D NAND memory in the second embodiment, therefore, the following third embodiment only describes the foregoing main differences, and please refer to the definition or description of the corresponding parts of the second and third embodiments for the other parts of the 3D NAND memory and the whole forming process of the 3D NAND memory.

Referring to fig. 34-36, fig. 34 is similar to fig. 20 in the second embodiment, fig. 35 is similar to fig. 30 in the second embodiment, fig. 36 is similar to fig. 32 in the second embodiment, and provides a semiconductor substrate having a stacked structure in which sacrificial layers and isolation layers are alternately stacked, the stacked structure includes a core region 11 and a step region 12 at one side of the core region 11, the stacked structure further includes a plurality of gate spacer regions 22, the gate spacer region 22 crosses over the core region 11 and the step region 12, the core region 11 on both sides of the gate spacer region 22 has a channel via adjustment region 14 therein, the step regions 12 on both sides of the gate spacer region 22 also have dummy channel via adjustment regions 13 therein, the channel through hole adjusting region 14 is in contact with the pseudo channel through hole adjusting region 13 and is respectively positioned at two sides of the interface of the core region 11 and the step region 12;

forming a plurality of channel through holes 112 in the channel through hole adjusting region 14 and the core region 11 outside the channel through hole adjusting region 14;

forming a plurality of dummy channel via holes 113 in the dummy channel via hole adjusting region 13 and the stepped region 12 outside the dummy channel via hole adjusting region 13, the density of the dummy channel via holes 113 in the dummy channel via hole adjusting region 13 being greater than the density of the dummy channel via holes 113 in the stepped region 12 outside the dummy channel via hole adjusting region 13, so that a difference between the density of the dummy channel via holes 113 in the dummy channel via hole adjusting region 13 and the density of the channel via holes 112 in the channel via hole adjusting region 14 is reduced;

forming a dummy channel structure 122 in the dummy channel via (refer to fig. 36);

forming a memory structure 119 in the trench via (refer to fig. 36);

after the dummy channel structure 122 and the memory structure 119 are formed, gate spacers 107 (refer to fig. 36) crossing the core region and the step region are formed in the gate spacer region.

In the present embodiment, by making the density of the dummy channel via holes 113 in the dummy channel via adjustment region 13 greater than the density of the dummy channel via holes 113 in the stepped region 12 outside the dummy channel via adjustment region 13, so that the difference between the density of the dummy channel via holes 113 in the dummy channel via adjustment region 13 and the density of the channel via holes 112 in the channel via adjustment region 14 is reduced, correspondingly, a dummy channel structure is formed in the dummy channel via holes 113, and when a memory structure is formed in the channel via holes 112, the density of the dummy channel structures 122 in the dummy channel via holes in the dummy channel via adjustment region 13 is made greater than the density of the dummy channel structures 122 in the dummy channel via holes in the stepped region outside the dummy channel via adjustment region 13, so that the difference between the density of the dummy channel structures 122 in the dummy channel via holes in the dummy channel via adjustment region 13 and the density of the memory structures 119 in the channel via adjustment region 13 is reduced, therefore, the difference of the stress of the film in the stacked structure 111 on two sides of or near the boundary of the stepped region 12 and the core region 11 is reduced, and when the gate spacer is formed by etching the stacked structure at the boundary of the stepped region and the core region, the sidewall of the gate spacer etched at the boundary of the stepped region and the core region is not inclined or the inclination is greatly reduced, so that the gate spacer is prevented from being short-circuited with the channel through hole. Moreover, since only the density of the channel vias 112 in the channel via adjustment region 14 is changed, the density of the channel vias 112 in other parts of the core region remains unchanged from the prior art, and thus the influence on the prior design and manufacturing process is not negligible.

In an embodiment, the density of the dummy channel vias 113 in the dummy channel via adjustment region 13 is greater than the density of the dummy channel vias 113 in the step region 12 outside the dummy channel via adjustment region 13, and the density of the channel vias 113 in the channel via adjustment region 14 is equal to the density of the dummy channel vias 112 in the dummy channel via adjustment region 13, or an absolute value of a difference between the density of the channel vias 113 in the channel via adjustment region 14 and the density of the dummy channel vias 112 in the dummy channel via adjustment region 13 is less than a density threshold.

In an embodiment, the density of the dummy channel vias 113 in the dummy channel via adjustment region 13 is greater than the density of the dummy channel vias 113 in the stepped region 12 outside the dummy channel via adjustment region 13, and the density of the dummy channel vias 113 in the dummy channel via adjustment region 13 gradually increases in a direction from the stepped region 12 toward the core region 11.

In an embodiment, the density of the dummy channel vias 113 in the dummy channel via adjustment region 13 is greater than the density of the dummy channel vias 113 in the stepped region 12 outside the dummy channel via adjustment region 13, and the density of the channel vias 112 in the channel via adjustment region 14 is less than the density of the channel vias 14 in the core region outside the channel via adjustment region 14.

In one embodiment, the density of dummy channel vias in the dummy channel via adjustment region is greater than the density of dummy channel vias in the step region outside the dummy channel via adjustment region, such that a difference between the density of dummy channel vias in the dummy channel via adjustment region and the density of channel vias in the channel via adjustment region is reduced, and the dummy channel structure and the memory structure are structurally different, the material hardness of the dummy channel structure being greater than the material hardness of the memory structure.

In one embodiment of the present invention, the substrate is,

referring to fig. 26, after forming the gate isolation trench, removing the sacrificial layer, and forming a control gate at the position where the sacrificial layer is removed; after forming the control gate, an array common source 123 is formed in the gate spacer.

The third embodiment of the present invention also provides a 3D NAND memory, including:

the semiconductor device comprises a semiconductor substrate, wherein a stacked structure with control gates and isolation layers stacked alternately is formed on the semiconductor substrate, the stacked structure comprises a core region and a step region located on one side of the core region, the stacked structure further comprises a plurality of gate separating groove regions, the gate separating groove regions cross the core region and the step region, channel through hole adjusting regions are arranged in the core region on two sides of the gate separating groove regions, pseudo channel through hole adjusting regions are arranged in the step regions on two sides of the gate separating groove regions, and the channel through hole adjusting regions are in contact with the pseudo channel through hole adjusting regions and are located on two sides of an interface of the core region and the step region respectively;

a plurality of channel vias located in the channel via adjustment region and the core region outside the channel via adjustment region;

a plurality of dummy channel through holes located in the dummy channel through hole adjustment region and in the step region outside the dummy channel through hole adjustment region, the density of the dummy channel through holes in the dummy channel through hole adjustment region being greater than the density of the dummy channel through holes in the step region outside the dummy channel through hole adjustment region, so that a difference between the density of the dummy channel through holes in the dummy channel through hole adjustment region and the density of the channel through holes in the channel through hole adjustment region is reduced;

a dummy channel structure in the dummy channel via;

a memory structure located in the trench via;

the grid separating groove is positioned in the grid separating groove region and transversely penetrates through the core region and the step region;

an array common source located in the gate spacer.

Correspondingly, the density of the pseudo channel structures in the pseudo channel through holes in the pseudo channel through hole adjusting region is greater than that of the pseudo channel structures in the pseudo channel through holes in the step region outside the pseudo channel through hole adjusting region, so that the difference between the density of the pseudo channel structures in the pseudo channel through holes in the pseudo channel through hole adjusting region and the density of the storage structures in the channel through holes in the channel through hole adjusting region is reduced.

In one embodiment, the density of the dummy channel via holes in the dummy channel via adjustment region gradually increases from the step region toward the core region.

In one embodiment, the density of channel vias in the channel via accommodating region is less than the density of channel vias in the core region outside the channel via accommodating region.

The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.

Claims

1. A method for forming a 3D NAND memory, comprising:

forming a filling layer in the grid electrode isolation groove, wherein the grid electrode isolation groove is filled with the filling layer, and the material of the filling layer is different from that of the isolation layer;

forming a storage structure in the trench via;

forming an array common source in the gate spacer.

2. The method of claim 1, wherein the stacked structure comprises a core region and a step region on one side of the core region, the gate spacer traverses the core region and the step region, and the channel via is in the step region.

3. The method of forming a 3D NAND memory of claim 2 wherein after the gate spacer and the filling layer are formed, dummy channel vias are formed in the step regions, the dummy channel vias being located in the step regions on both sides of the gate spacer; a dummy channel structure is formed in the dummy channel via.

4. The method of forming a 3D NAND memory of claim 3, wherein at an intersection of a terrace region and a core region, a density of the dummy channel structures and dummy channel vias in the terrace region is less than a density of the channel vias and memory structures in the core region.

5. The method of forming a 3D NAND memory of claim 1, wherein the material of the filling layer is the same as the material of the sacrificial layer.

6. The method of forming a 3D NAND memory as claimed in claim 1, wherein after forming the memory structure, a capping layer is formed on the stacked structure; forming an opening in the covering layer to expose the surface of the filling layer; and removing the filling layer along the opening.

7. The method of claim 6, wherein the opening has outwardly sloped sidewalls, and wherein a bottom of the opening has a size equal to or greater than a size of the gate spacer.

8. The method of forming a 3D NAND memory of claim 1 wherein the memory structure includes a charge storage layer on a sidewall surface of the channel via and a channel layer on a sidewall surface of the charge storage layer.

9. The method of forming a 3D NAND memory of claim 8 wherein the charge storage layer comprises a blocking layer on sidewall surfaces of the trench via, a charge trapping layer on sidewall surfaces of the blocking layer, and a tunneling layer on sidewall surfaces of the charge trapping layer.

10. The method of forming a 3D NAND memory as claimed in claim 1, wherein after removing the filling layer, the sacrificial layer in the stack structure is removed along the gate spacer.

11. The method of forming a 3D NAND memory of claim 10 wherein an array common source is formed in the gate spacer after the control gate is formed.